JP2978533B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JP2978533B2
JP2978533B2 JP2155228A JP15522890A JP2978533B2 JP 2978533 B2 JP2978533 B2 JP 2978533B2 JP 2155228 A JP2155228 A JP 2155228A JP 15522890 A JP15522890 A JP 15522890A JP 2978533 B2 JP2978533 B2 JP 2978533B2
Authority
JP
Japan
Prior art keywords
bonding wire
signal line
package
metallization
gnd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2155228A
Other languages
English (en)
Other versions
JPH0448756A (ja
Inventor
雅彦 西馬
千代士 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2155228A priority Critical patent/JP2978533B2/ja
Priority to US07/715,068 priority patent/US5225709A/en
Publication of JPH0448756A publication Critical patent/JPH0448756A/ja
Application granted granted Critical
Publication of JP2978533B2 publication Critical patent/JP2978533B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半島体集積回路装置に関し、特い超高速デ
バイス用ICパッケージのインピーダンス整合に適用して
有効な技術に関するものである。
〔従来の技術〕
GHz帯の高周波で動作するGaAs（ガリウムヒ素）ICな
どの超高速デバイスは、その入力インピーダンスと信号
伝送線路の特性インピーダンスとを整合させる必要があ
る。これは、高周波信号を伝送する際に信号伝送線路の
特性インピーダンスが不整合であると、信号の反射や波
形歪などの伝送ロスが生じて回路の正常な動作が妨げら
れるからである。そのため、超高速デバイスを搭載する
ICパッケージは、パッケージ内の信号線の特性インピー
ダンスの値が信号源のインピーダンスの置と一致するよ
うに設計される。なお、超高速デバイス用ICパッケージ
については、株式会社サイエンスフォーラム（昭和61年
３月15日）発行の「高密度実装技術ハンドブック」P352
に記載がある。
〔発明が解決しようとする課題〕
ところが、従来の超高速デバイス用ICパッケージは、
パッケージ内の信号線と半導体チップとを接続するボン
ディングワイヤのインピーダンス整合については充分な
配慮がなされていないため、デバイスの動作周波数が高
くなるにつれて、ボンディングワイヤのインピーダンス
不整合に起因する信号の伝送ロスが無視できなくなって
きた。
本発明は、上記した問題点に着目してなされたもので
あり、その目的は超高速デバイス用ICパッケージのボン
ディングワイヤの特性インピーダンスをパッケージ内の
信号線の特性インピーダンスと整合させる技術を提供す
ることにある。
本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述および添付図面から明らかになるであろ
う。
なお、特開昭63−228723号公報には、例えばその第１
図に、半導体チップ１上およびパッケージ２上で１本の
信号線31、32に対してその両側に接地線41、43、42、44
を同一平面上に設け、半導体チップ上とパッケージ上の
信号線同士および接地線同士をボンディングワイヤで電
気的に接続することにより、半導体チップ上とパッケー
ジ上の信号線31、32の特性インピーダンスを同一にした
半導体装置が開示されている。また、その第３図に、３
本のボンディングワイヤ51、52、53を誘電体の保持部11
により一体的に固定してそれからの相互の間隔が一定な
コプレーナ構造とし、ボンディングワイヤ51が半導体チ
ップ上およびパッケージ上の信号線31、32と同じ特性イ
ンピーダンスを呈するようにした例が示されている。
特開平２−72654号公報には、例えばその第１図およ
び第２図に、パッケージの端子の中の特性の端子10a
を、ICチップ収容のための空間を規定する枠部材４の内
壁4aに沿って延在させ、これをICチップ14を載せる導電
性のステージ８に電気的に接続することにより、ICパッ
ケージにおける漏話を抑制した半導体装置が開示されて
いる。
特開昭57−107059号公報には、例えばその第３図およ
び第４図に、ICチップ１を収納するパッケージの内部
に、ICチップ１の底部および側部の全面を包囲する接地
導体10を設けることにより、ノズルに対しICチップ１の
動作を安定化した半導体装置が開示されている。
〔課題を解決するための手段〕
本願において開示される発明のうち、代表的なものの
概要を簡単に説明すれば、次のとおりである。
本願の一発明は、半導体チップと信号線とを電気的に
接続するボンディングワイヤの近傍に定電位メタライズ
を配置したICパッケージである。
〔作用〕
上記した手段によれば、ボンディングワイヤの近傍に
定電位メタライズを配置したことにより、上記定電位メ
タライズとボンディングワイヤとの距離および両者を隔
てる物質の比誘電率を適当に選択することにより、ボン
ディングワイヤの特性インピーダンスの値を信号線の特
性インピーダンスの値と一致させることができる。
〔実施例〕
本発明の一実施例であるICパッケージを第１図および
第２図により説明する。第１図は、このICパッケージの
要部破断斜視図、第２図は断面図である。
ICパッケージ１は、いわゆるセラミックパッケージで
あり、アルミナなどからなる基板２、枠体３およびキャ
ップ４により隔成されたキャビティ５内には、例えば超
高速でスイッチング動作を行う論理ICを備えたGaAsチッ
プ６が搭載されている。
基板２の上面には、上記チップ６に高周波信号を伝送
する信号線７が設けられている。上記信号線７は、その
特性インピーダンスの値が信号源のインピーダンスの値
（例えば50Ω）と一致するように設計されている。信号
線７は、その一端がキャビティ５内に露出し、他端がパ
ッケージ外部に露出している。キャビティ５内に露出し
た信号線７と上記チップ６のボンディングパッド８と
は、Auなどからなるボンディングワイヤ９によって電気
的に接続されている。また、パッケージ外部に露出した
信号線７には、ICパッケージ１の外部端子を構成するリ
ード10が電気的に接続されている。上記リード10は、例
えば42アロイなどのFe系金属からなる。
基板２の上面には、信号線７と平行してGNDメタライ
ズ11aが設けられている。また、信号線７の上方の枠体
３内には、GNDメタライズ11bが設けられている。さら
に、信号線７の下方の基板２内には、GNDメタライズ11c
が設けられている。上記GNDメタライズ11cの一部は、キ
ャビティ４内に露出し、その上にAu−Sn共晶合金などの
ろう材12を介してチップ６が接合されている。上記GND
メタライズ11a、11b、11cは、基板２および枠体３に開
孔したスルーホール13を通じて電気的に接続されてい
る。すなわち、GNDメタライズ11a、11b、11cは、信号線
７をシールドするように配置されている。信号線７およ
びGNDメタライズ11a、11b、11cは、例えばＷ（タングス
テン）の厚膜印刷により形成される。
第１図に示すように、基板２の上面に設けられたGND
メタライズ11aは、信号線７の先端を囲むように配置さ
れている。すなわち、GNDメタライズ11aは、その一部が
ボンディングワイヤ９に近接するように配置されてい
る。また、ボンディングワイヤ９を良好にシールドする
ため、GNDメタライズ11aは、キャビティ５内の基板２の
側壁に設けられたGNDメタライズ11dを通じて下方のGND
メタライズ11cと電気的に接続されている。さらに、GND
メタライズ11aとボンディングワイヤ９との間には、ポ
リイミド樹脂などからなる絶縁体14が介装されている。
上記絶縁体14は、その厚さがボンディングワイヤ９のル
ープ高さと一致するように設計されているので、ボンデ
ィングワイヤ９とGNDメタライズ11aとの距離を一定に保
つように作用する。また、絶縁体14は、GNDメタライズ1
1aとボンディングワイヤ９との短絡を防止するように作
用する。
このように、本実施例のICパッケージ１は、ボンディ
ングワイヤ９の近傍にGNDメタライズ11aを配置し、かつ
それらの間に絶縁体14を介装したので、絶縁体14の厚さ
（すなわち、GNDメタライズ11aとボンディングワイヤ９
との距離）およびその材質（すなわち比誘電率）を適当
に選択することにより、ボンディングワイヤ９の特性イ
ンピーダンスの値を信号線７の特性インピーダンスの値
（50Ω）と一致させることができる。これにより、ICパ
ッケージ１内における信号の反射や波形歪が回避される
ので、高周波信号をロスなく伝送することができる。
以上、本発明者によってなされた発明を実施例に基づ
き具体的に説明したが、本発明は、前記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることはいうまでもない。
ボンディングワイヤとGNDメタライズとの間に介装す
る絶縁体は、絶縁性を有する材料であればよく、特に樹
脂に限定されるものではない。
ボンディングワイヤとGNDメタライズとの間に絶縁体
を介装する他の手段として、ボンディングワイヤを絶縁
性材料で被覆してもよい。
〔発明の効果〕
本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。
半導体チップと信号線とを電気的に接続するボンディ
ングワイヤの近傍に定電位メタライズを配置し、ボンデ
ィングワイヤの特性インピーダンスの値を信号線の特性
インピーダンスの値と一致させることにより、ボンディ
ングワイヤのインピーダンス不整合に起因する高周波信
号の伝送ロスを防止することができる。
【図面の簡単な説明】
第１図は、本発明の一実施例である半導体集積回路装置
の要部破断斜視図、 第２図は、この半導体集積回路装置の断面図である。 １……ICパッケージ、２……基板、３……枠体、４……
キャップ、５……キャビティ、６……GaAsチップ、７…
…信号線、８……ボンディングパッド、９……ボンディ
ングワイヤ、10……リード、11a,11b,11c,11d……GNDメ
タライズ、12……ろう材、13……スルーホール、14……
絶縁体。
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−125655（ＪＰ，Ａ) 特開 昭63−44745（ＪＰ，Ａ) 実開 昭62−145337（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/12

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】パッケージ内の半導体チップと信号線の一
    端とがボンディングワイヤにより電気的に接続されてい
    る半導体集積回路装置において、上記信号線と同一面上
    に、上記信号線から絶縁され、上記信号線の長さ方向
    に、上記ボンディングワイヤに相対する位置まで延在し
    て配置された上記ボンディングワイヤの特性インピーダ
    ンスを調節するための定電位メタライズを有しているこ
    とを特徴とする半導体集積回路装置。
  2. 【請求項２】上記定電位メタライズは上記ボンディング
    ワイヤと交差した部分を有しており、該交差部におい
    て、上記ボンディングワイヤと上記定電位メタライズの
    間に絶縁体が介在していることを特徴とする請求項１記
    載の半導体集積回路装置。
JP2155228A 1990-06-15 1990-06-15 半導体集積回路装置 Expired - Lifetime JP2978533B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2155228A JP2978533B2 (ja) 1990-06-15 1990-06-15 半導体集積回路装置
US07/715,068 US5225709A (en) 1990-06-15 1991-06-13 Package having a structure for stabilizing and/or impedance-matching a semiconductor IC device accommodated therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2155228A JP2978533B2 (ja) 1990-06-15 1990-06-15 半導体集積回路装置

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JPH0448756A JPH0448756A (ja) 1992-02-18
JP2978533B2 true JP2978533B2 (ja) 1999-11-15

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JPH0272654A (ja) * 1988-09-07 1990-03-12 Fujitsu Ltd Ｉｃパッケージ及びその接続構造
US5043794A (en) * 1990-09-24 1991-08-27 At&T Bell Laboratories Integrated circuit package and compact assemblies thereof

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US5225709A (en) 1993-07-06
JPH0448756A (ja) 1992-02-18

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