JP5387499B2 - 内部整合型トランジスタ - Google Patents
内部整合型トランジスタ Download PDFInfo
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- JP5387499B2 JP5387499B2 JP2010112248A JP2010112248A JP5387499B2 JP 5387499 B2 JP5387499 B2 JP 5387499B2 JP 2010112248 A JP2010112248 A JP 2010112248A JP 2010112248 A JP2010112248 A JP 2010112248A JP 5387499 B2 JP5387499 B2 JP 5387499B2
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
図1は、実施の形態1に係る内部整合型トランジスタを示す平面図である。ベース材10は導電性金属にAuメッキしたものであり、ベース材10全体がGND電位になっている。このベース材10の主面にV溝12,14が設けられている。ベース材10の主面は、V溝12とV溝14の間に存在する領域10aと、V溝12を挟んで領域10aと対向する領域10bと、V溝14を挟んで領域10aと対向する領域10cとを有する。ベース材10の領域10a上にトランジスタ16が半田接合されている。ベース材10の領域10b上に内部整合回路18が半田接合されている。ベース材10の領域10c上に内部整合回路20が半田接合されている。
図5は、実施の形態2に係る内部整合型トランジスタを示す拡大断面図である。実施の形態1の半田材26,28の代わりに、金ワイヤ22とV溝12の間まで非導電性(誘電性)の内部整合回路18の一部18aが張り出し、金ワイヤ24とV溝14の間まで非導電性(誘電性)の内部整合回路20の一部18bが張り出している。
図6は、実施の形態3に係る内部整合型トランジスタを示す拡大断面図である。実施の形態1の半田材26,28の代わりに、金ワイヤ22とV溝12の間に非導電性(誘電性)の樹脂材30が塗布され、金ワイヤ24とV溝14の間に非導電性(誘電性)の樹脂材32が塗布されている。
図7は、実施の形態4に係る内部整合型トランジスタを示す拡大断面図である。実施の形態1の半田材26,28の代わりに、トランジスタ16と内部整合回路18との間においてベース材10に2つのV溝12a,12bが形成され、トランジスタ16と内部整合回路20との間においてベース材10に2つのV溝14a,14bが形成されている。
図10は、実施の形態5に係る内部整合型トランジスタを示す拡大断面図である。実施の形態4の複数のV溝12a,12b,14a,14bの代わりに、第1溝34,36と第2溝38,40が形成されている。第1溝34は金ワイヤ22の下方においてベース材10に形成され、第2溝38は第1溝34の底部に形成されている。第1溝36は金ワイヤ24の下方においてベース材10に形成され、第2溝40は第1溝36の底部に形成されている。
図12は、実施の形態6に係る内部整合型トランジスタを示す拡大断面図である。実施の形態1のV溝12及び半田材26の代わりに、金ワイヤ22の下方においてベース材10に凸部42が設けられ、金ワイヤ24の下方においてベース材10に凸部44が設けられている。
12,12a,12b,12c,14,14a,14b,14c V溝(溝)
10a 領域(第1の領域)
10b,10c 領域(第2の領域)
16 トランジスタ
18 内部整合回路
22 金ワイヤ
26 半田材(材料)
30 樹脂材(材料)
34,36 第1溝
38,40 第2溝
42,44 凸部
Claims (6)
- 溝と、前記溝を挟んで対向する第1領域及び第2領域とを有する導電性のベース材と、
前記ベース材の前記第1領域上に接合されたトランジスタと、
前記ベース材の前記第2領域上に接合された内部整合回路と、
前記溝の上方を横切って、前記トランジスタと前記内部整合回路を接続するワイヤと、
前記ワイヤと前記溝の間に設けられた導電性又は非導電性の材料とを備え、
前記材料により前記ワイヤと前記ベース材との間の容量を調整することを特徴とする内部整合型トランジスタ。 - 前記材料は、前記溝に埋め込まれた半田材又は導電性樹脂であることを特徴とする請求項1に記載の内部整合型トランジスタ。
- 前記材料は、前記ワイヤと前記溝の間まで張り出した前記内部整合回路の一部であることを特徴とする請求項1に記載の内部整合型トランジスタ。
- 前記材料は、前記ワイヤと前記溝の間に塗布された樹脂材であることを特徴とする請求項1に記載の内部整合型トランジスタ。
- 複数の溝と、前記複数の溝を挟んで対向する第1領域及び第2領域とを有する導電性のベース材と、
前記ベース材の前記第1領域上に接合されたトランジスタと、
前記ベース材の前記第2領域上に接合された内部整合回路と、
前記複数の溝の上方を横切って、前記トランジスタと前記内部整合回路を接続するワイヤとを備え、
前記複数の溝により前記ワイヤと前記ベース材との間の容量を調整することを特徴とする内部整合型トランジスタ。 - 前記複数の溝は、第1溝と、前記第1溝の底部に形成された第2溝とを有することを特徴とする請求項5に記載の内部整合型トランジスタ。
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Application Number | Priority Date | Filing Date | Title |
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JP2010112248A JP5387499B2 (ja) | 2010-05-14 | 2010-05-14 | 内部整合型トランジスタ |
US13/025,589 US8217496B2 (en) | 2010-05-14 | 2011-02-11 | Internal matching transistor |
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JP2010112248A JP5387499B2 (ja) | 2010-05-14 | 2010-05-14 | 内部整合型トランジスタ |
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JP2011243643A JP2011243643A (ja) | 2011-12-01 |
JP5387499B2 true JP5387499B2 (ja) | 2014-01-15 |
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JP6565130B2 (ja) * | 2013-10-31 | 2019-08-28 | 三菱電機株式会社 | 増幅器 |
WO2019087699A1 (ja) * | 2017-11-02 | 2019-05-09 | ローム株式会社 | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0188505U (ja) * | 1987-12-04 | 1989-06-12 | ||
JPH0426145A (ja) * | 1990-05-22 | 1992-01-29 | Nec Corp | Icパッケージ |
JP2978533B2 (ja) * | 1990-06-15 | 1999-11-15 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH04154311A (ja) | 1990-10-18 | 1992-05-27 | Nec Corp | 電界効果トランジスタ装置 |
JPH04256206A (ja) * | 1991-02-07 | 1992-09-10 | Mitsubishi Electric Corp | Mmic化発振器 |
JPH05166960A (ja) * | 1991-12-18 | 1993-07-02 | Hitachi Ltd | 半導体装置の実装構造 |
JP3395290B2 (ja) | 1993-11-05 | 2003-04-07 | 三菱電機株式会社 | 高周波用回路基板 |
US5592122A (en) * | 1994-05-19 | 1997-01-07 | Matsushita Electric Industrial Co., Ltd. | Radio-frequency power amplifier with input impedance matching circuit based on harmonic wave |
JP4163818B2 (ja) * | 1999-07-07 | 2008-10-08 | 三菱電機株式会社 | 内部整合型トランジスタ |
WO2006097893A2 (en) | 2005-03-18 | 2006-09-21 | Nxp B.V. | Method and system for output matching of rf transistors |
JP2008035336A (ja) | 2006-07-31 | 2008-02-14 | Toshiba Corp | 高周波回路装置 |
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2010
- 2010-05-14 JP JP2010112248A patent/JP5387499B2/ja active Active
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2011
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US20110278700A1 (en) | 2011-11-17 |
JP2011243643A (ja) | 2011-12-01 |
US8217496B2 (en) | 2012-07-10 |
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