KR940022822A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR940022822A KR940022822A KR1019930004245A KR930004245A KR940022822A KR 940022822 A KR940022822 A KR 940022822A KR 1019930004245 A KR1019930004245 A KR 1019930004245A KR 930004245 A KR930004245 A KR 930004245A KR 940022822 A KR940022822 A KR 940022822A
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- KR
- South Korea
- Prior art keywords
- leads
- semiconductor
- semiconductor chips
- semiconductor chip
- package
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
이 발명은 반도체 패키지에서, 서로 크기가 다른 두개의 반도체 칩을 일정간격으로 형성되어 있는 리드들의 일측 상부 및 하부에 작고 큰 두개의 반도체 칩을 실장하거나, 리드들의 일측 상부에 두개의 반도체칩을 적층 절연실장하여 와이어로 리드들과 연결하였으므로, 모듈이나 IC카드등의 면적을 적게 차지하여 메모리 용량 및 실장 밀도를 향상시킬 수 있으며, 서로 동작이 다른 두개의 반도체칩을 리드의수를 증가시켜 하나의 패키지 몸체에 실장하였으므로, 모듈등의 실장밀도를 향상시킬 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 이 발명에 따른 반도체 패키지의 일실시예의 단면도, 제4도는 이 발명에 따른 반도체 패키지의 다른 실시예의 단면도이다.
Claims (6)
- 일정간격으로 형성되어 있는 리드들과; 상기 리드들의 일측상부에 실장되며, 상기 리드들과 제1와이어로 연결되는 제1반도체 칩과; 상기 제1반도체 칩보다 면적이 크며, 상기 리드들의 일측 하부에 실장되고, 상기 리드들과 중첩되지 않는 부분에 본딩패드들이 형성되어 있으며, 상기 리드들과 제2와이어로 연결되는 제2반도체 칩과; 상기 제1 및 제2반도체 칩과 제1 및 제2와이어를 감싸 보호하는 패키지 몸체를 구비하는 반도체 패키지.
- 제1항에 있어서, 상기 제1 및 제2반도체 칩이 폴리이미드테이프 및 절연 접착제로 이루어지는 군에서 임의로 선택되는 하나의 수단으로 실장되는 반도체 패키지.
- 제1항에 있어서, 상기 제1 및 제2반도체 칩이 동일한 동작을 수행하는 반도체 칩이거나 서로 다른 동작을 수행하는 반도체 칩인 반도체 패키지.
- 제3항에 있어서, 상기 제1 및 제2반도체 칩이 서로 다른 동작을 수행하는 반도체 칩이며 상기 리드들이 각각 하나의 반도체칩과만 연결되는 반도체 패키지.
- 일정간격으로 형성되어 있는 리드들과; 상기 리드들의 일측 상부에 절연실장되며, 상기 리드들과 제1와이어들로 연결되어 있는 제1반도체 칩과; 상기 제1반도체 칩 보다 면적이 작고, 상기 제1반도체 칩의 상부에 절연실장되며, 상기 리드들과 제2와이어들로 연결되어 있는 제2반도체 칩과; 상기 제1 및 제2반도체 칩과 제1 및 제2와이어를 감싸 보호하는 패키지 몸체를 구비하는 반도체 패키지.
- 제5항에 있어서, 상기 제1 및 제2반도체 칩이 동일한 동작을 수행하는 메모리용 반도체 칩이며 동일한 동작을 수행하는 본딩패드들은 동일한 리드와 연결되어 있는 반도체 패키지.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930004245A KR100235108B1 (ko) | 1993-03-19 | 1993-03-19 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930004245A KR100235108B1 (ko) | 1993-03-19 | 1993-03-19 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940022822A true KR940022822A (ko) | 1994-10-21 |
KR100235108B1 KR100235108B1 (ko) | 1999-12-15 |
Family
ID=19352434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930004245A KR100235108B1 (ko) | 1993-03-19 | 1993-03-19 | 반도체 패키지 |
Country Status (1)
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KR (1) | KR100235108B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100618541B1 (ko) * | 1999-07-06 | 2006-08-31 | 삼성전자주식회사 | 다층 반도체 칩 패키지 제작 방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7303137B2 (en) | 2005-02-04 | 2007-12-04 | Chun-Hsin Ho | Dual integrated circuit card system |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0750759B2 (ja) * | 1988-07-01 | 1995-05-31 | シャープ株式会社 | 半導体装置 |
JPH04142073A (ja) * | 1990-10-02 | 1992-05-15 | Nec Yamagata Ltd | 半導体装置 |
-
1993
- 1993-03-19 KR KR1019930004245A patent/KR100235108B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100618541B1 (ko) * | 1999-07-06 | 2006-08-31 | 삼성전자주식회사 | 다층 반도체 칩 패키지 제작 방법 |
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Publication number | Publication date |
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KR100235108B1 (ko) | 1999-12-15 |
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