JP2993480B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2993480B2
JP2993480B2 JP9283939A JP28393997A JP2993480B2 JP 2993480 B2 JP2993480 B2 JP 2993480B2 JP 9283939 A JP9283939 A JP 9283939A JP 28393997 A JP28393997 A JP 28393997A JP 2993480 B2 JP2993480 B2 JP 2993480B2
Authority
JP
Japan
Prior art keywords
wiring
semiconductor device
substrate
power supply
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9283939A
Other languages
English (en)
Other versions
JPH11121500A (ja
Inventor
幸二郎 渋谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9283939A priority Critical patent/JP2993480B2/ja
Publication of JPH11121500A publication Critical patent/JPH11121500A/ja
Application granted granted Critical
Publication of JP2993480B2 publication Critical patent/JP2993480B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、ワイヤボンディング技術を用いて基板上の配
線パターンと該基板上に固定された半導体チップとを電
気的に接続した半導体装置に関するものである。
【０００２】
【従来の技術】図５は従来のオーバーモールドタイプの
半導体装置の要部を示す平面図、図６は同半導体装置を
示す断面図であり、上面に配線パターンが配設された基
板１の中央部には、半導体チップ２が導電性ペースト３
を介して固定され、この半導体チップ２の上面に設けら
れた電極４と、基板１上に半導体チップ２を取り囲むよ
うに矩形状に配設された配線パターンのＧＮＤ（グラン
ド）配線５及び電源配線６、及び電源配線６の外側に配
設された複数本の信号配線７とは、各々ボンディングワ
イヤ８ａ〜８ｃにより電気的に接続されている。
【０００３】前記基板１上に配設された配線パターン
は、ＧＮＤ配線５、電源配線６、信号配線７等のワイヤ
ボンディングエリア以外の領域は、絶縁性のソルダーレ
ジスト９により覆われている。そして、基板１上の配線
パターンは、基板１に形成されたスルーホール１０を通
して基板１の下側にある半田ボールランド１１に接続さ
れ、半田ボールランド１１には半田ボール１２が形成さ
れている。一方、基板１の上面は、半導体チップ２及び
ボンディングワイヤ８ａ〜８ｃ全体をエポキシ樹脂等の
封止樹脂１３により覆われている。
【０００４】また、上述したオーバーモールドタイプ以
外の半導体装置としては、例えば、キャビティーダウン
タイプの半導体装置がある。この半導体装置は、メタル
スラグ等の金属基板上に、配線パターンが配設された配
線基板と半導体チップとを固定し、該半導体チップの電
極と、配線パターンのＧＮＤ配線、電源配線及び信号配
線とを、各々ボンディングワイヤにより電気的に接続
し、半導体チップ及びボンディングワイヤ全体をエポキ
シ樹脂等の封止樹脂で覆うとともに、配線基板上に半田
ボール等を形成したものである。
【０００５】
【発明が解決しようとする課題】従来の半導体装置の問
題点は、例えば、ボンディングワイヤ８ｃの場合、その
ループの一部がＧＮＤ配線５や電源配線６を跨いで信号
配線７にボンディングされているために、ボンディング
ワイヤ８ｃの配線パターン側のボンディング点付近のル
ープ垂れやトランスファモールドの際の注入樹脂による
変形等により、ＧＮＤ配線５や電源配線６あるいは他の
信号配線７に接触し易くなり、電気的なショートを起こ
す虞があるという点である。
【０００６】本発明は、上記の事情に鑑みてなされたも
のであって、ボンディングワイヤが他の配線を跨いでボ
ンディングされた場合であっても、ボンディングワイヤ
が他の配線に接触する虞が無く、ボンディングワイヤの
ループ垂れや変形に起因する電気的なショートを防止す
る半導体装置を提供することを目的とする。
【０００７】
【課題を解決するための手段】上記課題を解決するため
に、本発明は次の様な半導体装置を提供する。すなわ
ち、基板上に配設された配線パターンと、該基板上に固
定された半導体チップとを、ボンディングワイヤにより
電気的に接続し、前記基板上に、かつ前記配線パターン
のグランド配線、電源配線、信号配線それぞれの間に、
これらの配線より高さが高い絶縁体を設けたものであ
る。
【０００８】前記グランド配線及び電源配線を、前記信
号配線より半導体チップ側にある構成としてもよい。ま
た、前記グランド配線を、前記電源配線及び信号配線よ
り半導体チップ側にある構成としてもよい。また、前記
絶縁体を前記半導体チップの周辺に設けた構成としても
よい。さらに、前記基板をプリント配線基板とした構成
としてもよい。
【０００９】本発明の半導体装置では、前記基板上に、
かつ前記配線パターンのグランド配線、電源配線、信号
配線それぞれの間に、これらの配線より高さが高い絶縁
体を設けたことにより、半導体チップと配線パターンの
所望の配線とを電気的に接続したボンディングワイヤが
ループ垂れや変形を起こしても、このボンディングワイ
ヤが他の配線に接触する前に絶縁体に接触し、他の配線
に接触するのを防止する。これにより、ボンディングワ
イヤのループ垂れや変形に起因する電気的なショートを
防止することが可能になる。
【００１０】
【発明の実施の形態】本発明の半導体装置の各実施形態
について図面に基づき説明する。
【００１１】［第１の実施形態］図１は本発明の第１の
実施形態のオーバーモールドタイプの半導体装置の要部
を示す平面図、図２は同断面図であり、上面に配線パタ
ーンが配設されたガラスエポキシ基板（プリント配線基
板：以下、単に基板と略称する）２１の中央部には、半
導体チップ２が導電性ペースト３を介して固定され、こ
の半導体チップ２の上面に設けられた電極４と、ガラス
エポキシ基板２１上に半導体チップ２を取り囲むように
矩形状に配設された配線パターンのＧＮＤ配線５及び電
源配線６、及び電源配線６の外側に配設された複数本の
信号配線７とは、各々ボンディングワイヤ８ａ〜８ｃに
より電気的に接続されている。
【００１２】前記基板２１上に配設された配線パターン
は、ＧＮＤ配線５、電源配線６、信号配線７のワイヤボ
ンディングエリア以外の領域は、絶縁性のソルダーレジ
スト９により覆われている。そして、ＧＮＤ配線５と電
源配線６との間には前記ソルダーレジスト９と同種の矩
形状のソルダーレジスト（絶縁体）２２ａが、また、電
源配線６と信号配線７との間には前記ソルダーレジスト
９と同種の矩形状のソルダーレジスト（絶縁体）２２ｂ
が、それぞれ形成されている。
【００１３】これらのソルダーレジスト２２ａ、２２ｂ
は、近傍にある配線のボンディング点にボンディングツ
ールでボンディングした時、ボンディングツールとボン
ディングワイヤ８ａ〜８ｃが、ソルダーレジスト２２
ａ、２２ｂに干渉しない程度に位置している。また、こ
れらのソルダーレジスト２２ａ、２２ｂの上面の高さ
は、配線パターンを覆っているソルダーレジスト９の上
面と同一の高さになっている。
【００１４】通常、ソルダーレジスト２２ａ、２２ｂの
上面の高さは、ＧＮＤ配線５、電源配線６及び信号配線
７の配線パターンより３０〜５０μｍ程度高い。これら
のソルダーレジスト２２ａ、２２ｂは、露光現象を用い
た技術により簡単に形成することができる。
【００１５】そして、基板２１上の配線パターンは、基
板２１に形成されたスルーホール１０を通して基板２１
の下側にある半田ボールランド１１に接続され、半田ボ
ールランド１１には半田ボール１２が形成されている。
一方、基板２１の上面は、半導体チップ２及びボンディ
ングワイヤ８ａ〜８ｃ全体をエポキシ樹脂等の封止樹脂
１３により覆われている。
【００１６】本実施形態の半導体装置によれば、ＧＮＤ
配線５と電源配線６との間に矩形状のソルダーレジスト
（絶縁体）２２ａを、また、電源配線６と信号配線７と
の間に矩形状のソルダーレジスト（絶縁体）２２ｂを、
それぞれ形成したので、ボンディングワイヤ８ａ〜８ｃ
にループ垂れや変形等が発生した場合であっても、ボン
ディングワイヤ８ａ〜８ｃが他の配線に接触する前にソ
ルダレジスト２２ａ、２２ｂに接触するため、電気的な
ショート不良を防止することができ、半導体装置として
の信頼性を向上させることができる。これらのソルダレ
ジスト２２ａ、２２ｂは、特にループ垂れ及び変形が生
じ易い長ワイヤボンディング時に効果的である。
【００１７】なお、本実施形態の半導体装置では、ＧＮ
Ｄ配線５と電源配線６との間に矩形状のソルダーレジス
ト２２ａを、また、電源配線６と信号配線７との間に矩
形状のソルダーレジスト２２ｂを、それぞれ形成した構
成としたが、これらのソルダレジスト２２ａ、２２ｂ
は、ボンディングワイヤ８ａ〜８ｃが他の配線に接触す
る前に接触するような構成であればよく、上述した矩形
状に限定されることなく様々な形状、例えば、島状に配
列する等断続的に設ける構成とすることも可能である。
【００１８】［第２の実施形態］図３は本発明の第２の
実施形態のキャビティーダウンタイプの半導体装置の要
部を示す平面図、図４は同断面図であり、銅等からなる
メタル基板３１上には半導体チップ２が導電性ペースト
３を介して固定され、この半導体チップ２の周囲には、
配線パターンが形成された基板３２が導電性の接着剤３
３を介してメタル基板３１上に固定されている。
【００１９】この基板３２の最内周には、メタル基板３
１と電気的に接続されるＧＮＤ配線３４が形成され、Ｇ
ＮＤ配線３４を取り囲むように、信号配線３５と電源配
線３６がそれぞれ複数本配設されている。そして、ＧＮ
Ｄ配線３４と、信号配線３５及び電源配線３６との間に
は、これらの配線３４〜３６の高さより高い短冊状のソ
ルダーレジスト（絶縁体）３７が形成されている。
【００２０】本実施形態のパッケージとなる半導体チッ
プ２及び基板３２上の封止樹脂１３の高さは、図示しな
いマザーボードに実装する関係上、基板３２の外周部に
取り付けられた半田ボール１２よりも約０．２５ｍｍ以
上低くする必要がある。そこで、封止樹脂１３の流動を
阻止するダム樹脂３８の高さを半田ボール１２よりも約
０．２５ｍｍ以上低くしている。また、ボンディングワ
イヤ８ａ、８ｂのループ高さも低く抑え、かつ、ボンデ
ィングワイヤ８ａ、８ｂと配線パターンのＧＮＤ配線３
４との距離を確実に保つ必要がある。
【００２１】本実施形態の半導体装置によれば、ＧＮＤ
配線３４と、信号配線３５及び電源配線３６との間に、
これらの配線３４〜３６の高さより高い短冊状のソルダ
ーレジスト３７を形成したので、上記第１の実施形態の
半導体装置と同様の効果を奏することができる。しか
も、低ループボンディングが必要なパッケージに対して
非常に効果的である。
【００２２】
【発明の効果】以上説明した様に、本発明の半導体装置
によれば、基板上に、かつ配線パターンのグランド配
線、電源配線、信号配線それぞれの間に、これらの配線
より高さが高い絶縁体を設けたので、半導体チップと配
線パターンの所望の配線とを電気的に接続したボンディ
ングワイヤがループ垂れや変形を起こしても、このボン
ディングワイヤが他の配線に接触する前に絶縁体に接触
し、他の配線に接触するのを防止することができる。し
たがって、ボンディングワイヤのループ垂れや変形に起
因する電気的なショートを防止することができ、半導体
装置の信頼性を向上させることができる。
【図面の簡単な説明】
【図１】 本発明の第１の実施形態のオーバーモールド
タイプの半導体装置の要部を示す平面図である。
【図２】 本発明の第１の実施形態のオーバーモールド
タイプの半導体装置の要部を示す断面図である。
【図３】 本発明の第２の実施形態のキャビティーダウ
ンタイプの半導体装置の要部を示す平面図である。
【図４】 本発明の第２の実施形態のキャビティーダウ
ンタイプの半導体装置の要部を示す断面図である。
【図５】 従来のオーバーモールドタイプの半導体装置
の要部を示す平面図である。
【図６】 従来のオーバーモールドタイプの半導体装置
を示す断面図である。
【符号の説明】
１ 基板 ２ 半導体チップ ３ 導電性ペースト ４ 電極 ５ ＧＮＤ（グランド）配線 ６ 電源配線 ７ 信号配線 ８ａ〜８ｃ ボンディングワイヤ ９ ソルダーレジスト １０ スルーホール １１ 半田ボールランド １２ 半田ボール １３ 封止樹脂 ２１ ガラスエポキシ基板（プリント配線基板） ２２ａ、２２ｂ ソルダーレジスト（絶縁体） ３１ メタル基板 ３２ 基板 ３３ 導電性の接着剤 ３４ ＧＮＤ配線 ３５ 信号配線 ３６ 電源配線 ３７ ソルダーレジスト（絶縁体） ３８ ダム樹脂

Claims (5)

    (57)【特許請求の範囲】
  1. 【請求項１】 基板上に配設された配線パターンと、該
    基板上に固定された半導体チップとを、ボンディングワ
    イヤにより電気的に接続してなる半導体装置において、前記基板上に、かつ 前記配線パターンのグランド配線、
    電源配線、信号配線それぞれの間に、これらの配線より
    高さが高い絶縁体を設けたことを特徴とする半導体装
    置。
  2. 【請求項２】 前記グランド配線及び電源配線は、前記
    信号配線より半導体チップ側にあることを特徴とする請
    求項１記載の半導体装置。
  3. 【請求項３】 前記グランド配線は、前記電源配線及び
    信号配線より半導体チップ側にあることを特徴とする請
    求項１記載の半導体装置。
  4. 【請求項４】 前記絶縁体は、前記半導体チップの周辺
    に設けられていることを特徴とする請求項１、２または
    ３記載の半導体装置。
  5. 【請求項５】 前記基板は、プリント配線基板であるこ
    とを特徴とする請求項１、２、３または４記載の半導体
    装置。
JP9283939A 1997-10-16 1997-10-16 半導体装置 Expired - Fee Related JP2993480B2 (ja)

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Application Number Priority Date Filing Date Title
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JP2993480B2 true JP2993480B2 (ja) 1999-12-20

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