KR940003010A - 다층 배선 기판, 이 기판을 이용한 반도체 장치 및 다층 배선 기판의 제조방법 - Google Patents

다층 배선 기판, 이 기판을 이용한 반도체 장치 및 다층 배선 기판의 제조방법 Download PDF

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KR940003010A
KR940003010A KR1019930014513A KR930014513A KR940003010A KR 940003010 A KR940003010 A KR 940003010A KR 1019930014513 A KR1019930014513 A KR 1019930014513A KR 930014513 A KR930014513 A KR 930014513A KR 940003010 A KR940003010 A KR 940003010A
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base substrate
power supply
thin film
conductor patterns
via hole
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KR970005707B1 (ko
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도시오 스도
겐지 이또
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사또 후미오
가부시끼가이샤 도시바
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Abstract

본 발명은 멀티 칩 모듈에 사용되는 다층 배선 기판의 형성 공정을 간략화하는 것을 목적으로 한다.
전원용과 접지용 면상 도체 패턴(12 및 13)에 절연 시트를 통해 교대로 적층되어 세라믹 베이스 기판(11)이 구성되고, 세라믹 베이스 기판(11)의 중앙부에는 내부의 전원용과 접지용 면상 도체 패턴과 전기적으로 접속된 비아 홀 접촉부(15 및 16)이 규칙적으로 교대로 배치되며, 세라믹 베이스 기판(11)의 주면상에는 상기 각 비아홀 접촉부(15 및 16)과 선택적으로 접속된 전원 및 접지용 박막 배선과 신호용 박막 배선이 형성된 다층 박막배선부(22)가 설치된다.

Description

다층 배선 기판, 그 기판을 이용한 반도체 방치 및 다층 배선 기판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 다층 배선 기판의 구성을 도시한 패턴 평면도.
제2도는 제1도의 다층 배선 기판을 이용해서 구성된 반도체 장치의 구성을 도시한 단면도.
제3도는 제1도의 다층 배선 기판에서 사용되는 절연층에 형성된 면도체 패턴의 패턴 평면도.
제4도는 제2실시예에 관한 다층 배선 기판이 구성을 도시한 단면도.

Claims (9)

  1. 전원계의 각각 전위를 각각 전달하는 면상 도체 패턴(12 및 13)이 절연층을 개재하여 교대로 적층된 베이스 기판(11), 상기 베이스 기판의 전원계의 각 전위용 면상 도체 패턴의 각각과 전기적으로 접속되고, 상기 베이스 기판의 중앙부에 규칙적으로 교대로 배치되어 베이스 기판을 관통하도록 형성된 각각 복수의 전원계의 각 전위용 비아 홀 접촉부(15 및 16), 및 상기 베이스 기판이 주면상에 설치되어 상기 각 비아 홀 접촉부에 대해 선택적으로 접속된 전원계의 각 전위용 박막 배선과 신호용 박막 배선이 형성된 다음 박막 배선부(22)를 구비한 것을 특징으로 하는 다층 배선 개판.
  2. 전원용 및 접지용 면상 도체 패턴(12 및 13)이 절연층을 개재하여 교대로 적층된 베이스 기판(11), 상기 베이스 기판의 전원용 및 접지용 면상 도체 패턴 각각과 전기적으로 접속되고, 상기 베이스 기판의 중앙부에 규칙적으로 교대로 배치되어 이 베이스 기판을 관통하도록 형성된 각각 복수의 전원용 및 접지용 비아 홀 접촉부(15 및 16), 및 상기 베이스 기판의 주면상에 설치되고 상기 전원용 및 접지용 비아 홀 접촉부에 대해 선택적으로 접속된 전원 및 박막 배선과 신호용 박막과 패턴이 형성된 다층 박막 배선부(22)를 구비한 것을 특징으로 하는 다층 배선 기판.
  3. 제2항에 있어서, 상기 베이스 기판이 절연층이 알루미늄·나이트라이드로 구성되는 것을 특징으로 하는 다층 배선 기판.
  4. 제2항에 있어서, 상기 베이스 기판의 주면에는 다른 절연층보다도 두께가 충분히 얇은 절연층이 설치되어 있는 것을 특징으로 하는 다층 배선 기판.
  5. 전원용 및 접지용 면상 도체 패턴(12 및 13)이 절연층을 개재하여 교대로 적층된 베이스 기판(11), 상기 베이스 기판의 전원용 및 접지용 면상 도체 패턴 각각과 전기적으로 접속되고, 상기 베이스 기판의 중앙부에 규칙적으로 교대로 배치되어 이 베이스 기판을 관통하도록 형성된 각각 복수의 전원용 비아 홀 접촉부(15 및 16), 및 상기 베이스 기판의 주면상에 설치되고 상기 전원용 및 접지용 바이 홀 접촉부에 대해 선택적으로 접속된 전원 및 접지용 박막 배선과 신호용 박막 배선이 형성된 다층 박막 배선부(22), 및 상기 다층 박막 배선부 상에 탑재되고, 복수의 표면 전극을 가지고, 이들 표면 전극이 상기 다층 박막 배선부의 박막 배선층과 선택적으로 접속된 적어도 1개의 반도체 칩(23)을 구비한 것을 특징으로 하는 반도체 장치.
  6. 제5항에 있어서, 상기 베이스 기판의 주면에는 다른 절연층보다 두께가 충분히 얇은 절연층이 설치되어 있는 것을 특징으로 하는 반도체 장치.
  7. 전원용 및 접지용 면상 도체 패턴(12 및 13)이 절연층을 개재하여 교대로 적층된 베이스 기판(11), 상기 베이스 기판의 전원용 및 접지용 면상 도체 패턴 각각과 전기적으로 접속되고, 상기 베이스 기판의 중앙부에 규칙적으로 교대로 배치되어 이 베이스 기판을 관통하도록 형성된 각각 복수의 전원용 및 접지용 비아 홀 접촉부(15 및 16), 상기 베이스 기판에 상기 전원용 및 접지용 비아 홀 접촉부와 함께 배치되고, 상기 베이스 기판을 관통하도록 형성된 복수의 신호용 비아 홀 접촉부(17), 및 상기 베이스 기판의 주면상에 형성되고, 상기 각 비아 홀 접촉부와 접속된 복수의 패드 전극(25 및 54)를 구비하는 것을 특징으로 하는 다층 배선 기판.
  8. 제7항에 있어서, 상기 베이스 기판의 절연층이 알루미늄·나이트라이드로 구성되는 것을 특징으로 하는 다종 배선 기판.
  9. 전원용 접지용 면상 도체 패턴이 절연층을 개재하여 교대로 적층되고, 이들 전원용 및 접지용 면상 도체 패턴의 각각과 전기적으로 접속된 각각 복수의 전원용 및 접지용 바이 홀 접촉부 및 복수의 신호용 바이 홀 접촉부를 갖는 베이스 기판을 형성하고, 상기 베이스 기판을 필요한 치수로 절단해서 개개의 다층 배선 기판으로 분리하는 것을 특징으로 하는 다층 배선 기판의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930014513A 1992-07-30 1993-07-29 다층 배선 기판, 이 기판을 이용한 반도체 장치 및 다층 배선 기판의 제조방법 KR970005707B1 (ko)

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Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3210503B2 (ja) * 1993-09-30 2001-09-17 株式会社東芝 マルチチップモジュールおよびその製造方法
JPH07109573A (ja) * 1993-10-12 1995-04-25 Semiconductor Energy Lab Co Ltd ガラス基板および加熱処理方法
US5583376A (en) * 1995-01-03 1996-12-10 Motorola, Inc. High performance semiconductor device with resin substrate and method for making the same
JPH09107048A (ja) * 1995-03-30 1997-04-22 Mitsubishi Electric Corp 半導体パッケージ
US5914533A (en) * 1995-06-06 1999-06-22 International Business Machines Corporation Multilayer module with thinfilm redistribution area
FR2735648B1 (fr) * 1995-06-13 1997-07-11 Bull Sa Procede de refroidissement d'un circuit integre monte dans un boitier
US5675183A (en) * 1995-07-12 1997-10-07 Dell Usa Lp Hybrid multichip module and methods of fabricating same
US5756395A (en) * 1995-08-18 1998-05-26 Lsi Logic Corporation Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
US5751165A (en) * 1995-08-18 1998-05-12 Chip Express (Israel) Ltd. High speed customizable logic array device
US5623160A (en) * 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
US5789783A (en) * 1996-04-02 1998-08-04 Lsi Logic Corporation Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection
US6323549B1 (en) * 1996-08-29 2001-11-27 L. Pierre deRochemont Ceramic composite wiring structures for semiconductor devices and method of manufacture
US5886597A (en) * 1997-03-28 1999-03-23 Virginia Tech Intellectual Properties, Inc. Circuit structure including RF/wideband resonant vias
US6303879B1 (en) * 1997-04-01 2001-10-16 Applied Materials, Inc. Laminated ceramic with multilayer electrodes and method of fabrication
US5888445A (en) * 1997-06-02 1999-03-30 Eastman Kodak Company Method for making ceramic micro-electromechanical parts and tools
US6317333B1 (en) 1997-08-28 2001-11-13 Mitsubishi Denki Kabushiki Kaisha Package construction of semiconductor device
JP4190602B2 (ja) * 1997-08-28 2008-12-03 株式会社ルネサステクノロジ 半導体装置
JP3985016B2 (ja) * 1997-10-31 2007-10-03 沖電気工業株式会社 半導体装置
US5969421A (en) * 1997-11-18 1999-10-19 Lucent Technologies Inc. Integrated circuit conductors that avoid current crowding
US6828666B1 (en) * 1998-03-21 2004-12-07 Advanced Micro Devices, Inc. Low inductance power distribution system for an integrated circuit chip
US6218729B1 (en) * 1999-03-11 2001-04-17 Atmel Corporation Apparatus and method for an integrated circuit having high Q reactive components
TW409330B (en) * 1999-03-20 2000-10-21 United Microelectronics Corp Repairable multi-chip module package
US6198635B1 (en) * 1999-05-18 2001-03-06 Vsli Technology, Inc. Interconnect layout pattern for integrated circuit packages and the like
JP2000331835A (ja) * 1999-05-21 2000-11-30 Taiyo Yuden Co Ltd 積層電子部品及び回路モジュール
JP4441974B2 (ja) * 2000-03-24 2010-03-31 ソニー株式会社 半導体装置の製造方法
US7215022B2 (en) * 2001-06-21 2007-05-08 Ati Technologies Inc. Multi-die module
DE10217565A1 (de) * 2002-04-19 2003-11-13 Infineon Technologies Ag Halbleiterbauelement mit integrierter gitterförmiger Kapazitätsstruktur
JP3632684B2 (ja) * 2002-08-26 2005-03-23 株式会社日立製作所 半導体素子及び半導体パッケージ
DE10260786A1 (de) * 2002-12-23 2004-07-15 Daimlerchrysler Ag Flachkabelstrang
US7047628B2 (en) * 2003-01-31 2006-05-23 Brocade Communications Systems, Inc. Impedance matching of differential pair signal traces on printed wiring boards
WO2004091268A1 (ja) * 2003-04-07 2004-10-21 Ibiden Co., Ltd. 多層プリント配線板
US7061096B2 (en) * 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US7732904B2 (en) * 2003-10-10 2010-06-08 Interconnect Portfolio Llc Multi-surface contact IC packaging structures and assemblies
US7280372B2 (en) * 2003-11-13 2007-10-09 Silicon Pipe Stair step printed circuit board structures for high speed signal transmissions
US7652381B2 (en) 2003-11-13 2010-01-26 Interconnect Portfolio Llc Interconnect system without through-holes
US7278855B2 (en) 2004-02-09 2007-10-09 Silicon Pipe, Inc High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture
JP4844080B2 (ja) * 2005-10-18 2011-12-21 日本電気株式会社 印刷配線板及びその電源雑音抑制方法
JP2007207826A (ja) * 2006-01-31 2007-08-16 Orion Denki Kk プリント基板
US7629683B1 (en) * 2006-02-28 2009-12-08 Juniper Networks, Inc. Thermal management of electronic devices
US7510323B2 (en) * 2006-03-14 2009-03-31 International Business Machines Corporation Multi-layered thermal sensor for integrated circuits and other layered structures
US20070252283A1 (en) * 2006-04-28 2007-11-01 Keller Christopher L High speed, high density board to board interconnect
US7911059B2 (en) * 2007-06-08 2011-03-22 SeniLEDS Optoelectronics Co., Ltd High thermal conductivity substrate for a semiconductor device
US7906838B2 (en) * 2007-07-23 2011-03-15 Headway Technologies, Inc. Electronic component package and method of manufacturing same
JP4492695B2 (ja) * 2007-12-24 2010-06-30 株式会社デンソー 半導体モジュールの実装構造
US20110075392A1 (en) 2009-09-29 2011-03-31 Astec International Limited Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets
WO2011074221A1 (ja) * 2009-12-14 2011-06-23 パナソニック株式会社 半導体装置
JP2015207677A (ja) * 2014-04-22 2015-11-19 京セラサーキットソリューションズ株式会社 配線基板
US10586012B2 (en) 2018-04-25 2020-03-10 International Business Machines Corporation Semiconductor process modeling to enable skip via in place and route flow

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AR228608A1 (es) * 1980-07-11 1983-03-30 Du Pont Procedimiento para formar una conexion esteril entre tubos,aparato,disposicion y recipiente para llevarlo a cabo
JPS58111396A (ja) * 1981-12-25 1983-07-02 株式会社日立製作所 多層配線基板
JPS6014494A (ja) * 1983-07-04 1985-01-25 株式会社日立製作所 セラミツク多層配線基板およびその製造方法
JPS6156493A (ja) * 1984-08-28 1986-03-22 日本電気株式会社 多層回路基板の電源配線構造
US4721831A (en) * 1987-01-28 1988-01-26 Unisys Corporation Module for packaging and electrically interconnecting integrated circuit chips on a porous substrate, and method of fabricating same
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
JPH01191461A (ja) * 1988-01-27 1989-08-01 Nec Corp Ｉｃパッケージ
JPH02168662A (ja) * 1988-09-07 1990-06-28 Hitachi Ltd チップキャリア
JPH0353795A (ja) * 1989-07-21 1991-03-07 Nec Corp 誤動作検出方式
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
JP2574902B2 (ja) * 1989-09-20 1997-01-22 株式会社日立製作所 半導体装置

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