KR970067822A - 반도체장치의 제조방법 및 반도체장치의 패키지 - Google Patents

반도체장치의 제조방법 및 반도체장치의 패키지 Download PDF

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Publication number
KR970067822A
KR970067822A KR1019960071161A KR19960071161A KR970067822A KR 970067822 A KR970067822 A KR 970067822A KR 1019960071161 A KR1019960071161 A KR 1019960071161A KR 19960071161 A KR19960071161 A KR 19960071161A KR 970067822 A KR970067822 A KR 970067822A
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South Korea
Prior art keywords
hole
metal foil
forming
insulating substrate
main surface
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KR1019960071161A
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English (en)
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KR100213857B1 (ko
Inventor
마사키 와타나베
아키요시 사와이
요시카즈 나루타키
도모아키 하시모토
마사토시 야스나가
쥰 시바타
히로시 세키
가즈히코 구라후치
가츠노리 아사이
Original Assignee
기타오카 다카시
미쓰비시덴키 주식회사
요시토미 마사오
료덴세미컨덕터시스템 엔지니어링 주식회사
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Publication of KR970067822A publication Critical patent/KR970067822A/ko
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Publication of KR100213857B1 publication Critical patent/KR100213857B1/ko

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    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

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Abstract

프린트기판형 BGA 패키지를 구비하는 반도체장치의 제조방법 및 반도체 장치의 패키지에 관한 것으로서, 프린트기판형 BGA의 프린트기판에 형성되는 배선의 간격을 좁게 하기 위해, 배선층(20a),(22a)는 도금이 실시되고 있지 않는 분만큼 종래보다 얇게 형성되고 있고, 배선층(19a)(23a)는 도금이 1층뿐이므로 종래보다 얇게 형성되어 있으며, 얇게 형성되어 있는 배선층 (19a)(20a)(22a)(23a)는 배선간격을 좁게 형성하기 쉽게 되어 있다. 이러한 것에 의해 얇은 도전체층을 패터닝할 수 있어 패터닝된 배선간의 피치를 좁게 할 수 있다는 등의 효과가 있다.

Description

반도체장치의 제조방법 및 반도체장치의 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제14도는 실시형태1의 반도체장치의 1제조공정을 도시한 단면도.

Claims (3)

  1. 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하는 반도체장치의 제조방법.
  2. 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하고, 상기 제1프린트기판(15a)를 준비하는 공정은 상기 절연기판(18)의 상기 제1주면에 상기 제1금속박(30)을 형성하는 공정, 상기 절연기판과 상기 제1금속박을 관통하는 상기 제1구멍(60)을 형성하는 공정 및 상기 절연기판의 상기 제2주면에 상기 제2금속박(31a)를 적층하는 공정을 구비하는 반도체장치의 제조방법.
  3. 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하고, 상기 제1구멍을 슬릿형사의 구멍(147,`150)을 포함하고, 상기 개구부(45a)를 형성하는 공정은 상기 슬릿형상의 구멍(150)의 외벽을 남기고 그 내벽을 깍아서 그 슬릿형상의 구멍의 바닥부단면을 노출시키는 공정, 상기 슬릿형상의 구멍의 상기 외벽의 상부를 스폿페이싱가공에 의해서 깍아내는 공정 및 상기 슬릿형상의 구멍의 상기 바닥부상에 패드(69)를 형성하는 공정을 구비하는 반도체장치의 제조방법.
KR1019960071161A 1996-03-28 1996-12-24 반도체장치의 제조방법 및 반도체장치의 패키지 KR100213857B1 (ko)

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US6005289A (en) 1999-12-21
CN1160984A (zh) 1997-10-01
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TW332962B (en) 1998-06-01
JPH09266268A (ja) 1997-10-07

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