JP4844080B2 - 印刷配線板及びその電源雑音抑制方法 - Google Patents
印刷配線板及びその電源雑音抑制方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000001629 suppression Effects 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 29
- 239000003990 capacitor Substances 0.000 description 28
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09336—Signal conductors in same plane as power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
前記第1の信号層には、電源電位とグランド電位のうちの一方の電位の第1の配線領域をその空き領域に設ける工程と、
前記第2の信号層には、電源電位とグランド電位のうちの他方の電位の第2の配線領域をその空き領域に設ける工程と、を含むようにしてもよい。
パルス幅をT(=半周期)、
雑音源であるICの電源端子(またはGND端子)と電源配線領域111のパターン(またはGND配線領域112のパターン)までの距離をL、
雑音の単位長当たりの伝播遅延時間をτ、
とすると、雑音のピークであるT/2地点(1/4周期)を反射電圧と重畳させる必要があることから、次式(3)なる関係を満たすことが必要である。
T=√(ε)・λ/(2c) …(4)
τ=√(ε)/c …(5)
から、
L<λ/8 …(6)
なる関係が導かれる。
101 電源層
102 信号層
103 GND層
104 電源用スルーホール
105 GND用スルーホール
106 スルーホール(信号用スルーホール)
107 パッド
108 引き出し線
110 空き領域(信号層における電源、GND配線領域)
111 電源配線領域
112 GND配線領域
200 印刷配線板(基板)
201 電源層
202 GND層
203 電源配線領域
204 GND配線領域
205 電源用スルーホール
206 GND用スルーホール
207 パッド
208 信号
210 空き領域(信号層における電源、GND配線領域)
Claims (8)
- 信号層に設けられた所定の空き領域に、電源電位及び/又はグランド電位の配線領域を備えた印刷配線板であって、
各層間に絶縁層を配して順に積層されてなる、第1の電源層、第1の信号層、第1のグランド層、第2の電源層、第2の信号層、及び、第2のグランド層を含み、
前記第1の信号層は、電源電位とグランド電位のうちの一方の電位の第1の配線領域を、前記第1の信号層に設けられた空き領域に含み、
前記第2の信号層は、電源電位とグランド電位のうちの他方の電位の第2の配線領域を、前記第2の信号層に設けられた空き領域に含む、ことを特徴とする印刷配線板。 - 前記印刷配線板に実装される半導体装置の底面の中心部から四方に拡延された領域に対応する前記信号層の領域を前記空き領域とし、電源電位及び/又はグランド電位の配線領域を備えている、ことを特徴とする請求項1記載の印刷配線板。
- 信号層に設けられた所定の空き領域に、電源電位及び/又はグランド電位の配線領域を備えた印刷配線板であって、
前記信号層は、電源層とグランド層との間にそれぞれ絶縁層を介して配設され、
前記印刷配線板には、その部品面に対向する底面に複数の電極を備えた半導体装置が実装され、
前記印刷配線板において、前記半導体装置の前記複数の電極とそれぞれ当接する複数のパッドを前記部品面に有し、前記パッドに接続するスルーホールは、前記パッドに対して、前記半導体装置の外周側に位置するように配置され、
前記半導体装置の底面の縦横の中心線に対応して十字状に拡延された領域に対応する前記信号層の領域が前記空き領域とされる、ことを特徴とする印刷配線板。 - 前記空き領域は、前記半導体装置の底面の中心部に対応する領域から外周側に幅が段階的に狭まる形状である、ことを特徴とする請求項3記載の印刷配線板。
- 前記第1の配線領域は、前記第1の配線領域の近傍に配設された、電源電位とグランド電位のうちの一方の電位のスルーホールに接続され、
前記第2の配線領域は、前記第2の配線領域の近傍に配設された、電源電位とグランド電位のうちの他方の電位のスルーホールに接続される、ことを特徴とする請求項1記載の印刷配線板。 - 信号層に空き領域を設け、前記信号層の空き領域に、電源電位及び/又はグランド電位となる配線領域を設ける工程を含む印刷配線板の電源雑音抑制方法であって、
第1の電源層、第1の信号層、第1のグランド層、第2の電源層、第2の信号層、及び、第2のグランド層を各層間に絶縁層を配してこの順に積層する工程を含み、
前記第1の信号層には、電源電位とグランド電位のうちの一方の電位の第1の配線領域を、前記第1の信号層の空き領域に設ける工程と、
前記第2の信号層には、電源電位とグランド電位のうちの他方の電位の第2の配線領域を、前記第2の信号層の空き領域に設ける工程と、
を含む、印刷配線板の電源雑音抑制方法。 - 信号層に空き領域を設け、前記信号層の空き領域に、電源電位及び/又はグランド電位となる配線領域を設ける工程を含む印刷配線板の電源雑音抑制方法であって、
前記印刷配線板には、その部品面に対向する底面に複数の電極を備えた半導体装置が実装され、
前記印刷配線板において、前記半導体装置の前記複数の電極とそれぞれ当接する複数のパッドを前記部品面に有し、前記パッドに接続するスルーホールは、前記パッドに対して、前記半導体装置の外周側に位置するように配置され、
前記半導体装置の底面の縦横の中心線に対応して、十字状に拡延された領域に対応する信号層の領域が、前記空き領域とされる、ことを特徴とする印刷配線板の電源雑音抑制方法。 - 前記第1の配線領域を、前記第1の配線領域の近傍に配設された、電源電位とグランド電位のうちの一方の電位のスルーホールに接続する工程と、
前記第2の配線領域を、前記第2の配線領域の近傍に配設された、電源電位とグランド電位のうちの他方の電位のスルーホールに接続する工程と、
を含む、ことを特徴とする請求項6記載の印刷配線板の電源雑音抑制方法。
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JP2005303386A JP4844080B2 (ja) | 2005-10-18 | 2005-10-18 | 印刷配線板及びその電源雑音抑制方法 |
US11/549,449 US8033015B2 (en) | 2005-10-18 | 2006-10-13 | Printed wiring board and method of suppressing power supply noise thereof |
US13/026,965 US8451619B2 (en) | 2005-10-18 | 2011-02-14 | Printed wiring board and method of suppressing power supply noise thereof |
US13/198,589 US20110286192A1 (en) | 2005-10-18 | 2011-08-04 | Printed wiring board and method of suppressing power supply noise thereof |
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JP2005303386A JP4844080B2 (ja) | 2005-10-18 | 2005-10-18 | 印刷配線板及びその電源雑音抑制方法 |
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JP5035039B2 (ja) * | 2008-03-11 | 2012-09-26 | 日本電気株式会社 | 電子回路基板の電源雑音解析方法とシステム並びにプログラム |
JP5151571B2 (ja) * | 2008-03-11 | 2013-02-27 | 日本電気株式会社 | 電子回路基板の電源雑音解析装置とプログラム |
US8273994B2 (en) * | 2009-12-28 | 2012-09-25 | Juniper Networks, Inc. | BGA footprint pattern for increasing number of routing channels per PCB layer |
JP5673673B2 (ja) * | 2010-04-06 | 2015-02-18 | 日本電気株式会社 | 機能素子内蔵基板 |
DE102013102714A1 (de) * | 2013-03-18 | 2014-09-18 | Schott Ag | Hochfrequenzdurchführung |
JP2015005716A (ja) * | 2013-05-24 | 2015-01-08 | アイカ工業株式会社 | 多層プリント基板 |
JP2015153808A (ja) * | 2014-02-12 | 2015-08-24 | ソニー株式会社 | 半導体チップ、および、半導体モジュール |
JP2016025419A (ja) * | 2014-07-17 | 2016-02-08 | 新日本無線株式会社 | 多層構造の高周波回路 |
US20180184516A1 (en) * | 2015-07-08 | 2018-06-28 | Nec Corporation | Printed wiring board |
JP2017191902A (ja) * | 2016-04-15 | 2017-10-19 | ルネサスエレクトロニクス株式会社 | 電子装置 |
US10477672B2 (en) * | 2018-01-29 | 2019-11-12 | Hewlett Packard Enterprise Development Lp | Single ended vias with shared voids |
CN109743835A (zh) * | 2018-09-21 | 2019-05-10 | 昆山联滔电子有限公司 | 一种柔性扁平电缆 |
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-
2005
- 2005-10-18 JP JP2005303386A patent/JP4844080B2/ja active Active
-
2006
- 2006-10-13 US US11/549,449 patent/US8033015B2/en not_active Expired - Fee Related
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2011
- 2011-02-14 US US13/026,965 patent/US8451619B2/en not_active Expired - Fee Related
- 2011-08-04 US US13/198,589 patent/US20110286192A1/en not_active Abandoned
Also Published As
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US20070085193A1 (en) | 2007-04-19 |
US20110286192A1 (en) | 2011-11-24 |
US8451619B2 (en) | 2013-05-28 |
JP2007115772A (ja) | 2007-05-10 |
US8033015B2 (en) | 2011-10-11 |
US20110132640A1 (en) | 2011-06-09 |
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