JP2015207677A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2015207677A JP2015207677A JP2014087874A JP2014087874A JP2015207677A JP 2015207677 A JP2015207677 A JP 2015207677A JP 2014087874 A JP2014087874 A JP 2014087874A JP 2014087874 A JP2014087874 A JP 2014087874A JP 2015207677 A JP2015207677 A JP 2015207677A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- holes
- power supply
- semiconductor element
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 42
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000004020 conductor Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】コア基板1を貫通するようにして互いに隣接して配設された接地用のスルーホール5Gおよび電源用のスルーホール5Pを具備して成る配線基板10であって、接地用のスルーホール5Gと電源用のスルーホール5Pとは、水平断面形状が角部と該角部との間を結ぶ辺部とを有する略方形状であり、互いに隣接するもの同士の辺部同士が互いに対向するように配置されている。互いに隣接する接地用のスルーホール5Gと電源用のスルーホール5Pとの対向面積がを大きくなり、それにより両者間のループインダクタンスを小さいものとして半導体素子Sに対して十分な電源供給を行なうことができる。
【選択図】図2
Description
図1は、本発明における配線基板の実施形態の一例を示す概略断面図であり、図2は図1の切断線I−Iにおけるスルーホールの配置を示す平面模式図である。
5G 接地用のスルーホール導体
5P 電源用のスルーホール導体
10 配線基板
Claims (2)
- コア基板を貫通するようにして互いに隣接して配設された接地用のスルーホールおよび電源用のスルーホールを具備して成る配線基板であって、前記接地用のスルーホールと電源用のスルーホールとは、水平断面形状が角部と該角部との間を結ぶ辺部とを有する略方形状であり、互いに隣接するもの同士の前記辺部同士が互いに対向するように配置されていることを特徴とする配線基板。
- 互いに隣接して配置された前記接地用のスルーホールと前記電源用のスルーホールとが市松模様をなすように交互に配置されていることを特徴とする請求項1記載の配線基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014087874A JP2015207677A (ja) | 2014-04-22 | 2014-04-22 | 配線基板 |
US14/690,625 US20150305155A1 (en) | 2014-04-22 | 2015-04-20 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014087874A JP2015207677A (ja) | 2014-04-22 | 2014-04-22 | 配線基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2015207677A true JP2015207677A (ja) | 2015-11-19 |
Family
ID=54323227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014087874A Pending JP2015207677A (ja) | 2014-04-22 | 2014-04-22 | 配線基板 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20150305155A1 (ja) |
JP (1) | JP2015207677A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017174931A (ja) * | 2016-03-23 | 2017-09-28 | 京セラ株式会社 | 配線基板 |
JP2019149508A (ja) * | 2018-02-28 | 2019-09-05 | 京セラ株式会社 | 配線基板及び電子装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106211556B (zh) * | 2016-07-28 | 2019-03-19 | Oppo广东移动通信有限公司 | 印刷电路板及具有其的电子装置 |
CN107148144B (zh) * | 2017-06-22 | 2020-04-07 | 青岛海信移动通信技术股份有限公司 | 一种4g模块 |
JP6869209B2 (ja) * | 2018-07-20 | 2021-05-12 | 日本特殊陶業株式会社 | 配線基板 |
KR102262073B1 (ko) * | 2018-07-26 | 2021-06-08 | 교세라 가부시키가이샤 | 배선 기판 |
CN115547846A (zh) * | 2019-02-21 | 2022-12-30 | 奥特斯科技(重庆)有限公司 | 部件承载件及其制造方法和电气装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013062296A (ja) * | 2011-09-12 | 2013-04-04 | Shinko Electric Ind Co Ltd | 配線基板、及び半導体パッケージ |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2960276B2 (ja) * | 1992-07-30 | 1999-10-06 | 株式会社東芝 | 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法 |
JP3269397B2 (ja) * | 1995-09-19 | 2002-03-25 | 株式会社デンソー | プリント配線基板 |
US6828666B1 (en) * | 1998-03-21 | 2004-12-07 | Advanced Micro Devices, Inc. | Low inductance power distribution system for an integrated circuit chip |
US6713685B1 (en) * | 1998-09-10 | 2004-03-30 | Viasystems Group, Inc. | Non-circular micro-via |
CN100367491C (zh) * | 2004-05-28 | 2008-02-06 | 日本特殊陶业株式会社 | 中间基板 |
US7266788B2 (en) * | 2005-07-19 | 2007-09-04 | International Business Machines Corporation | Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules |
US7557444B2 (en) * | 2006-09-20 | 2009-07-07 | Infineon Technologies Ag | Power-via structure for integration in advanced logic/smart-power technologies |
US8093708B2 (en) * | 2009-07-06 | 2012-01-10 | Sony Ericsson Mobile Communications Ab | Semiconductor package having non-uniform contact arrangement |
KR102017829B1 (ko) * | 2013-04-09 | 2019-09-03 | 삼성전자 주식회사 | 관통부를 갖는 인쇄 회로 기판 및 이를 이용하여 형성된 반도체 패키지 |
-
2014
- 2014-04-22 JP JP2014087874A patent/JP2015207677A/ja active Pending
-
2015
- 2015-04-20 US US14/690,625 patent/US20150305155A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013062296A (ja) * | 2011-09-12 | 2013-04-04 | Shinko Electric Ind Co Ltd | 配線基板、及び半導体パッケージ |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017174931A (ja) * | 2016-03-23 | 2017-09-28 | 京セラ株式会社 | 配線基板 |
JP2019149508A (ja) * | 2018-02-28 | 2019-09-05 | 京セラ株式会社 | 配線基板及び電子装置 |
Also Published As
Publication number | Publication date |
---|---|
US20150305155A1 (en) | 2015-10-22 |
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