JP5959395B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP5959395B2 JP5959395B2 JP2012218914A JP2012218914A JP5959395B2 JP 5959395 B2 JP5959395 B2 JP 5959395B2 JP 2012218914 A JP2012218914 A JP 2012218914A JP 2012218914 A JP2012218914 A JP 2012218914A JP 5959395 B2 JP5959395 B2 JP 5959395B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- resin layer
- insulating resin
- conductor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Description
10 半導体素子接続パッド
10a 独立パッド
10b 統合パッド
11 導体柱
11b 統合パッド上に形成された導体柱
G 間隙
S 半導体集積回路素子
T 半導体集積回路素子の電極
Claims (2)
- 第1の絶縁樹脂層と、該第1の絶縁樹脂層上に形成されており、半導体集積回路素子の1個ずつの電極に対して電気的に独立して接続される独立パッドおよび半導体集積回路素子の複数個の電極に対して電気的に共通して接続される統合パッドを含む複数の半導体素子接続パッドと、前記第1の絶縁樹脂層および前記半導体素子接続パッド上に形成されており、前記半導体素子接続パッドの上面中央部を露出させる開口部を有する第2の絶縁樹脂層と、前記開口部内の前記半導体素子接続パッド上に形成されており、前記第2の絶縁樹脂層の上面から突出する銅めっき層から成る導体柱とを具備して成る配線基板であって、前記統合パッド上に形成された前記導体柱は、複数個の前記電極に対応する部分が1つに繋がった状態で前記第2の絶縁樹脂層の上面から前記開口部の大きさよりも大きな大きさで突出していることを特徴とする配線基板。
- 前記統合パッド上に形成された前記導体柱は、前記第2の絶縁樹脂層の上面から突出する部分が間隙を介して複数に分かれていることを特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012218914A JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012218914A JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014072467A JP2014072467A (ja) | 2014-04-21 |
JP5959395B2 true JP5959395B2 (ja) | 2016-08-02 |
Family
ID=50747379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012218914A Expired - Fee Related JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5959395B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6324336B2 (ja) | 2014-03-31 | 2018-05-16 | 三ツ星ベルト株式会社 | 歯付きベルト |
JP6394136B2 (ja) * | 2014-07-14 | 2018-09-26 | 凸版印刷株式会社 | パッケージ基板およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4605887B2 (ja) * | 2000-10-30 | 2011-01-05 | 京セラ株式会社 | 実装用配線基板および半導体装置の実装構造 |
JP2003142817A (ja) * | 2001-10-30 | 2003-05-16 | Kyocera Corp | 半田印刷用マスクおよびこれを用いた配線基板の製造方法 |
JP2005268637A (ja) * | 2004-03-19 | 2005-09-29 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
TWI286829B (en) * | 2006-01-17 | 2007-09-11 | Via Tech Inc | Chip package |
JP5273333B2 (ja) * | 2006-12-28 | 2013-08-28 | 株式会社ジャパンディスプレイ | 表示装置 |
JP5164160B2 (ja) * | 2008-09-25 | 2013-03-13 | 日立マクセル株式会社 | 半導体装置とその製造方法 |
JP2010147418A (ja) * | 2008-12-22 | 2010-07-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20130105329A1 (en) * | 2010-08-02 | 2013-05-02 | Atotech Deutschland Gmbh | Method to form solder deposits and non-melting bump structures on substrates |
-
2012
- 2012-09-29 JP JP2012218914A patent/JP5959395B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2014072467A (ja) | 2014-04-21 |
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