JP6051143B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP6051143B2 JP6051143B2 JP2013225187A JP2013225187A JP6051143B2 JP 6051143 B2 JP6051143 B2 JP 6051143B2 JP 2013225187 A JP2013225187 A JP 2013225187A JP 2013225187 A JP2013225187 A JP 2013225187A JP 6051143 B2 JP6051143 B2 JP 6051143B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- conductor
- pad
- height
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
3A 搭載部
10 半導体素子接続パッド
10a 独立パッド
10b 統合パッド
11 導体柱
11a 独立導体柱
11b 統合導体柱
S 半導体素子
T 半導体素子の電極
Claims (2)
- 上面に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部に形成されており、半導体素子の1個ずつの電極に対して電気的に独立して接続される独立パッドおよび前記半導体素子の複数個の電極に対して電気的に一つに繋がった状態で接続される統合パッドを含む複数の半導体素子接続パッドと、前記独立パッド上に形成された独立導体柱および前記統合パッド上に形成されており、前記独立導体柱を環状に取り囲む統合導体柱を含む導体柱と、前記絶縁基板および前記半導体素子接続パッド上に形成されており、前記半導体素子接続パッドおよび前記導体柱の下端部を埋設するソルダーレジスト層と、を具備して成り、前記ソルダーレジスト層は、前記独立導体柱とこれを取り囲む前記統合導体柱との間の高さが前記導体柱の上端よりも10μm以下低い第1の高さであり、それ以外の前記搭載部における高さが前記導体柱の上端よりも35μm以上低い第2の高さであることを特徴とする配線基板。
- 前記ソルダーレジスト層は、前記搭載部の周囲を前記第1の高さで取り囲む枠状の領域を有すること特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013225187A JP6051143B2 (ja) | 2013-10-30 | 2013-10-30 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013225187A JP6051143B2 (ja) | 2013-10-30 | 2013-10-30 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015088584A JP2015088584A (ja) | 2015-05-07 |
JP6051143B2 true JP6051143B2 (ja) | 2016-12-27 |
Family
ID=53051072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013225187A Expired - Fee Related JP6051143B2 (ja) | 2013-10-30 | 2013-10-30 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6051143B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4605887B2 (ja) * | 2000-10-30 | 2011-01-05 | 京セラ株式会社 | 実装用配線基板および半導体装置の実装構造 |
JP2010147418A (ja) * | 2008-12-22 | 2010-07-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP5415632B2 (ja) * | 2011-07-25 | 2014-02-12 | 日本特殊陶業株式会社 | 配線基板 |
-
2013
- 2013-10-30 JP JP2013225187A patent/JP6051143B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2015088584A (ja) | 2015-05-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101085733B1 (ko) | 전자소자 내장 인쇄회로기판 및 그 제조방법 | |
JP6013960B2 (ja) | 配線基板 | |
JP2012054297A (ja) | 配線基板およびその製造方法 | |
KR101878242B1 (ko) | 배선 기판 및 그 제조 방법 | |
KR20160066311A (ko) | 반도체 패키지 및 반도체 패키지의 제조방법 | |
JP2012054295A (ja) | 配線基板およびその製造方法 | |
KR101893839B1 (ko) | 배선 기판 | |
JP2015207676A (ja) | 配線基板およびその製造方法 | |
JP5959395B2 (ja) | 配線基板 | |
KR20140079204A (ko) | 반도체 패키지용 기판, 이를 이용한 반도체 패키지 및 그 제조 방법 | |
JP6051143B2 (ja) | 配線基板 | |
JP2012033786A (ja) | 配線基板 | |
JP2016127134A (ja) | 配線基板 | |
JP4235092B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP2014096584A (ja) | プリント回路基板及びプリント回路基板の製造方法 | |
JP2018120954A (ja) | 配線基板 | |
US9412688B2 (en) | Wiring board | |
JP4439248B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP5997197B2 (ja) | 配線基板 | |
JP2016012588A (ja) | 配線基板 | |
JP2013247307A (ja) | 配線基板 | |
JP2014192363A (ja) | 配線基板およびその製造方法 | |
JP2016127132A (ja) | 配線基板 | |
JP2017152449A (ja) | 配線基板 | |
JP2015103779A (ja) | 配線基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20151125 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20160401 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161021 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20161027 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161128 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6051143 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |