JP2014072467A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2014072467A JP2014072467A JP2012218914A JP2012218914A JP2014072467A JP 2014072467 A JP2014072467 A JP 2014072467A JP 2012218914 A JP2012218914 A JP 2012218914A JP 2012218914 A JP2012218914 A JP 2012218914A JP 2014072467 A JP2014072467 A JP 2014072467A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- resin layer
- integrated circuit
- circuit element
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】半導体集積回路素子Sの1個ずつの電極Tに対して電気的に独立して接続される独立パッド10aと、半導体集積回路素子Sの複数個の電極Tに対して電気的に共通して接続される統合パッド10bとを含む複数の半導体素子接続パッド10を、上面側の最外層の絶縁樹脂層2の下に有しており、この最外層の絶縁樹脂層2に設けた開口部11a、11b内の独立パッド10a上および統合パッド10b上に、最外層の絶縁樹脂層2の上面から突出する導体柱11a、11bが形成されて成る配線基板であって、統合パッド10b上に形成された導体柱11bは、複数個の電極Tに対応する部分が1つに繋がった状態で最上層のの絶縁樹脂層2の上面から突出している。
【選択図】図1
Description
10 半導体素子接続パッド
10a 独立パッド
10b 統合パッド
11 導体柱
11b 統合パッド上に形成された導体柱
G 間隙
S 半導体集積回路素子
T 半導体集積回路素子の電極
Claims (2)
- 第1の絶縁樹脂層と、該第1の絶縁樹脂層上に形成されており、半導体集積回路素子の1個ずつの電極に対して電気的に独立して接続される独立パッドおよび半導体集積回路素子の複数個の電極に対して電気的に共通して接続される統合パッドを含む複数の半導体素子接続パッドと、前記第1の絶縁樹脂層および前記半導体素子接続パッド上に形成されており、前記半導体素子接続パッドの上面中央部を露出させる開口部を有する第2の絶縁樹脂層と、前記開口部内の前記半導体素子接続パッド上に形成されており、前記第2の絶縁樹脂層の上面から突出する導体柱とを具備して成る配線基板であって、前記統合パッド上に形成された前記導体柱は、複数個の前記電極に対応する部分が1つに繋がった状態で前記第2の絶縁樹脂層の上面から突出していることを特徴とする配線基板。
- 前記統合パッド上に形成された前記導体柱は、前記第2の絶縁樹脂層の上面から突出する部分が間隙を介して複数に分かれていることを特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012218914A JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012218914A JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014072467A true JP2014072467A (ja) | 2014-04-21 |
JP5959395B2 JP5959395B2 (ja) | 2016-08-02 |
Family
ID=50747379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012218914A Expired - Fee Related JP5959395B2 (ja) | 2012-09-29 | 2012-09-29 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5959395B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016021481A (ja) * | 2014-07-14 | 2016-02-04 | 凸版印刷株式会社 | パッケージ基板およびその製造方法 |
EP3792521A1 (en) | 2014-03-31 | 2021-03-17 | Mitsuboshi Belting Ltd. | Toothed belt |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002134648A (ja) * | 2000-10-30 | 2002-05-10 | Kyocera Corp | 実装用配線基板および半導体装置の実装構造 |
JP2003142817A (ja) * | 2001-10-30 | 2003-05-16 | Kyocera Corp | 半田印刷用マスクおよびこれを用いた配線基板の製造方法 |
JP2005268637A (ja) * | 2004-03-19 | 2005-09-29 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
US20070164447A1 (en) * | 2006-01-17 | 2007-07-19 | Kwun-Yao Ho | Semiconductor package and fabricating method thereof |
JP2008166460A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 表示装置 |
JP2010080656A (ja) * | 2008-09-25 | 2010-04-08 | Kyushu Hitachi Maxell Ltd | 半導体装置とその製造方法 |
JP2010147418A (ja) * | 2008-12-22 | 2010-07-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
WO2012016932A1 (en) * | 2010-08-02 | 2012-02-09 | Atotech Deutschland Gmbh | Method to form solder deposits and non-melting bump structures on substrates |
-
2012
- 2012-09-29 JP JP2012218914A patent/JP5959395B2/ja not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002134648A (ja) * | 2000-10-30 | 2002-05-10 | Kyocera Corp | 実装用配線基板および半導体装置の実装構造 |
JP2003142817A (ja) * | 2001-10-30 | 2003-05-16 | Kyocera Corp | 半田印刷用マスクおよびこれを用いた配線基板の製造方法 |
JP2005268637A (ja) * | 2004-03-19 | 2005-09-29 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
US20070164447A1 (en) * | 2006-01-17 | 2007-07-19 | Kwun-Yao Ho | Semiconductor package and fabricating method thereof |
JP2008166460A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 表示装置 |
JP2010080656A (ja) * | 2008-09-25 | 2010-04-08 | Kyushu Hitachi Maxell Ltd | 半導体装置とその製造方法 |
JP2010147418A (ja) * | 2008-12-22 | 2010-07-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
WO2012016932A1 (en) * | 2010-08-02 | 2012-02-09 | Atotech Deutschland Gmbh | Method to form solder deposits and non-melting bump structures on substrates |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3792521A1 (en) | 2014-03-31 | 2021-03-17 | Mitsuboshi Belting Ltd. | Toothed belt |
JP2016021481A (ja) * | 2014-07-14 | 2016-02-04 | 凸版印刷株式会社 | パッケージ基板およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5959395B2 (ja) | 2016-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5280309B2 (ja) | 半導体装置及びその製造方法 | |
JP6013960B2 (ja) | 配線基板 | |
KR101085733B1 (ko) | 전자소자 내장 인쇄회로기판 및 그 제조방법 | |
US20180130761A1 (en) | Semiconductor package, manufacturing method thereof, and electronic element module using the same | |
JP2012054297A (ja) | 配線基板およびその製造方法 | |
JP6092752B2 (ja) | 配線基板 | |
JP2012054295A (ja) | 配線基板およびその製造方法 | |
KR101893839B1 (ko) | 배선 기판 | |
JP2015207677A (ja) | 配線基板 | |
JP5959395B2 (ja) | 配線基板 | |
JP6051143B2 (ja) | 配線基板 | |
JP2016127134A (ja) | 配線基板 | |
JP4235092B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP5761664B2 (ja) | 配線基板 | |
JP2009290044A (ja) | 配線基板 | |
JP2018120954A (ja) | 配線基板 | |
JP2011023627A (ja) | 半導体装置及びその製造方法 | |
JP2009290043A (ja) | 配線基板 | |
JP4227502B2 (ja) | 配線基板およびこれを用いた半導体装置 | |
JP2012119361A (ja) | 配線基板 | |
JP5997197B2 (ja) | 配線基板 | |
JP2014130974A (ja) | 配線基板 | |
JP2013175518A (ja) | 配線基板 | |
JP2013115060A (ja) | 配線基板 | |
JP2016225473A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150326 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20151014 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20151016 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151209 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20160401 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160607 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160621 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5959395 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |