KR940012602A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR940012602A KR940012602A KR1019930024011A KR930024011A KR940012602A KR 940012602 A KR940012602 A KR 940012602A KR 1019930024011 A KR1019930024011 A KR 1019930024011A KR 930024011 A KR930024011 A KR 930024011A KR 940012602 A KR940012602 A KR 940012602A
- Authority
- KR
- South Korea
- Prior art keywords
- wiring
- power supply
- semiconductor substrate
- shielding
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract 14
- 230000008878 coupling Effects 0.000 abstract 4
- 238000010168 coupling process Methods 0.000 abstract 4
- 238000005859 coupling reaction Methods 0.000 abstract 4
- 238000006073 displacement reaction Methods 0.000 abstract 2
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L2924/3025—Electromagnetic shielding
Abstract
본 발명은 차폐 배선이 반도체 기판과 전원 전위 또는 접지 전위 공급을 위한 전원 배선 사이에 배열되어 있는 반도체 장치에 관한 것이다. 반도체 기판의 전위 변위에 의해 나타나는 잡음은 차폐 배선에 의해서 상기 전원 배선에 전달되지 못한다. 한 양상에 있어서, 차폐 배선(1)은 전위를 반도체 기판상의 여러 회로에 공급하기 위한 Vss 배선과 기판(7)사이에 배열되어 있다. 이러한 차폐배선(1)은 M1칩 내부 배선(4), M2 칩 내부 배선(5), 접속부(40), 결합 배선(3), 및 결합 와이어(8)을 통해 접지 리드 프레임(18)에 접속된다. 차폐 배선(1)과 기판(7)사이에 결합 임피던스 (거의 정전 캐패시턴스(Css)에 기인함)은 크고 Vss 배선(2)와 기판(7)사이의 결합 임피던스 (거의 접합 커패시턴스(D)에 기인함)은 낮기 때문에, 기판(7)의 전위 변위에 의해 발생되는 잡음이 차폐 배선(1)에 전달되므로 Vss 배선(2)에는 거의 전달되지 않는다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체 장치의 제1실시예를 도시한 부분 사시도.
제4도는 반도체 칩의 구성예로써 CMOS 반전기 회로를 도시한 단면도.
Claims (6)
- 다수의 회로 소자들이 형성되는 반도체 기판; 상기 반도체 기판의 윗 표면에 형성된 절연층; 상기 절연층에 배열되어 있고 적어도 전원 배선을 포함하는 다수의 배선부; 상기 반도체 기판과 상기 전원 배선 사이의 한 위치에서 상기 절연층에 끼워져 있는 차폐 배선, 및 일정 전위를 상기 차폐 배선에 인가하는 수단을 포함하는 것윽 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 차폐 배선이 전원 전위를 제공하는 제1전원 배선과 접지 전위를 제공하는 제2전원 배선 위에 배열되는 것을 특징으로 하는 반도체 장치.
- 제1항 또는 제2항에 있어서, 상기 차폐 배선이 상기 전원 배선 보다 상기 반도체 기판에 더 가까운 위치에 배열되는 것을 특징으로 하는 반도체 장치.
- 제1항 또는 제2항에 있어서, 상기 차폐 배선이 상기 반도체 기판과 접촉되게 배열되는 것을 특징으로 하는 반도체 장치.
- 제1항, 제2항, 제3항 또는 제4항에 있어서, 상기 차폐 배선의 폭이 상기 전원 배선의 폭 보다 큰 것을 특징으로 하는 반도체 장치.
- 제1도전형 반도체 기판, 상기 반도체 기판 상에 형성된 제2도전형 차폐 영역 및 상기 차폐 영역 상의 제1도전형 또는 제2도전형 영역 내에 형성된 다수의 회로 소자를 포함하는 것을 특징으로 하는 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP92-327264 | 1992-11-12 | ||
JP32726492A JP3390875B2 (ja) | 1992-11-12 | 1992-11-12 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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KR940012602A true KR940012602A (ko) | 1994-06-23 |
KR100320057B1 KR100320057B1 (ko) | 2002-03-21 |
Family
ID=18197179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019930024011A KR100320057B1 (ko) | 1992-11-12 | 1993-11-12 | 반도체장치 |
Country Status (3)
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US (1) | US5594279A (ko) |
JP (1) | JP3390875B2 (ko) |
KR (1) | KR100320057B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100702034B1 (ko) * | 2006-05-12 | 2007-03-30 | 삼성전자주식회사 | 반도체 장치, 이 장치의 전원 노이즈 감소 방법 및 인쇄회로 기판 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09107048A (ja) | 1995-03-30 | 1997-04-22 | Mitsubishi Electric Corp | 半導体パッケージ |
JPH097373A (ja) * | 1995-06-20 | 1997-01-10 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
JP3501620B2 (ja) * | 1997-05-26 | 2004-03-02 | 株式会社 沖マイクロデザイン | 半導体集積回路 |
US6166403A (en) * | 1997-11-12 | 2000-12-26 | Lsi Logic Corporation | Integrated circuit having embedded memory with electromagnetic shield |
US6097195A (en) * | 1998-06-02 | 2000-08-01 | Lucent Technologies Inc. | Methods and apparatus for increasing metal density in an integrated circuit while also reducing parasitic capacitance |
US6963626B1 (en) | 1998-10-02 | 2005-11-08 | The Board Of Trustees Of The Leland Stanford Junior University | Noise-reducing arrangement and method for signal processing |
JP3374967B2 (ja) * | 1998-10-26 | 2003-02-10 | 日本電気株式会社 | 半導体集積回路 |
EP1071130A3 (en) * | 1999-07-14 | 2005-09-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device interconnection structure comprising additional capacitors |
JP3727220B2 (ja) * | 2000-04-03 | 2005-12-14 | Necエレクトロニクス株式会社 | 半導体装置 |
JP2001339047A (ja) * | 2000-05-29 | 2001-12-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP4553461B2 (ja) * | 2000-08-23 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体装置、その設計方法および設計装置 |
JP4083977B2 (ja) * | 2000-12-20 | 2008-04-30 | 富士通株式会社 | 半導体集積回路及び配線決定方法 |
JP2006506801A (ja) * | 2002-10-18 | 2006-02-23 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 周波数に独立な分圧器 |
JP2004214561A (ja) * | 2003-01-08 | 2004-07-29 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
KR100554369B1 (ko) | 2004-07-01 | 2006-03-03 | 윤국원 | 악보대의 높낮이 조절장치 |
US7286437B2 (en) * | 2005-06-17 | 2007-10-23 | International Business Machines Corporation | Three dimensional twisted bitline architecture for multi-port memory |
US20070098524A1 (en) * | 2005-10-31 | 2007-05-03 | Dunlap William L | Conical nut |
US20070200233A1 (en) * | 2005-12-14 | 2007-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad structures with reduced coupling noise |
US7368668B2 (en) * | 2006-02-03 | 2008-05-06 | Freescale Semiconductor Inc. | Ground shields for semiconductors |
JP4436334B2 (ja) * | 2006-03-02 | 2010-03-24 | パナソニック株式会社 | シールド基板、半導体パッケージ、及び半導体装置 |
US7885138B2 (en) * | 2007-10-19 | 2011-02-08 | International Business Machines Corporation | Three dimensional twisted bitline architecture for multi-port memory |
US8183663B2 (en) * | 2008-12-18 | 2012-05-22 | Samsung Electronics Co., Ltd. | Crack resistant circuit under pad structure and method of manufacturing the same |
US8441127B2 (en) * | 2011-06-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace structures with wide and narrow portions |
US9368454B2 (en) * | 2013-10-10 | 2016-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with shielding layer in post-passivation interconnect structure |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5721849A (en) * | 1980-07-14 | 1982-02-04 | Fujitsu Ltd | Semiconductor integrated circuit |
JPS5771165A (en) * | 1980-10-22 | 1982-05-01 | Toshiba Corp | Semiconductor device |
JPS5884455A (ja) * | 1981-11-13 | 1983-05-20 | Fujitsu Ltd | 半導体記憶装置 |
US4924293A (en) * | 1985-05-24 | 1990-05-08 | Hitachi, Ltd. | Semiconductor integrated circuit device |
JPS6344759A (ja) * | 1986-08-12 | 1988-02-25 | Canon Inc | 光電変換装置 |
NL8701997A (nl) * | 1987-08-26 | 1989-03-16 | Philips Nv | Geintegreerde halfgeleiderschakeling met ontkoppelde dc bedrading. |
US5179539A (en) * | 1988-05-25 | 1993-01-12 | Hitachi, Ltd., Hitachi Vlsi Engineering Corporation | Large scale integrated circuit having low internal operating voltage |
US5136357A (en) * | 1989-06-26 | 1992-08-04 | Micron Technology, Inc. | Low-noise, area-efficient, high-frequency clock signal distribution line structure |
US5262353A (en) * | 1992-02-03 | 1993-11-16 | Motorola, Inc. | Process for forming a structure which electrically shields conductors |
-
1992
- 1992-11-12 JP JP32726492A patent/JP3390875B2/ja not_active Expired - Lifetime
-
1993
- 1993-11-10 US US08/149,876 patent/US5594279A/en not_active Expired - Lifetime
- 1993-11-12 KR KR1019930024011A patent/KR100320057B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100702034B1 (ko) * | 2006-05-12 | 2007-03-30 | 삼성전자주식회사 | 반도체 장치, 이 장치의 전원 노이즈 감소 방법 및 인쇄회로 기판 |
Also Published As
Publication number | Publication date |
---|---|
JP3390875B2 (ja) | 2003-03-31 |
KR100320057B1 (ko) | 2002-03-21 |
JPH06151435A (ja) | 1994-05-31 |
US5594279A (en) | 1997-01-14 |
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