KR910013524A - 반도체집적회로장치 - Google Patents
반도체집적회로장치 Download PDFInfo
- Publication number
- KR910013524A KR910013524A KR1019900019524A KR900019524A KR910013524A KR 910013524 A KR910013524 A KR 910013524A KR 1019900019524 A KR1019900019524 A KR 1019900019524A KR 900019524 A KR900019524 A KR 900019524A KR 910013524 A KR910013524 A KR 910013524A
- Authority
- KR
- South Korea
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- pads
- wiring
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000009825 accumulation Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체집적회로장치의 평면도,
제2도는 제1실시예 장치의 패드 근방의 확대 평면도,
제3도는 제2도의 단면 A-A′선에 따른 단면도.
Claims (5)
- 반도체집적회로칩(10)의 주연부에 외부단자와 전기적으로 접속되는 패드(11a, 11b, 21a∼21c, 31a∼31c)카 배치되어 있는 반도체집적 회로장치에 있어서, 상기 패드는 복수개가 칩의 테두리를 따라서 두겹 이상의 열로 나란히 배치되고, 상기 패드와 내부회로를 전기적으로 접속하는 내부배선을 구성하는 배선층(14a, 14b, 24a∼24c)이 칩두께 방향으로 적어도 2층이상 설치되어 있는 것을 특징으로 하는 반도체집적회로장치.
- 제1항에 있어서, 상기 내부배선중 가장 외측에 배치되는 패드에 접속되는 내부배선이 장치표면으로부터 가장 깊은 위치에 설치된 배선층(14a, 24a)에 의해 형성되고, 이것 보다 내측에 배치된 패드로 향함에 따라 접속되는 내부배선이 장치표면으로부터 순차로 얕은 위치에 설치되는 배선층(14b, 24b, 24c)에 의해 형성되는 것을 특징으로 하는 반도체집적회로장치.
- 제1항에 있어서, 상기 내부배선에는 슬릿(18)이 형성되어 있는 것을 특징으로 하는 반도체집척회로장치.
- 제1항에 있어서, 상기 패드중 가장 외측에 존재하는 열에 배치된 패드(11a, 21a, 31a)만이 외부단자와 전기적으로 접속되는 것을 특징으로 하는 반도체집적회로장치.
- 제1항에 있어서, 상기 가장 외측에 존재하는 열에 배치된 패드(31a)의 배치피치가 그것 보다 내측에 존재하는 패드의 배치피치보다 큰 것을 특징으로 하는 반도체집적회로장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1-312276 | 1989-12-02 | ||
JP312276/1 | 1989-12-02 | ||
JP1312276A JPH06105709B2 (ja) | 1989-12-02 | 1989-12-02 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910013524A true KR910013524A (ko) | 1991-08-08 |
KR930005493B1 KR930005493B1 (ko) | 1993-06-22 |
Family
ID=18027292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900019524A KR930005493B1 (ko) | 1989-12-02 | 1990-11-30 | 반도체집적회로장치 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0431490B1 (ko) |
JP (1) | JPH06105709B2 (ko) |
KR (1) | KR930005493B1 (ko) |
DE (1) | DE69013646T2 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5149674A (en) * | 1991-06-17 | 1992-09-22 | Motorola, Inc. | Method for making a planar multi-layer metal bonding pad |
WO1993012540A1 (en) * | 1991-12-10 | 1993-06-24 | Vlsi Technology, Inc. | Integrated circuit with variable pad pitch |
US5691218A (en) * | 1993-07-01 | 1997-11-25 | Lsi Logic Corporation | Method of fabricating a programmable polysilicon gate array base cell structure |
EP0693783B1 (en) * | 1994-07-13 | 1999-09-22 | United Microelectronics Corporation | Method for eliminating process antenna effect |
EP0693781B1 (en) * | 1994-07-13 | 2002-10-02 | United Microelectronics Corporation | Grounding method for eliminating process antenna effect |
EP0693782B1 (en) * | 1994-07-13 | 2000-11-15 | United Microelectronics Corporation | Method for reducing process antenna effect |
US5552333A (en) * | 1994-09-16 | 1996-09-03 | Lsi Logic Corporation | Method for designing low profile variable width input/output cells |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
JP3989038B2 (ja) * | 1996-04-17 | 2007-10-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JPH10163319A (ja) * | 1996-11-29 | 1998-06-19 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3472455B2 (ja) * | 1997-09-12 | 2003-12-02 | 沖電気工業株式会社 | 半導体集積回路装置及びそのパッケージ構造 |
US6031258A (en) * | 1998-03-06 | 2000-02-29 | S3 Incorporated | High DC current stagger power/ground pad |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211248A (en) * | 1981-06-22 | 1982-12-25 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1989
- 1989-12-02 JP JP1312276A patent/JPH06105709B2/ja not_active Expired - Fee Related
-
1990
- 1990-11-30 EP EP90122955A patent/EP0431490B1/en not_active Expired - Lifetime
- 1990-11-30 DE DE69013646T patent/DE69013646T2/de not_active Expired - Fee Related
- 1990-11-30 KR KR1019900019524A patent/KR930005493B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0431490B1 (en) | 1994-10-26 |
KR930005493B1 (ko) | 1993-06-22 |
DE69013646T2 (de) | 1995-04-13 |
JPH03173433A (ja) | 1991-07-26 |
EP0431490A1 (en) | 1991-06-12 |
JPH06105709B2 (ja) | 1994-12-21 |
DE69013646D1 (de) | 1994-12-01 |
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Payment date: 20040331 Year of fee payment: 12 |
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