CN102110666B - 集成电路芯片封装及实体层介面排列 - Google Patents
集成电路芯片封装及实体层介面排列 Download PDFInfo
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Abstract
本发明公开一种集成电路封装及实体层介面排列,该集成电路封装包括一集成电路芯片、一封装载板及多个将集成电路芯片连接至封装载板的导电凸块。集成电路芯片包括一基底及一配置在基底的一有源面上的集成电路层。有源面具有一核心区及一围绕着核心区的信号区。集成电路层包括一第一实体层介面。第一实体层介面包括多个第一凸块垫及多个分别电性连接至这些第一凸块垫的内部垫。这些第一内部垫多排地排列于信号区。
Description
技术领域
本发明涉及一种适用于集成电路芯片的实体层介面排列。
背景技术
集成电路芯片(IC chip)通常包括一基底(例如:硅晶片)及配置在基底的一有源面(active surface)上的集成电路层(IC layer),在此「有源面」是指在基底上配置集成电路层的那一面。一般来说,集成电路层由多个内部元件(例如:MOS晶体管、电感、电容等)、多层介电层以及多层图案化金属层等构成。多层介电层以及多层图案化金属层相互堆叠,且图案化金属层会将内部元件的信号传递至外界或是由外界传递至内部。无论集成电路芯片的内部元件、多层图案化金属层如何配置,若要将信号传递至外界(或传递至内部),皆须透过集成电路层的最外层来达成。以集成电路层的最外层的这个平面来看,其包括一核心区(core area)与围绕着核心区的一信号区(signal area),其中核心区提供核心电源(core power)与核心接地(coreground),而信号区提供信号。此外,信号区还包括多个实体层介面(physicallayer interface),这些实体层介面单排地(in single row)排列于核心区周围,并分别提供不同功能的信号传输,即每个实体层介面作为内部元件与外部元件电连接的桥梁,并且提供特定功能的信号传输。在某些情况下,多个实体层介面共同提供某一特定功能的信号传输。
对于采用倒装封装(flip chip package)技术的集成电路芯片,集成电路层的最外层的每个实体层介面包括多个凸块垫,这些凸块垫依设计规则(design rule)而排列。此外,每个实体层介面还包括多个内部垫及多条重布线(redistribution line),这些内部垫及重布线位于对应的凸块垫下方,且位于集成电路层中。这些内部垫单排地(in single row)排列,而这些重布线将这些凸块垫分别电性连接至这些对应的内部垫。
当单一的集成电路芯片提供的功能越来越多,表示需要更多的凸块垫以作为信号的输出或输入之用。此外,当工艺技术越来越进步,表示芯片的内部元件、图案化金属层的尺寸可以进一步缩小,即表示整个集成电路层的面积可以缩小。因此,在芯片上设计上需有所改进,以符合时势所趋。
发明内容
本发明提供一种集成电路封装,其可提升电性效能。
本发明提供一种实体层介面排列,其可提升电性效能。
本发明提出一种集成电路封装,包括一集成电路芯片、一封装载板及多个将集成电路芯片连接至封装载板的导电凸块。集成电路芯片包括一基底及一配置在基底的一有源面上的集成电路层。有源面具有一核心区及一围绕着核心区的信号区。集成电路层包括一第一实体层介面。第一实体层介面包括多个第一凸块垫及多个分别电性连接至这些第一凸块垫的内部垫。这些第一内部垫多排地排列于信号区。
本发明还提出一种实体层介面排列,其包括上述的第一实体层介面。
基于上述,本发明通过将内部垫多排地排列于信号区以缩短电流路径,这有助于提升电性效能。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1为本发明的一实施例的一种集成电路芯片的局部剖面图。
图2为图1的部分2的细部放大图。
图3绘示图1的集成电路芯片的多个实体层介面。
图4绘示图3的部分4的四个实体层介面的凸块垫。
图5绘示图4的这些实体层介面的内部垫及重布线。
图6绘示本发明的另一实施例的内部接垫的排列。
图7为本发明的另一实施例的一种集成电路封装的侧视图。
附图标记说明
100:集成电路芯片
101、103、105:实体层介面
110:基底
112:有源面
112a:核心区
112b:信号区
120:集成电路层
122、122-1、122-2、122-3、122-4:凸块垫
124、124-1、124-2、124-3、124-4:内部垫
126、126-1、126-2、126-3、126-4:重布线
128、128-1、128-2:电源环
P1、P2:几何平面
PHY、PHY-1、PHY-2、PHY-3、PHY-4:实体层介面
R1、R2、R3、R4、R5、R6:排
具体实施方式
图1为本发明的一实施例的一种集成电路芯片的局部剖面图,而图2为图1的部分2的细部放大图。请参考图1及图2,在本实施例中,集成电路芯片100包括一基底110及一集成电路层120,其中基底110例如是硅晶片,其具有一有源面112,而集成电路层120配置在有源面112上。集成电路层120由多个内部元件(例如:MOS晶体管、电感、电容等)、多层介电层以及多层图案化金属层等构成,在图1中并未绘示这些构件,而仅以标号120表示此集成电路层。靠近外部的集成电路层120具有多个凸块垫122(仅绘示其二)、多个内部垫124(仅绘示其二)及多条重布线126(仅绘示其二)。这些凸块垫122位于集成电路层120的最外层,用以安装一个导电凸块B,并分别经由这些重布线126而电性连接至这些内部垫124。
图3绘示图1的集成电路芯片的俯视示意图,即绘示集成电路层120的最外层。请参考图1及图3,有源面112包括一核心区112a与一围绕着核心区112a的信号区112b,其中集成电路层120包括多个核心电源凸块垫(未绘示)与核心接地凸块垫(未绘示)于核心区112a,用以提供电源或接地传输,而集成电路层120包括多个实体层介面PHY于信号区112b,用以提供特定功能的信号传输,而数个实体层介面PHY可组成一实体层介面排列。在一实施例中,不同的实体层介面PHY可提供不同功能的信号传输。在另一实施例中,多个实体层介面PHY可共同提供某一特定功能的信号传输。值得一提的是,每一实体层介面PHY包括多个凸块垫122,其包括信号凸块垫、电源凸块垫及接地凸块垫。然而,不同于核心区的核心电源凸块垫及核心接地凸块垫,此处的电源凸块垫及接地凸块垫仅供对应的实体层介面PHY所使用。
更进一步来说,每个实体层介面PHY的局部剖面图类似图2所绘示,其包括多个凸块垫122(图2仅绘示其二)。此外,每个实体层介面PHY还包括多个内部垫124(图2仅绘示其二)及多条重布线126(图2仅绘示其二),内部垫124及重布线126位于对应的凸块垫122下方,且位于如图1所绘示的集成电路层120中。
图4绘示图3的部分4的四个实体层介面PHY的凸块垫,且实体层介面PHY中的凸块垫排列仅为示意,并非用以限定这些凸块垫的排列。请参考图3及图4,集成电路层120包括一第一实体层介面PHY-1及一第二实体层介面PHY-2,其中第一实体层介面PHY-1及第二实体层介面PHY-2双排地排列于图3的核心区112a外围而位于信号区112b内。此外,第二实体层介面PHY-2为第一实体层介面PHY-1的垂直镜像,此处的「垂直」是指第二实体层介面PHY-2与第一实体层介面PHY-1位于不同排,即在X1方向上,二者相对于核心区112a的距离不同。具体而言,第一实体层介面PHY-1包括多个第一凸块垫122-1。第二实体层介面PHY-2包括多个第二凸块垫122-2。这些第二凸块垫122-2为这些第一凸块垫122-1相对于一垂直于图1的有源面112的第一几何平面P1的镜像。详言之,这些第一凸块垫122-1可能是信号、电源、接地凸块垫,而在第二实体层介面PHY-2中,会有以第一几何平面P1呈镜像排列的信号、电源、接地凸块垫。
在本实施例中,集成电路层120还可包括一第三实体层介面PHY-3及一第四实体层介面PHY-4,其中第一实体层介面PHY-1与第三实体层介面PHY-3排成同一排而位于图3的核心区112a外围而位于信号区112b内;同样地,第二实体层介面PHY-2与第四实体层介面PHY-4排成同一排而位于图3的核心区112a外围而位于信号区112b内。换言之,第一实体层介面PHY-1、第二实体层介面PHY-2、第三实体层介面PHY-3及第四实体层介面PHY-4双排地排列于核心区112a外围而位于信号区112b内。第三实体层介面PHY-3及第四实体层介面PHY-4分别为第一实体层介面PHY-1及第二实体层介面PHY-2的水平镜像,此处的「水平」是指第三实体层介面PHY-3与第一实体层介面PHY-1位于同一排,或第四实体层介面PHY-4与第二实体层介面PHY-2位于同一排,即在X1方向上,同一排的实体层介面PHY相对于核心区112a的距离相同。
具体而言,第三实体层介面PHY-3包括多个第三凸块垫122-3,而这些第三凸块垫122-3为这些第一凸块垫122-1相对于一垂直于图1的有源面112的第二几何平面P2的镜像。第四实体层介面PHY-4包括多个第四凸块垫122-4,而这些第四凸块垫122-4为这些第二凸块垫122-2相对于一垂直于图1的有源面112的第二几何平面P2的镜像。在本实施例中,第一几何平面P1与第二几何平面P2彼此垂直。
值得注意的是,上述所指的双排是相较于图3的实体层介面101、103、105沿着X1方向以单排方式排列而言。更进一步来说,在本实施例中,实体层介面PHY-1与PHY-3沿着X2方向单排排列;同样地,实体层介面PHY-2与PHY-4亦沿着X2方向单排排列。但整体来说,实体层介面PHY-1、PHY-2、PHY-3与PHY-4在X1方向呈现双排排列。在以往的电路设计中,这些实体层介面PHY都是以单排的方式排列,如此导致整体的芯片尺寸无法缩小。然而,随着工艺的演进,工艺的线距与线宽皆进一步缩小,故核心区112a所占的面积可以缩小,信号区112b的可用面积变大,故实体层介面PHY可以双排的方式排列。
另外,上述的这些实体层介面PHY-1~4相对于几何平面P1(及P2)以镜像排列适用于这些实体层介面PHY用于共同提供某一特定功能的信号传输,例如:多个实体层介面PHY共同提供双倍数据速率(DDR;Double DataRate)存储器、通用串行总线(USB;Universal Serial Bus)或串行先进技术附件(SATA;Serial Advanced Technology Attachment)等的信号传递。更进一步来说,在以往的设计中,会将共同提供某一特定功能的这些实体层介面PHY以单排的方式(如图3的实体层介面101、103、105的排列)排列在一起,且彼此并没有镜像对称关系。如此在信号传输上,可能导致不同位置的实体层介面PHY虽共同提供某一特定功能,但其传输路径长度不尽相同,而影响传输品质,甚至造成信号错误传递。因此,在本案中,若一特定功能需由多个实体层介面共同提供,则可如本实施例以双排方式排列;反之,若一特定功能,仅需由一个实体层介面提供则可如实体层介面101、103、105以单排方式排列。除此之外,上述的实体层介面PHY的双排排列,并不以4个实体层介面PHY作为一个单位为限。在一实施例中,也可以6个实体层介面PHY以垂直或水平镜像做排列。
图5绘示图4的这些实体层介面的内部垫及重布线,而单一的实体层介面及其内部垫及重布线剖面图如图2所示。请参考图5,在本实施例中,第一实体层介面PHY-1还包括多个第一内部垫124-1,第一内部垫124-1多排地排列于信号区112b,这些第一内部垫124-1例如是排列成三排R1、R2及R3,其中排R1及排R2相邻,而排R2与排R3相隔一段距离。在本实施例中,这些第一内部垫124-1的形状可为矩形,特别是长方形。第二实体层介面PHY-2还包括多个第二内部垫124-2,第二内部垫124-2多排地排列于信号区112b,这些第二内部垫124-2例如是排列成三排R4、R5及R6,其中排R4及排R5相邻,而排R5与排R6相隔一段距离。在本实施例中,这些第二内部垫124-2的形状可为矩形,特别是长方形。这些第二内部垫124-2为这些第一内部垫124-1相对于第一几何平面P1的镜像。
在本实施例中,第一实体层介面PHY-1还可包括多个第一重布线126-1,而这些第一重布线126-1分别将这些第一凸块垫122-1电性连接至这些第一内部垫124-1。第二实体层介面PHY-2还可包括多个第二重布线126-2,而这些第二重布线126-2分别将这些第二凸块垫122-2电性连接至这些第二内部垫124-2。这些第二重布线126-2为这些第一重布线126-1相对于第一几何平面P1的镜像。
值得注意的是,在以往实体层介面的设计中,仅会在靠近实体层介面的边缘配置内部垫,例如:排R1的位置。然而,如此的设计会导致靠近第一几何平面P1的凸块垫需透过较长的重布线才可与内部垫电性连接,而影响信号传递品质。对于单一的实体层介面而言,本案通过多排的内部垫,可以缩短重布线的长度,以确保信号传递品质。
在本实施例中,第三实体层介面PHY-3还包括多个第三内部垫124-3,这些第三内部垫124-3为这些第一内部垫124-1相对于第二几何平面P2的镜像。同样地,第三内部垫124-3多排地排列于信号区112b。此外,第四实体层介面PHY-4还包括多个第四内部垫124-4,这些第四内部垫124-4为这些第二内部垫124-2相对于第二几何平面P2的镜像。同样地,第四内部垫124-4多排地排列于信号区112b。
在本实施例中,第三实体层介面PHY-3还可包括多个第三重布线126-3,这些第三重布线126-3分别将这些第三凸块垫122-3电性连接至这些第三内部垫124-3,这些第三重布线126-3为这些第一重布线126-1相对于第二几何平面P2的镜像。此外,第四实体层介面PHY-4还可包括多个第四重布线126-4,这些第四重布线126-4分别将这些第四凸块垫122-4电性连接至这些第四内部垫124-4,这些第四重布线126-4为这些第二重布线126-2相对于第二几何平面P2的镜像。
值得注意的是,在本实施例中,上述的这些内部垫可能是用于信号及电源的传输,故信号凸块垫及电源凸块垫是利用对应的重布线与对应的内部垫作电性上及物理上的连接。
在本实施例中,集成电路层120还可包括多个电源环128-1,其实体结构如同图2的电源环128。电源环128-1位于同一排(R1、R2或R3)的这些第一内部垫124-1下方,以提供电压至第一实体层介面PHY-1。电源环128-1还位于同一排(R1、R2或R3)的这些第三内部垫124-3下方,以提供电压至第三实体层介面PHY-3。此外,集成电路层120还可包括多个电源环128-2,其实体结构亦如同图2的电源环128。电源环128-2位于同一排(R4、R5或R6)的这些第二内部垫124-2,以提供电压至第二实体层介面PHY-2。电源环128-2还位于同一排(R4、R5或R6)的这些第四内部垫124-4,以提供电压至第四实体层介面PHY-4。特别是,此处的这些电源环128-1与128-2同样亦相对于第二几何平面P2而呈镜像排列,如此一来,若第二实体层介面PHY-2或第四实体层介面PHY-4需要电压时,可以直接由第二实体层介面PHY-2或第四实体层介面PHY-4中对应的电源环128-2取得,而不再由电路径较长的第一实体层介面PHY-1或第三实体层介面PHY-3中的电源环128-1提供,以维持良好的电性品质。而且,单一实体层介面中的多排的电源环,更可进一步缩短传输路径。
值得一提是,在以往的设计中,每一个实体层介面PHY中的凸块垫分布是属于「窄型」的分布;而在本案中,每一个实体层介面PHY中的凸块垫分布是属于「宽型」的分布。更进一步来说,以图3的标记「PHY 」的实体层介面为例,假设这个实体层介面PHY有24个凸块垫,在以往的设计中,会在X1方向上配置8个,X2方向上配置3个,甚至在X1方向上配置12个,X2方向上配置2个,以缩小实体层介面PHY的尺寸,进一步缩小芯片的面积。反观本案,由于部分的实体层介面采取双排排列,信号区112b的可用面积变大,故可在X1方向上配置6个,X2方向上配置4个。如此一来,当凸块垫利用重布线与对应的内部垫连接时,最靠近核心区112a的凸块垫,其对应的重布线长度(即实体层介面PHY中最长的重布线长度)可以缩短,如此可以缩短传递的路径,避免信号衰减。除此之外,本案的实体层介面中还配置多排的内部垫,因此可更进一步缩短重布线的长度。
在本实施例中,这些第一凸块垫122-1包括多个信号凸块垫、多个电源凸块垫及多个接地凸块垫,而这些信号凸块垫的数量与这些电源凸块垫的数量的比值介于2至8。因为在结构及电性上的镜射,这些第二凸块垫122-2、这些第三凸块垫122-3或这些第四凸块垫122-4所具有的这些信号凸块垫的数量与这些电源凸块垫的数量的比值亦介于2至8。
请再参考图3以及图5,在上述的实施例中虽然是以4个实体层介面PHY进行描述,但不限定于此。以图3的单排的实体层介面101、103或105为例,单一的实体层介面101、103或105亦可采用如图5的实体层介面PHY-1、PHY-2、PHY-3或PHY-4的设计。换言之,在单一的实体层介面101、103或105中,亦可包括多排的内部垫排列于信号区112b中,或是包括对应的多个电源环。如此一来,对于单排的实体层介面亦可有效地缩短信号传输路径,以维持信号品质。
图6绘示本发明的另一实施例的内部接垫的排列。请参考图6,不同于图5的第一实体层介面PHY-1的这些第一内部垫124-1的长度方向均垂直于这些排R1、R2及R3的延伸方向,在图6的第一实体层介面PHY-1中,位于同一排R1的这些第一内部垫124-1的长度方向垂直于排R1的延伸方向,但是位于同一排R2的这些第一内部垫124-1的长度方向平行于排R2的延伸方向。
图7为本发明的另一实施例的一种集成电路封装的侧视图。请参考图7,在本实施例中,集成电路封装200包括一集成电路芯片202、一封装载板204及多个导电凸块206。集成电路芯片202相同于图1所示的集成电路芯片100,并经由这些导电凸块206来连接于封装载板204。在本实施例中,封装载板204可为一无核心线路板(coreless wired board)。所谓的无核心线路板是一种采用不含玻纤的树脂作为其介电层的线路板,这有助于降低导电通孔(conductive through via)的尺寸以提高线路板的布线密度。如此一来,本发明的具有双排排列的实体层介面PHY可搭配上述的无核心线路板进行芯片封装工艺。
综上所述,本发明通过将内部垫多排地排列于信号区以缩短电流路径,这有助于提升电性效能。再者,本发明通过垂直镜射及水平镜射将一实体层介面复制于其旁侧而形成一实体层介面排列,这亦有助于提升电性效能。此外,本发明通过将这些实体层介面双排地排列于有源面的信号区,这有助于缩短信号传输路径及缩小芯片尺寸。
虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求所界定为准。
Claims (18)
1.一种集成电路封装,包括:
一集成电路芯片;
一封装载板;以及
多个导电凸块,该集成电路芯片经由该多个导电凸块连接于该封装载板,
其中该集成电路芯片包括:
一基底,具有一有源面,该有源面具有一核心区及一围绕着该核心区的信号区;以及
一集成电路层,配置在该有源面上,并包括:
一第一实体层介面,包括:
多个第一凸块垫;以及
多个第一内部垫,分别电性连接至该多个第一凸块垫,其中该多个第一内部垫多排地排列于该信号区。
2.如权利要求1所述的集成电路封装,其中排成一排的该多个第一内部垫的长度方向垂直于该排的延伸方向,而排成另一排的该多个第一内部垫的长度方向平行于该另一排的延伸方向。
3.如权利要求1所述的集成电路封装,其中该集成电路层还包括多个电源环,且排成一排的该多个第一内部垫下方对应配置该多个电源环的其中之一。
4.如权利要求1所述的集成电路封装,其中该集成电路层还包括:
一第二实体层介面,包括:
多个第二凸块垫;以及
多个第二内部垫,多排地排列于该信号区且分别电性连接至该多个第二凸块垫,
其中该多个第二凸块垫为该多个第一凸块垫相对于垂直于该有源面的一第一几何平面的镜像,而该多个第二内部垫为该多个第一内部垫相对于该第一几何平面的镜像。
5.如权利要求4所述的集成电路封装,其中该集成电路层还包括多个第一电源环与多个第二电源环,排成一排的该多个第一内部垫下方对应配置该多个第一电源环的其中之一,排成一排的该多个第二内部垫下方对应配置该多个第二电源环的其中之一,且该多个第二电源环为该多个第一电源环相对于垂直于该有源面的该第一几何平面的镜像。
6.如权利要求4所述的集成电路封装,其中该集成电路层还包括:
一第三实体层介面,包括:
多个第三凸块垫;以及
多个第三内部垫,多排地排列于该信号区且分别电性连接至该多个第三凸块垫;以及
一第四实体层介面,包括:
多个第四凸块垫;以及
多个第四内部垫,多排地排列于该信号区且分别电性连接至该多个第四凸块垫,
其中该多个第三凸块垫为该多个第一凸块垫相对于垂直于该有源面及该第一几何平面的一第二几何平面的镜像,该多个第三内部垫为该多个第一内部垫相对于该第二几何平面的镜像,
并且该多个第四凸块垫为该多个第二凸块垫相对于该第二几何平面的镜像,且该多个第四内部垫为该多个第二内部垫相对于该第二几何平面的镜像。
7.如权利要求6所述的集成电路封装,其中该集成电路层还包括多个第一电源环与多个第二电源环,排成一排的该多个第一内部垫与该多个第三内部垫的下方,对应配置该多个第一电源环的其中之一,排成一排的该多个第二内部垫与该多个第四内部垫的下方对应配置该多个第二电源环的其中之一,且该多个第二电源环为该多个第一电源环相对于垂直于该有源面的该第一几何平面的镜像。
8.如权利要求1所述的集成电路封装,其中该多个第一凸块垫包括多个信号凸块垫、多个电源凸块垫及多个接地凸块垫。
9.如权利要求1所述的集成电路封装,其中该多个第一凸块垫包括多个信号凸块垫及多个电源凸块垫,该多个信号凸块垫的数量与该多个电源凸块垫的数量的比值介于2至8。
10.一种实体层介面排列件,适于配置在一集成电路芯片的一基底的一有源面的上方,该有源面具有一核心区及一围绕着该核心区的信号区,该实体层介面排列件包括:
第一实体层介面,包括:
多个第一凸块垫;以及
多个第一内部垫,分别电性连接至该多个第一凸块垫,其中该多个第一内部垫多排地排列于该信号区。
11.如权利要求10所述的实体层介面排列件,其中排成一排的该多个第一内部垫的长度方向垂直于该排的延伸方向,而排成另一排的该多个第一内部垫的长度方向平行于该另一排的延伸方向。
12.如权利要求10所述的实体层介面排列件,还包括多个电源环,且排成一排的该多个第一内部垫下方对应配置该多个电源环的其中之一。
13.如权利要求10所述的实体层介面排列件,其中该实体层介面排列件还包括:
第二实体层介面,包括:
多个第二凸块垫;以及
多个第二内部垫,多排地排列于该信号区且分别电性连接至该多个第二凸块垫,
其中该多个第二凸块垫为该多个第一凸块垫相对于垂直于该有源面的一第一几何平面的镜像,而该多个第二内部垫为该多个第一内部垫相对于该第一几何平面的镜像。
14.如权利要求13所述的实体层介面排列件,还包括多个第一电源环与多个第二电源环,排成一排的该多个第一内部垫下方对应配置该多个第一电源环的其中之一,排成一排的该多个第二内部垫下方对应配置该多个第二电源环的其中之一,且该多个第二电源环为该多个第一电源环相对于垂直于该有源面的该第一几何平面的镜像。
15.如权利要求13所述的实体层介面排列件,还包括:
一第三实体层介面,包括:
多个第三凸块垫;以及
多个第三内部垫,多排地排列于该信号区且分别电性连接至该多个第三凸块垫;以及
一第四实体层介面,包括:
多个第四凸块垫;以及
多个第四内部垫,多排地排列于该信号区且分别电性连接至该多个第四凸块垫,
其中该多个第三凸块垫为该多个第一凸块垫相对于垂直于该有源面及该第一几何平面的一第二几何平面的镜像,该多个第三内部垫为该多个第一内部垫相对于该第二几何平面的镜像,
并且该多个第四凸块垫为该多个第二凸块垫相对于该第二几何平面的镜像,且该多个第四内部垫为该多个第二内部垫相对于该第二几何平面的镜像。
16.如权利要求15所述的实体层介面排列件,还包括多个第一电源环与多个第二电源环,排成一排的该多个第一内部垫与该多个第三内部垫的下方,对应配置该多个第一电源环的其中之一,排成一排的该多个第二内部垫与该多个第四内部垫的下方对应配置该多个第二电源环的其中之一,且该多个第二电源环为该多个第一电源环相对于垂直于该有源面的该第一几何平面的镜像。
17.如权利要求10所述的实体层介面排列件,其中该多个第一凸块垫包括多个信号凸块垫、多个电源凸块垫及多个接地凸块垫。
18.如权利要求10所述的实体层介面排列件,其中该多个第一凸块垫包括多个信号凸块垫及多个电源凸块垫,该多个信号凸块垫的数量与该多个电源凸块垫的数量的比值介于2至8。
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