JP4921724B2 - 半導体装置におけるパッド部の配線構造 - Google Patents
半導体装置におけるパッド部の配線構造 Download PDFInfo
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- JP4921724B2 JP4921724B2 JP2005140499A JP2005140499A JP4921724B2 JP 4921724 B2 JP4921724 B2 JP 4921724B2 JP 2005140499 A JP2005140499 A JP 2005140499A JP 2005140499 A JP2005140499 A JP 2005140499A JP 4921724 B2 JP4921724 B2 JP 4921724B2
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- bias
- pad
- wiring
- semiconductor device
- pads
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 239000000523 sample Substances 0.000 claims description 5
- 238000005452 bending Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
上記の構成を有する本発明に係る半導体装置におけるパッド部の配線構造では、図4及び図5に示すように、Va2、Vb2、Vc2、またはVx2と示された各第1バイアス配線23がパッドアレイの両側に配置され、それぞれパッド21と電気的に接続されて、半導体装置を動作させる。この場合、パッド21と第1バイアス配線23とは同一層にパターニングされている。
2 パッド部
11、21 パッド
13、23 第1バイアス配線
15、25 第2バイアス配線
17、27 最下層のバイアス配線
Claims (5)
- 半導体装置の中央部分に配列された複数のパッドを有するパッドアレイと、
複数の前記パッドと同一層に形成され、前記パッドアレイの両側に配列されて所定量の信号のための信号経路として利用される複数の第1バイアス配線と、
前記第1バイアス配線及び前記パッドの下位層において、隣接する前記パッドの間を通り、前記第1バイアス配線と直交する方向に延伸し、所定量の信号のための信号経路として利用される複数の第2バイアス配線とを備え、
前記第2バイアス配線が、前記第1バイアス配線と直交する方向に延伸し、前記パッドアレイの前記パッドの間を通る配線、及び、前記パッドの間で2つに分割され、前記パッドアレイの方向に折れ曲がり、複数の前記パッドの下を通って前記第1バイアス配線と平行な方向に延伸する形状を有する配線で構成されていることを特徴とする半導体装置におけるパッド部の配線構造。 - 複数の前記パッドが、ボンディングパッド及びプローブパッドを含むことを特徴とする請求項1記載の半導体装置におけるパッド部の配線構造。
- 複数の前記第1バイアス配線が、VDD、VSS、VDDQ、VSSQ、VDDL、VSSL及びVREFを備えることを特徴とする請求項1記載の半導体装置におけるパッド部の配線構造。
- 前記第1バイアス配線及び前記第2バイアス配線に、同一量の信号が送出されることを特徴とする請求項1記載の半導体装置におけるパッド部の配線構造。
- 前記第2バイアス配線の下位層に、前記第2バイアス配線と電気的に接続されるバイアスラインを更に備えることを特徴とする請求項1記載の半導体装置におけるパッド部の配線構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040057679A KR100548582B1 (ko) | 2004-07-23 | 2004-07-23 | 반도체소자의 패드부 |
KR10-2004-0057679 | 2004-07-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041480A JP2006041480A (ja) | 2006-02-09 |
JP4921724B2 true JP4921724B2 (ja) | 2012-04-25 |
Family
ID=35656290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005140499A Expired - Fee Related JP4921724B2 (ja) | 2004-07-23 | 2005-05-13 | 半導体装置におけるパッド部の配線構造 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7227269B2 (ja) |
JP (1) | JP4921724B2 (ja) |
KR (1) | KR100548582B1 (ja) |
CN (1) | CN100397633C (ja) |
TW (1) | TWI289919B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100895353B1 (ko) * | 2007-10-12 | 2009-04-29 | 스테코 주식회사 | 반도체 패키지 |
KR101053666B1 (ko) | 2009-07-31 | 2011-08-02 | 주식회사 하이닉스반도체 | 반도체 장치의 레이아웃 구조 |
JP5656611B2 (ja) * | 2010-12-20 | 2015-01-21 | キヤノン株式会社 | 半導体装置及び固体撮像装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6248043A (ja) * | 1985-08-27 | 1987-03-02 | Nec Corp | 半導体集積回路 |
JPH06120427A (ja) * | 1992-10-05 | 1994-04-28 | Toshiba Corp | パッド周辺回路 |
JPH07106522A (ja) * | 1993-09-30 | 1995-04-21 | Hitachi Ltd | 半導体集積回路 |
JP3328542B2 (ja) * | 1997-03-19 | 2002-09-24 | 富士通株式会社 | 高周波半導体集積回路装置 |
US6064116A (en) * | 1997-06-06 | 2000-05-16 | Micron Technology, Inc. | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
JP2002050179A (ja) * | 2000-08-01 | 2002-02-15 | Fujitsu Ltd | 半導体記憶装置 |
TWI252582B (en) * | 2001-02-27 | 2006-04-01 | Sanyo Electric Co | Switch circuit device |
JP2004055080A (ja) * | 2002-07-23 | 2004-02-19 | Renesas Technology Corp | 半導体メモリモジュールおよびそれに用いる半導体チップの製造方法 |
JP2005012209A (ja) * | 2003-06-17 | 2005-01-13 | Samsung Electronics Co Ltd | 半導体装置の信号バスラインレイアウト構造及びその方法 |
-
2004
- 2004-07-23 KR KR1020040057679A patent/KR100548582B1/ko active IP Right Grant
-
2005
- 2005-05-13 TW TW094115695A patent/TWI289919B/zh not_active IP Right Cessation
- 2005-05-13 JP JP2005140499A patent/JP4921724B2/ja not_active Expired - Fee Related
- 2005-05-16 US US11/131,099 patent/US7227269B2/en active Active
- 2005-06-20 CN CNB2005100783820A patent/CN100397633C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1725482A (zh) | 2006-01-25 |
TW200605301A (en) | 2006-02-01 |
JP2006041480A (ja) | 2006-02-09 |
KR100548582B1 (ko) | 2006-02-02 |
CN100397633C (zh) | 2008-06-25 |
US7227269B2 (en) | 2007-06-05 |
US20060017178A1 (en) | 2006-01-26 |
TWI289919B (en) | 2007-11-11 |
KR20060008026A (ko) | 2006-01-26 |
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