TWI437675B - 積體電路晶片封裝及實體層介面排列 - Google Patents
積體電路晶片封裝及實體層介面排列 Download PDFInfo
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Description
本發明是有關於一種適用於積體電路晶片的實體層介面排列。
積體電路晶片(IC chip)通常包括一基底(例如:矽晶圓)及配置在基底之一主動面(active surface)上的積體電路層(IC layer),在此「主動面」係指在基底上配置積體電路層的那一面。一般來說,積體電路層由多個內部元件(例如:MOS電晶體、電感、電容等)、多層介電層以及多層圖案化金屬層等構成。多層介電層以及多層圖案化金屬層係相互堆疊,且圖案化金屬層會將內部元件的訊號傳遞至外界、或是由外界傳遞至內部。無論積體電路晶片的內部元件、多層圖案化金屬層如何配置,若要將訊號傳遞至外界(或傳遞至內部),皆須透過積體電路層的最外層來達成。以積體電路層的最外層的這個平面來看,其包括一核心區(core area)與圍繞著核心區的一訊號區(signal area),其中核心區係提供核心電源(core power)與核心接地(core ground),而訊號區係提供訊號。此外,訊號區更包括多個實體層介面(physical layer interface),這些實體層介面單排地(in single row)排列於核心區周圍,並分別提供不同功能的訊號傳輸,即每個實體層介面係做為內部元件與外部元件電連接的橋樑,並且提供特定功能的訊號傳輸。在某些情況下,多個實體層介面係共同提供某一特定功能的訊號傳輸。
對於採用覆晶封裝(flip chip package)技術的積體電路晶片,積體電路層的最外層之每個實體層介面包括多個凸塊墊,這些凸塊墊依設計規則(design rule)而排列。此外,每個實體層介面更包括多個內部墊及多條重佈線(redistribution line),這些內部墊及重佈線係位於對應的凸塊墊下方,且位於積體電路層中。這些內部墊單排地(in single row)排列,而這些重佈線將這些凸塊墊分別電性連接至這些對應的內部墊。
當單一的積體電路晶片提供的功能越來越多,係表示需要更多的凸塊墊以作為訊號的輸出或輸入之用。此外,當製程技術越來越進步,係表示晶片的內部元件、圖案化金屬層的尺寸可以進一步縮小,即表示整個積體電路層的面積可以縮小。因此,在晶片上設計上需有所改進,以符合時勢所趨。
本發明提供一種積體電路封裝,其可提升電性效能。
本發明提供一種實體層介面排列,其可提升電性效能。
本發明提出一種積體電路封裝,包括一積體電路晶片、一封裝載板及多個將積體電路晶片連接至封裝載板的導電凸塊。積體電路晶片包括一基底及一配置在基底的一主動面上的積體電路層。主動面具有一核心區及一圍繞著核心區的訊號區。積體電路層包括一第一實體層介面。第一實體層介面包括多個第一凸塊墊及多個分別電性連接至這些第一凸塊墊的內部墊。這些第一內部墊多排地排列於訊號區。
本發明更提出一種實體層介面排列,其包括上述的第一實體層介面。
基於上述,本發明藉由將內部墊多排地排列於訊號區以縮短電流路徑,這有助於提升電性效能。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例的一種積體電路晶片的局部剖面圖,而圖2為圖1之部分2的細部放大圖。請參考圖1及圖2,在本實施例中,積體電路晶片100包括一基底110及一積體電路層120,其中基底110例如是矽晶圓,其具有一主動面112,而積體電路層120配置在主動面112上。積體電路層120由多個內部元件(例如:MOS電晶體、電感、電容等)、多層介電層以及多層圖案化金屬層等構成,在圖1中並未繪示這些構件,而僅以標號120表示此積體電路層。靠近外部的積體電路層120具有多個凸塊墊122(僅繪示其二)、多個內部墊124(僅繪示其二)及多條重佈線126(僅繪示其二)。這些凸塊墊122係位於積體電路層120的最外層,用以安裝一個導電凸塊B,並分別經由這些重佈線126而電性連接至這些內部墊124。
圖3繪示圖1之積體電路晶片的上視示意圖,即繪示積體電路層120的最外層。請參考圖1及圖3,主動面112包括一核心區112a與一圍繞著核心區112a的訊號區112b,其中積體電路層120包括多個核心電源凸塊墊(未繪示)與核心接地凸塊墊(未繪示)於核心區112a,用以提供電源或接地傳輸,而積體電路層120包括多個實體層介面PHY於訊號區112b,用以提供特定功能的訊號傳輸,而數個實體層介面PHY可組成一實體層介面排列。在一實施例中,不同的實體層介面PHY可提供不同功能的訊號傳輸。在另一實施例中,多個實體層介面PHY可共同提供某一特定功能的訊號傳輸。值得一提的是,每一實體層介面PHY包括多個凸塊墊122,其包括訊號凸塊墊、電源凸塊墊及接地凸塊墊。然而,不同於核心區的核心電源凸塊墊及核心接地凸塊墊,此處的電源凸塊墊及接地凸塊墊僅供對應的實體層介面PHY所使用。
更進一步來說,每個實體層介面PHY的局部剖面圖係類似圖2所繪示,其包括多個凸塊墊122(圖2僅繪示其二)。此外,每個實體層介面PHY更包括多個內部墊124(圖2僅繪示其二)及多條重佈線126(圖2僅繪示其二),內部墊124及重佈線126係位於對應的凸塊墊122下方,且位於如圖1所繪示的積體電路層120中。
圖4繪示圖3之部分4的四個實體層介面PHY的凸塊墊,且實體層介面PHY中的凸塊墊排列僅為示意,並非用以限定這些凸塊墊的排列。請參考圖3及圖4,積體電路層120包括一第一實體層介面PHY-1及一第二實體層介面PHY-2,其中第一實體層介面PHY-1及第二實體層介面PHY-2雙排地排列於圖3的核心區112a外圍而位於訊號區112b內。此外,第二實體層介面PHY-2為第一實體層介面PHY-1的垂直鏡像,此處之「垂直」係指第二實體層介面PHY-2與第一實體層介面PHY-1位於不同排,即在X1方向上,二者相對於核心區112a的距離不同。具體而言,第一實體層介面PHY-1包括多個第一凸塊墊122-1。第二實體層介面PHY-2包括多個第二凸塊墊122-2。這些第二凸塊墊122-2為這些第一凸塊墊122-1相對於一垂直於圖1的主動面112的第一幾何平面P1的鏡像。詳言之,這些第一凸塊墊122-1可能是訊號、電源、接地凸塊墊,而在第二實體層介面PHY-2中,會有以第一幾何平面P1呈鏡像排列之訊號、電源、接地凸塊墊。
在本實施例中,積體電路層120更可包括一第三實體層介面PHY-3及一第四實體層介面PHY-4,其中第一實體層介面PHY-1與第三實體層介面PHY-3排成同一排而位於圖3的核心區112a外圍而位於訊號區112b內;同樣地,第二實體層介面PHY-2與第四實體層介面PHY-4排成同一排而位於圖3的核心區112a外圍而位於訊號區112b內。換言之,第一實體層介面PHY-1、第二實體層介面PHY-2、第三實體層介面PHY-3及第四實體層介面PHY-4雙排地排列於核心區112a外圍而位於訊號區112b內。第三實體層介面PHY-3及第四實體層介面PHY-4分別為第一實體層介面PHY-1及第二實體層介面PHY-2的水平鏡像,此處之「水平」係指第三實體層介面PHY-3與第一實體層介面PHY-1位於同一排,或第四實體層介面PHY-4與第二實體層介面PHY-2位於同一排,即在X1方向上,同一排的實體層介面PHY相對於核心區112a的距離相同。
具體而言,第三實體層介面PHY-3包括多個第三凸塊墊122-3,而這些第三凸塊墊122-3為這些第一凸塊墊122-1相對於一垂直於圖1的主動面112的第二幾何平面P2的鏡像。第四實體層介面PHY-4包括多個第四凸塊墊122-4,而這些第四凸塊墊122-4為這些第二凸塊墊122-2相對於一垂直於圖1的主動面112的第二幾何平面P2的鏡像。在本實施例中,第一幾何平面P1與第二幾何平面P2係彼此垂直。
值得注意的是,上述所指的雙排係相較於圖3之實體層介面101、103、105沿著X1方向以單排方式排列而言。更進一步來說,在本實施例中,實體層介面PHY-1與PHY-3沿著X2方向單排排列;同樣地,實體層介面PHY-2與PHY-4亦沿著X2方向單排排列。但整體來說,實體層介面PHY-1、PHY-2、PHY-3與PHY-4係在X1方向呈現雙排排列。在以往的電路設計中,這些實體層介面PHY都是以單排的方式排列,如此導致整體的晶片尺寸無法縮小。然而,隨著製程的演進,製程的線距與線寬皆進一步縮小,故核心區112a所佔的面積可以縮小,訊號區112b的可用面積變大,故實體層介面PHY可以雙排的方式排列。
另外,上述的這些實體層介面PHY-1~4相對於幾何平面P1(及P2)以鏡像排列係適用於這些實體層介面PHY用於共同提供某一特定功能的訊號傳輸,例如:多個實體層介面PHY共同提供雙倍資料速率(DDR;Double Data Rate)記憶體、通用序列匯流排(USB;Universal Serial Bus)或序列先進技術附件(SATA;Serial Advanced Technology Attachment)等之訊號傳遞。更進一步來說,在以往的設計中,會將共同提供某一特定功能的這些實體層介面PHY以單排的方式(如圖3之實體層介面101、103、105的排列)排列在一起,且彼此並沒有鏡像對稱關係。如此在訊號傳輸上,可能導致不同位置的實體層介面PHY雖共同提供某一特定功能,但其傳輸路徑長度不盡相同,而影響傳輸品質,甚至造成訊號錯誤傳遞。因此,在本案中,若一特定功能需由多個實體層介面共同提供,則可如本實施例以雙排方式排列;反之,若一特定功能,僅需由一個實體層介面提供則可如實體層介面101、103、105以單排方式排列。除此之外,上述之實體層介面PHY的雙排排列,並不以4個實體層介面PHY作為一個單位為限。在一實施例中,也可以6個實體層介面PHY以垂直或水平鏡像做排列。
圖5繪示圖4之這些實體層介面的內部墊及重佈線,而單一的實體層介面及其內部墊及重佈線剖面圖係如圖2所示。請參考圖5,在本實施例中,第一實體層介面PHY-1更包括多個第一內部墊124-1,而這些第一內部墊124-1多排地排列於訊號區112b。這些第一內部墊124-1例如是排列成三排R1、R2及R3,其中排R1及排R2相鄰,而排R2與排R3相隔一段距離。在本實施例中,這些第一內部墊124-1的形狀可為矩形,特別是長方形。第二實體層介面PHY-2更包括多個第二內部墊124-2,而這些第二內部墊124-2多排地排列於訊號區112b。這些第二內部墊124-2例如是排列成三排R4、R5及R6,其中排R4及排R5相鄰,而排R5與排R6相隔一段距離。在本實施例中,這些第二內部墊124-2的形狀可為矩形,特別是長方形。這些第二內部墊124-2為這些第一內部墊124-1相對於第一幾何平面P1的鏡像。
在本實施例中,第一實體層介面PHY-1更可包括多個第一重佈線126-1,而這些第一重佈線126-1分別將這些第一凸塊墊122-1電性連接至這些第一內部墊124-1。第二實體層介面PHY-2更可包括多個第二重佈線126-2,而這些第二重佈線126-2分別將這些第二凸塊墊122-2電性連接至這些第二內部墊124-2。這些第二重佈線126-2為這些第一重佈線126-1相對於第一幾何平面P1的鏡像。
值得注意的是,在以往實體層介面的設計中,僅會在靠近實體層介面的邊緣配置內部墊,例如:排R1的位置。然而,如此的設計會導致靠近第一幾何平面P1的凸塊墊需透過較長的重佈線才可與內部墊電性連接,而影響訊號傳遞品質。對於單一的實體層介面而言,本案藉由多排的內部墊,可以縮短重佈線的長度,以確保訊號傳遞品質。
在本實施例中,第三實體層介面PHY-3更包括多個第三內部墊124-3,這些第三內部墊124-3為這些第一內部墊124-1相對於第二幾何平面P2的鏡像。同樣地,第三內部墊124-3多排地排列於訊號區112b。此外,第四實體層介面PHY-4更包括多個第四內部墊124-4,這些第四內部墊124-4為這些第二內部墊124-2相對於第二幾何平面P2的鏡像。同樣地,第四內部墊124-4多排地排列於訊號區112b。
在本實施例中,第三實體層介面PHY-3更可包括多個第三重佈線126-3,這些第三重佈線126-3分別將這些第三凸塊墊122-3電性連接至這些第三內部墊124-3,這些第三重佈線126-3為這些第一重佈線126-1相對於第二幾何平面P2的鏡像。此外,第四實體層介面PHY-4更可包括多個第四重佈線126-4,這些第四重佈線126-4分別將這些第四凸塊墊122-4電性連接至這些第四內部墊124-4,這些第四重佈線126-4為這些第二重佈線126-2相對於第二幾何平面P2的鏡像。
值得注意的是,在本實施例中,上述的這些內部墊可能是用於訊號及電源的傳輸,故訊號凸塊墊及電源凸塊墊係利用對應的重佈線與對應的內部墊作電性上及物理上的連接。
在本實施例中,積體電路層120更可包括多個電源環128-1,其實體結構如同圖2的電源環128。電源環128-1位於同一排(R1、R2或R3)的這些第一內部墊124-1下方,以提供電壓至第一實體層介面PHY-1。電源環128-1更位於同一排(R1、R2或R3)的這些第三內部墊124-3下方,以提供電壓至第三實體層介面PHY-3。此外,積體電路層120更可包括多個電源環128-2,其實體結構亦如同圖2的電源環128。電源環128-2位於同一排(R4、R5或R6)的這些第二內部墊124-2,以提供電壓至第二實體層介面PHY-2。電源環128-2更位於同一排(R4、R5或R6)的這些第四內部墊124-4,以提供電壓至第四實體層介面PHY-4。特別是,此處之這些電源環128-1與128-2同樣亦相對於第二幾何平面P2而呈鏡像排列,如此一來,若第二實體層介面PHY-2或第四實體層介面PHY-4需要電壓時,可以直接由第二實體層介面PHY-2或第四實體層介面PHY-4中對應的電源環128-2取得,而不再由電路徑較長的第一實體層介面PHY-1或第三實體層介面PHY-3中的電源環128-1提供,以維持良好的電性品質。而且,單一實體層介面中之多排的電源環,更可進一步縮短傳輸路徑。
值得一提是,在以往的設計中,每一個實體層介面PHY中的凸塊墊分佈是屬於「窄型」的分佈;而在本案中,每一個實體層介面PHY中的凸塊墊分佈是屬於「寬型」的分佈。更進一步來說,以圖3的標記「PHY」的實體層介面為例,假設這個實體層介面PHY有24個凸塊墊,在以往的設計中,會在X1方向上配置8個,X2方向上配置3個,甚至在X1方向上配置12個,X2方向上配置2個,以縮小實體層介面PHY的尺寸,進一步縮小晶片的面積。反觀本案,由於部分的實體層介面採取雙排排列,訊號區112b的可用面積變大,故可在X1方向上配置6個,X2方向上配置4個。如此一來,當凸塊墊利用重佈線與對應的內部墊連接時,最靠近核心區112a的凸塊墊,其對應的重佈線長度(即實體層介面PHY中最長的重佈線長度)可以縮短,如此可以縮短傳遞的路徑,避免訊號衰減。除此之外,本案之實體層介面中更配置多排的內部墊,因此可更進一步縮短重佈線的長度。
在本實施例中,這些第一凸塊墊122-1包括多個訊號凸塊墊、多個電源凸塊墊及多個接地凸塊墊,而這些訊號凸塊墊的數量與這些電源凸塊墊的數量的比值介於2至8。因為在結構及電性上的鏡射,這些第二凸塊墊122-2、這些第三凸塊墊122-3或這些第四凸塊墊122-4所具有的這些訊號凸塊墊的數量與這些電源凸塊墊的數量的比值亦介於2至8。
請再參考圖3及圖5,在上述的實施例中,雖然是以4個實體層介面PHY進行描述,但不限定於此。以圖3之單排的實體層介面101、103或105為例,單一的實體層介面101、103或105亦可採用如圖5之實體層介面PHY-1、PHY-2、PHY-3或PHY-4的設計。換言之,於單一的實體層介面101、103或105中,亦可包括多排的內部墊排列於訊號區112b中,或是包括對應的多個電源環。如此一來,對於單排的實體層介面亦可有效地縮短訊號傳輸路徑,以維持訊號品質。
圖6繪示本發明之另一實施例的內部接墊的排列。請參考圖6,不同於圖5的第一實體層介面PHY-1的這些第一內部墊124-1的長度方向均垂直於這些排R1、R2及R3的延伸方向,在圖6的第一實體層介面PHY-1中,位於同一排R1的這些第一內部墊124-1的長度方向垂直於排R1的延伸方向,但是位於同一排R2的這些第一內部墊124-1的長度方向平行於排R2的延伸方向。
圖7為本發明之另一實施例的一種積體電路封裝的側視圖。請參考圖7,在本實施例中,積體電路封裝200包括一積體電路晶片202、一封裝載板204及多個導電凸塊206。積體電路晶片202相同於圖1所示的積體電路晶片100,並經由這些導電凸塊206來連接於封裝載板204。在本實施例中,封裝載板204可為一無核心線路板(coreless wired board)。所謂的無核心線路板是一種採用不含玻纖的樹脂作為其介電層的線路板,這有助於降低導電通孔(conductive through via)的尺寸以提高線路板的佈線密度。如此一來,本發明之具有雙排排列的實體層介面PHY可搭配上述之無核心線路板進行晶片封裝製程。
綜上所述,本發明藉由將內部墊多排地排列於訊號區以縮短電流路徑,這有助於提升電性效能。再者,本發明藉由垂直鏡射及水平鏡射將一實體層介面複製於其旁側而形成一實體層介面排列,這亦有助於提升電性效能。此外,本發明藉由將這些實體層介面雙排地排列於主動面的訊號區,這有助於縮短訊號傳輸路徑及縮小晶片尺寸。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...積體電路晶片
101、103、105...實體層介面
110...基底
112...主動面
112a...核心區
112b...訊號區
120...積體電路層
122、122-1、122-2、122-3、122-4...凸塊墊
124、124-1、124-2、124-3、124-4...內部墊
126、126-1、126-2、126-3、126-4...重佈線
128、128-1、128-2...電源環
P1、P2...幾何平面
PHY、PHY-1、PHY-2、PHY-3、PHY-4...實體層介面
R1、R2、R3、R4、R5、R6...排
圖1為本發明之一實施例的一種積體電路晶片的局部剖面圖。
圖2為圖1之部分2的細部放大圖。
圖3繪示圖1之積體電路晶片的多個實體層介面。
圖4繪示圖3之部分4的四個實體層介面的凸塊墊。
圖5繪示圖4之這些實體層介面的內部墊及重佈線。
圖6繪示本發明之另一實施例的內部接墊的排列。
圖7為本發明之另一實施例的一種積體電路封裝的側視圖。
112a...核心區
112b...訊號區
122-1、122-2、122-3、122-4...凸塊墊
124-1、124-2、124-3、124-4...內部墊
126-1、126-2、126-3、126-4...重佈線
128-1、128-2...電源環
P1、P2...幾何平面
PHY-1、PHY-2、PHY-3、PHY-4...實體層介面
Claims (18)
- 一種積體電路封裝,包括:一積體電路晶片;一封裝載板;以及多個導電凸塊,該積體電路晶片經由該些導電凸塊連接於該封裝載板,其中該積體電路晶片包括:一基底,具有一主動面,該主動面具有一核心區及一圍繞著該核心區的訊號區;以及一積體電路層,配置在該主動面上,並包括:一第一實體層介面,包括:多個第一凸塊墊;以及多個第一內部墊,分別電性連接至該些第一凸塊墊,其中該些第一內部墊多排地排列於該訊號區。
- 如申請專利範圍第1項所述的積體電路封裝,其中排成一排的該些第一內部墊的長度方向垂直於該排的延伸方向,而排成另一排的該些第一內部墊的長度方向平行於該另一排的延伸方向。
- 如申請專利範圍第1項所述的積體電路封裝,其中該積體電路層更包括多個電源環,且排成一排之該些第一內部墊下方對應配置該些電源環之其中之一。
- 如申請專利範圍第1項所述的積體電路封裝,其中該積體電路層更包括:一第二實體層介面,包括:多個第二凸塊墊;以及多個第二內部墊,多排地排列於該訊號區且分別電性連接至該些第一凸塊墊,其中該些第二凸塊墊為該些第一凸塊墊相對於垂直於該主動面的一第一幾何平面的鏡像,而該些第二內部墊為該些第一內部墊相對於該第一幾何平面的鏡像。
- 如申請專利範圍第4項所述的積體電路封裝,其中該積體電路層更包括多個第一電源環與多個第二電源環,排成一排之該些第一內部墊下方對應配置該些第一電源環之其中之一,排成一排之該些第二內部墊下方對應配置該些第二電源環之其中之一,且該些第二電源環為該些第一電源環相對於垂直於該主動面的該第一幾何平面的鏡像。
- 如申請專利範圍第4項所述的積體電路封裝,其中該積體電路層更包括:一第三實體層介面,包括:多個第三凸塊墊;以及多個第三內部墊,多排地排列於該訊號區且分別電性連接至該些第三凸塊墊;以及一第四實體層介面,包括:多個第四凸塊墊;以及多個第四內部墊,多排地排列於該訊號區且分別電性連接至該些第四凸塊墊,其中該些第三凸塊墊為該些第一凸塊墊相對於垂直於該主動面及該第一幾何平面的一第二幾何平面的鏡像,該些第三內部墊為該些第一內部墊相對於該第二幾何平面的鏡像,並且該些第四凸塊墊為該些第二凸塊墊相對於該第二幾何平面的鏡像,且該些第四內部墊為該些第二內部墊相對於該第二幾何平面的鏡像。
- 如申請專利範圍第6項所述的積體電路封裝,其中該積體電路層更包括多個第一電源環與多個第二電源環,排成一排之該些第一內部墊與該些第三內部墊的下方對應配置該些第一電源環之其中之一,排成一排之該些第二內部墊與該些第四內部墊的下方對應配置該些第二電源環之其中之一,且該些第二電源環為該些第一電源環相對於垂直於該主動面的該第一幾何平面的鏡像。
- 如申請專利範圍第1項所述的積體電路封裝,其中該些第一凸塊墊包括多個訊號凸塊墊、多個電源凸塊墊及多個接地凸塊墊。
- 如申請專利範圍第1項所述的積體電路晶片,其中該些第一凸塊墊包括多個訊號凸塊墊及多個電源凸塊墊,該些訊號凸塊墊的數量與該些電源凸塊墊的數量的比值介於2至8。
- 一種實體層介面排列,適於配置在一積體電路晶片的一基底的一主動面的上方,該主動面具有一核心區及一圍繞著該核心區的訊號區,該實體層介面排列包括:一第一實體層介面,包括:多個第一凸塊墊;以及多個第一內部墊,分別電性連接至該些第一凸塊墊,其中該些第一內部墊多排地排列於該訊號區。
- 如申請專利範圍第10項所述的實體層介面排列,其中排成一排的該些第一內部墊的長度方向垂直於該排的延伸方向,而排成另一排的該些第一內部墊的長度方向平行於該另一排的延伸方向。
- 如申請專利範圍第10項所述的實體層介面排列,更包括多個電源環,其中排成一排之該些第一內部墊下方對應配置該些電源環之其中之一。
- 如申請專利範圍第10項所述的實體層介面排列,其中該實體層介面排列更包括:一第二實體層介面,包括:多個第二凸塊墊;以及多個第二內部墊,多排地排列於該訊號區且分別電性連接至該些第一凸塊墊,其中該些第二凸塊墊為該些第一凸塊墊相對於垂直於該主動面的一第一幾何平面的鏡像,而該些第二內部墊為該些第一內部墊相對於該第一幾何平面的鏡像。
- 如申請專利範圍第13項所述的實體層介面排列,更包括多個第一電源環與多個第二電源環,其中排成一排之該些第一內部墊下方對應配置該些第一電源環之其中之一,排成一排之該些第二內部墊下方對應配置該些第二電源環之其中之一,且該些第二電源環為該些第一電源環相對於垂直於該主動面的該第一幾何平面的鏡像。
- 如申請專利範圍第13項所述的實體層介面排列,更包括:一第三實體層介面,包括:多個第三凸塊墊;以及多個第三內部墊,多排地排列於該訊號區且分別電性連接至該些第三凸塊墊;以及一第四實體層介面,包括:多個第四凸塊墊;以及多個第四內部墊,多排地排列於該訊號區且分別電性連接至該些第四凸塊墊,其中該些第三凸塊墊為該些第一凸塊墊相對於垂直於該主動面及該第一幾何平面的一第二幾何平面的鏡像,該些第三內部墊為該些第一內部墊相對於該第二幾何平面的鏡像,並且該些第四凸塊墊為該些第二凸塊墊相對於該第二幾何平面的鏡像,且該些第四內部墊為該些第二內部墊相對於該第二幾何平面的鏡像。
- 如申請專利範圍第15項所述的實體層介面排列,更包括多個第一電源環與多個第二電源環,其中排成一排之該些第一內部墊與該些第三內部墊的下方對應配置該些第一電源環之其中之一,排成一排之該些第二內部墊與該些第四內部墊的下方對應配置該些第二電源環之其中之一,且該些第二電源環為該些第一電源環相對於垂直於該主動面的該第一幾何平面的鏡像。
- 如申請專利範圍第10項所述的實體層介面排列,其中該些第一凸塊墊包括多個訊號凸塊墊、多個電源凸塊墊及多個接地凸塊墊。
- 如申請專利範圍第10項所述的實體層介面排列,其中該些第一凸塊墊包括多個訊號凸塊墊及多個電源凸塊墊,該些訊號凸塊墊的數量與該些電源凸塊墊的數量的比值介於2至8。
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