KR980005659A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

Info

Publication number
KR980005659A
KR980005659A KR1019970023983A KR19970023983A KR980005659A KR 980005659 A KR980005659 A KR 980005659A KR 1019970023983 A KR1019970023983 A KR 1019970023983A KR 19970023983 A KR19970023983 A KR 19970023983A KR 980005659 A KR980005659 A KR 980005659A
Authority
KR
South Korea
Prior art keywords
input
semiconductor substrate
output terminal
terminal portion
metal
Prior art date
Application number
KR1019970023983A
Other languages
English (en)
Other versions
KR100290193B1 (ko
Inventor
아키토 요시다
Original Assignee
니시무로 타이조
가부시기가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 니시무로 타이조, 가부시기가이샤 도시바 filed Critical 니시무로 타이조
Publication of KR980005659A publication Critical patent/KR980005659A/ko
Application granted granted Critical
Publication of KR100290193B1 publication Critical patent/KR100290193B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02377Fan-in arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49004Electrical device making including measuring or testing of device or component part

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 장치에 형성되는 입·출력 단자가 다이소트 단자부(101)와 범프를 갖는 입·출력 단자부(102)로 이루어져 종래의 프로브 카드를 이용하여도 다이소트를 용이하게 행하 수 있는 반도체 장치 및 그 제조 방법을 제공한다. 반도체 기판(1)에는 입·출력 단자 및 입·출력 회로가 형성되어 있다. 반도체 기판(1)의 주면은 집적 회로가 형성되어 있는내부 영역부(1a)와 입·출력 회로(11)가 형성되어 있는 주변 영역(1b)으로 나누어진다. 임·출력 회로(11)는 양 영역의 경계에 배치되어 있다. 입·출력 단자는 주변 영역(1b)에 배치되고, 범프가 형성되지 않은 테스트용의 다이소트 단자부(101)와 내부 영역 (1a)에 배치되며, 범프가 형성된 접속용 입·출력 단자부(102)로 구성되어 있다. 다이소트 단자부 (101)와 입·출력 단자부(102)는 예컨대, 양 단자부를 구성하는 금속 배선으로로부터 하층의 접속 배선 (103)에 의해 적기적으로 접속되어 있다.

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 제1 실시예의 반도체 장치의 평면도.

Claims (10)

  1. 반도체 기판과,
    상기 반도체 기판상에 형성된 복수의 입·출력 단자를 구비하고, 상기 입·출력 단자는, 상기 반도체 기판상의 주변 영역에 설치된 다이소트 단자부와 상기 반도체 기판상의 내부 영역에 설치되고, 범프가 형성되어 있는 입·출력 단자부를 가지며, 이 다이소트 단자부와 입·출력 단자부는 전기적으로 접속되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제 1 항에 있어서, 상기 반도체 기판의 상기 주변 영역에는 상기 반도체 기판의 변을 따라 입·출력 회로부가 형성되어 있고, 상기 다이소트 단자부는 이 입·출력 회로부와 상기 반도체 기판의 변과의 사이에 형성되어 있는 것을 특징으로 하는 반도체 장치.
  3. 제 1 항에 있어서, 상기 입·출력 단자부는 상기 반도체 기판상의 내부 영역에 있어서 등간격으로 배열되어 있는 것을 특징으로 하는 반도체 장치.
  4. 제 3 항에 있어서, 상기 입·출력 단자부는 거의 정방형이고, 그 대향하는 2변에 평행한 중심선은 상기 반도체 기판의 임의의 변에 대하여 45° 기울어 있는 것을 특징으로 하는 반도체 장치.
  5. 제 1 항에 있어서, 상기 반도체 기판상에는 금속 배선으로 구성된 다층 배선이 형성되어 있고 이 다층 배선의 상기 입·출력 단자부와 상기 다이소트 단자부를 전기적으로 접속하는 배선에는 이 다층 배선의 소정 층의 배선을 이용하고, 상기 입·출력 단자부 및 상기 다이소트 단자부에는 이 소정 층의 배선으로부터 상층의 배선을 이용하는 것을 특징으로 하는 반도체 장치.
  6. 제 1 항에 있어서, 다이소트 단자부가 입·출력 단자부만으로 이루어지는 입·출력 단자를 추가로 갖는 것을 특징으로 하는 반도체 장치.
  7. 제 1 항에 있어서, 상기 다이소트 단자부는 표면에 도전성의 내에칭성 보호막이 피복되어 있는 금속 배선으로 이루어지는 것을 특징으로 하는 반도체 장치.
  8. 제 7 항에 있어서, 상기 내에칭성 보호막은 상기 배리어 메탈을 에칭하는 에칭액에 대하여 이 배리어 메탈보다 내에칭성이 높은 것을 특징으로 하는 반도체 장치.
  9. 반도체 기판상에 금속막을 형성하는 공정과,
    상기 금속막을 패터닝하여 상기 반도체 기판의 내부 영역상에 금속 배선으로 이루어지는 복수의 입·출력 단자부와, 상기 반도체 기판의 주변 영역상에 금속 배선으로 이루어지고, 이 입·출력 단자부와는 전기적으로 접속되어 있는 다이소트 단자부를 형성하는 공정과,
    상기 입·출력 단자부및 상기 다이소트 단자부의 상기 금속 배선상에 도전성의 내에칭 보호막을 형성하는 공정과, 상기 반도체 기판상에 배리어 메탈 형성용 금속막을 형성하는 공정과,
    상기 입·출력 단자부 위에 상기 내에칭 보호막 및 상기 배리어 메탈 형성용 금속막을 통해 범프를 형성하는 공정과,
    상기 배리어 메탈 형서용 금속막을 패터닝하여, 상기 입·출력 단자부의 상기 범프와 상기 내에칭 보호막과의 사이에 배리어 메탈을 형성하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조방법.
  10. 반도체 기판상에 금속막을 형성하는 공정과, 상기 금속막상에 도전성의 내에칭 보호막을 형성하는 공정과, 상기 금속막 및 상기 내에칭 보호막을 패터닝하여 상기 반도체 기판의 내부 영역상에 상기 내에칭 보호막으로 피복된 금속 배선으로 이루어지는 복수의 입·출력 단자부와, 상기 반도체 기판의 주변 영역상에 상기 내에칭 보호막으로 피복된 금속 배선으로 이루어지며, 이 입·출력 단자부와는 전기적으로 접속되어 있는 다이소트 단자부를 형성하는 공정과, 상기 반도체 기판상에 배리어 메탈 형성용 금속막을 형성하는 공정과, 상기 입·출력 단자부 위에 상기 내에칭 보호막 및 상기 배리어 메탈 형성용 금속막을 통해 범프를 형성하는 공정과, 상기 배리어 메탈 형성용 금속막을 패터닝하여, 상기 입·출력 단자부의 상기 범프와 상기 내에칭 보호막과의 사이에 배리어 메탈을 형성하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970023983A 1996-06-12 1997-06-11 반도체장치및그제조방법 KR100290193B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP96-171664 1996-06-12
JP8171664A JPH09330934A (ja) 1996-06-12 1996-06-12 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR980005659A true KR980005659A (ko) 1998-03-30
KR100290193B1 KR100290193B1 (ko) 2001-05-15

Family

ID=15927419

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970023983A KR100290193B1 (ko) 1996-06-12 1997-06-11 반도체장치및그제조방법

Country Status (6)

Country Link
US (1) US6445001B2 (ko)
EP (1) EP0813238B1 (ko)
JP (1) JPH09330934A (ko)
KR (1) KR100290193B1 (ko)
DE (1) DE69735318T2 (ko)
TW (1) TW332900B (ko)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3549714B2 (ja) * 1997-09-11 2004-08-04 沖電気工業株式会社 半導体装置
US6456099B1 (en) 1998-12-31 2002-09-24 Formfactor, Inc. Special contact points for accessing internal circuitry of an integrated circuit
US6831294B1 (en) * 1999-01-22 2004-12-14 Renesas Technology Corp. Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes
US6707159B1 (en) 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
JP3480416B2 (ja) * 2000-03-27 2003-12-22 セイコーエプソン株式会社 半導体装置
JP3449333B2 (ja) * 2000-03-27 2003-09-22 セイコーエプソン株式会社 半導体装置の製造方法
JP3829050B2 (ja) * 2000-08-29 2006-10-04 松下電器産業株式会社 一体型電子部品
DE10085331T1 (de) * 2000-10-23 2003-09-11 Mitsubishi Electric Corp Bondhügelbildungsverfahren und Bondhügelbildungsvorrichtung
US6833620B1 (en) * 2000-11-28 2004-12-21 Ati Technologies, Inc. Apparatus having reduced input output area and method thereof
JP3526548B2 (ja) * 2000-11-29 2004-05-17 松下電器産業株式会社 半導体装置及びその製造方法
JP4824228B2 (ja) * 2001-09-07 2011-11-30 株式会社リコー 半導体装置
US6715663B2 (en) * 2002-01-16 2004-04-06 Intel Corporation Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method
DE10234648A1 (de) * 2002-07-29 2004-02-12 Infineon Technologies Ag Halbleiterwafer mit elektrisch verbundenen Kontakt- und Prüfflächen
US6861749B2 (en) * 2002-09-20 2005-03-01 Himax Technologies, Inc. Semiconductor device with bump electrodes
DE10255378B4 (de) 2002-11-27 2006-03-23 Advanced Micro Devices, Inc., Sunnyvale Teststruktur zum Bestimmen der Stabilität elektronischer Vorrichtungen die miteinander verbundene Substrate umfassen
JP4150604B2 (ja) * 2003-01-29 2008-09-17 日立マクセル株式会社 半導体装置
JP2005136246A (ja) * 2003-10-31 2005-05-26 Renesas Technology Corp 半導体集積回路装置の製造方法
US7132303B2 (en) * 2003-12-18 2006-11-07 Freescale Semiconductor, Inc. Stacked semiconductor device assembly and method for forming
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package
US7808115B2 (en) * 2004-05-03 2010-10-05 Broadcom Corporation Test circuit under pad
JP2006210438A (ja) * 2005-01-25 2006-08-10 Nec Electronics Corp 半導体装置およびその製造方法
KR100699838B1 (ko) * 2005-04-13 2007-03-27 삼성전자주식회사 롬 인터페이스 용 패드를 구비하는 반도체장치
JP4592634B2 (ja) * 2005-06-17 2010-12-01 パナソニック株式会社 半導体装置
CN100346467C (zh) * 2005-07-19 2007-10-31 钰创科技股份有限公司 电路重布线方法及电路结构
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
JP2007115958A (ja) * 2005-10-21 2007-05-10 Seiko Epson Corp 半導体装置
US7462038B2 (en) * 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
JP5114969B2 (ja) * 2007-02-21 2013-01-09 富士通セミコンダクター株式会社 半導体装置、半導体ウエハ構造、及び半導体装置の製造方法
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
US9267985B2 (en) * 2009-07-31 2016-02-23 Altera Corporation Bond and probe pad distribution
US8338287B2 (en) * 2010-03-24 2012-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US9129973B2 (en) 2011-12-07 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit probing structures and methods for probing the same
KR102357937B1 (ko) * 2015-08-26 2022-02-04 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
KR102372349B1 (ko) 2015-08-26 2022-03-11 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
JP6569901B2 (ja) * 2015-08-28 2019-09-04 ラピスセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
KR20190105337A (ko) * 2018-03-05 2019-09-17 삼성전자주식회사 반도체 메모리 장치
KR20210028801A (ko) * 2019-09-04 2021-03-15 삼성전자주식회사 반도체 소자

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5230381A (en) * 1975-09-03 1977-03-08 Hitachi Ltd Semiconductor integrating circuit
US4144493A (en) * 1976-06-30 1979-03-13 International Business Machines Corporation Integrated circuit test structure
US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
US4254445A (en) * 1979-05-07 1981-03-03 International Business Machines Corporation Discretionary fly wire chip interconnection
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
JPS5815251A (ja) * 1981-07-20 1983-01-28 Hitachi Ltd 半導体装置
US4951098A (en) * 1988-12-21 1990-08-21 Eastman Kodak Company Electrode structure for light emitting diode array chip
JPH02184043A (ja) * 1989-01-10 1990-07-18 Nec Corp 半導体装置の製造方法
JPH0382129A (ja) * 1989-08-25 1991-04-08 Agency Of Ind Science & Technol 半導体チップ
JPH0727927B2 (ja) * 1990-03-12 1995-03-29 株式会社東芝 テープキャリア
JP2901156B2 (ja) * 1990-08-31 1999-06-07 三菱電機株式会社 半導体集積回路装置
EP0494782B1 (en) * 1991-01-11 1997-04-23 Texas Instruments Incorporated Wafer burn-in and test system and method of making the same
JPH0563029A (ja) * 1991-09-02 1993-03-12 Fujitsu Ltd 半導体素子
US5249728A (en) * 1993-03-10 1993-10-05 Atmel Corporation Bumpless bonding process having multilayer metallization
KR950004464A (ko) * 1993-07-15 1995-02-18 김광호 칩 범프의 제조방법
US5367763A (en) 1993-09-30 1994-11-29 Atmel Corporation TAB testing of area array interconnected chips
JP2570147B2 (ja) * 1993-11-18 1997-01-08 日本電気株式会社 半導体装置
FR2714528B1 (fr) * 1993-12-27 1996-03-15 Sgs Thomson Microelectronics Structure de test de circuit intégré.
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design
US5973376A (en) * 1994-11-02 1999-10-26 Lsi Logic Corporation Architecture having diamond shaped or parallelogram shaped cells
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
US5517127A (en) 1995-01-09 1996-05-14 International Business Machines Corporation Additive structure and method for testing semiconductor wire bond dies
JPH09139471A (ja) * 1995-09-07 1997-05-27 Hewlett Packard Co <Hp> オンサーキット・アレイ・プロービング用の補助パッド
US5633210A (en) * 1996-04-29 1997-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming damage free patterned layers adjoining the edges of high step height apertures
US5719449A (en) * 1996-09-30 1998-02-17 Lucent Technologies Inc. Flip-chip integrated circuit with improved testability
JP3718360B2 (ja) * 1999-02-09 2005-11-24 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
EP0813238A2 (en) 1997-12-17
DE69735318D1 (de) 2006-04-27
DE69735318T2 (de) 2006-11-02
TW332900B (en) 1998-06-01
EP0813238A3 (en) 1998-11-18
EP0813238B1 (en) 2006-03-01
KR100290193B1 (ko) 2001-05-15
JPH09330934A (ja) 1997-12-22
US6445001B2 (en) 2002-09-03
US20010011771A1 (en) 2001-08-09

Similar Documents

Publication Publication Date Title
KR980005659A (ko) 반도체 장치 및 그 제조방법
KR960035835A (ko) 반도체장치와 그 제조방법
US5477062A (en) Semiconductor wafer
KR950030242A (ko) 반도체장치와 그 제조방법
KR950007059A (ko) 집적 회로
KR970008536A (ko) 반도체 장치 및 그 제조 방법
KR920005304A (ko) 반도체집적회로장치의 배선접속구조 및 그 제조방법
KR970077744A (ko) 박막 트랜지스터 및 그 제조 방법
KR900007085A (ko) 반도체집적회로장치 및 그 제조방법
KR960036009A (ko) 반도체장치 및 그 제조방법
KR920020618A (ko) 반도체 장치의 배선 접속 구조 및 그 제조방법
KR950004532A (ko) 고집적 반도체 배선구조 및 그 제조방법
KR930003260A (ko) 반도체 장치 및 그 제조 방법
KR960042968A (ko) 반도체장치 및 그 제조방법
KR930000614B1 (ko) 반도체 집적회로장치
KR930020590A (ko) 알루미늄을 주성분으로 하는 금속박막의 에칭방법 및 박막트랜지스터의 제조방법
KR910003783A (ko) 반도체장치 및 그 제조방법
US3414784A (en) Electrical structural element having closely neighboring terminal contacts and method of making it
KR970017961A (ko) 반도체 집적회로장치 및 그의 제조방법
KR910005379A (ko) 반도체집적회로장치 및 그 제조방법
US5523625A (en) Semiconductor integrated circuit device having partially constricted lower wiring for preventing upper wirings from short-circuit
JP2778235B2 (ja) 半導体装置
KR950027946A (ko) 반도체 소자의 금속배선 콘택 제조방법
KR970052368A (ko) 티(t)자 형태의 금속 플러그를 갖는 반도체 장치 및 그 제조방법
KR100192578B1 (ko) 비아 저항 체크 패턴 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee