TW332900B - The semiconductor device and producing method - Google Patents
The semiconductor device and producing methodInfo
- Publication number
- TW332900B TW332900B TW086107705A TW86107705A TW332900B TW 332900 B TW332900 B TW 332900B TW 086107705 A TW086107705 A TW 086107705A TW 86107705 A TW86107705 A TW 86107705A TW 332900 B TW332900 B TW 332900B
- Authority
- TW
- Taiwan
- Prior art keywords
- input
- terminal
- semiconductor device
- producing method
- putout
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/05166—Titanium [Ti] as principal constituent
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- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/05666—Titanium [Ti] as principal constituent
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
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- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8171664A JPH09330934A (ja) | 1996-06-12 | 1996-06-12 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW332900B true TW332900B (en) | 1998-06-01 |
Family
ID=15927419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086107705A TW332900B (en) | 1996-06-12 | 1997-06-04 | The semiconductor device and producing method |
Country Status (6)
Country | Link |
---|---|
US (1) | US6445001B2 (zh) |
EP (1) | EP0813238B1 (zh) |
JP (1) | JPH09330934A (zh) |
KR (1) | KR100290193B1 (zh) |
DE (1) | DE69735318T2 (zh) |
TW (1) | TW332900B (zh) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3549714B2 (ja) * | 1997-09-11 | 2004-08-04 | 沖電気工業株式会社 | 半導体装置 |
US6456099B1 (en) | 1998-12-31 | 2002-09-24 | Formfactor, Inc. | Special contact points for accessing internal circuitry of an integrated circuit |
JP3908908B2 (ja) * | 1999-01-22 | 2007-04-25 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6707159B1 (en) | 1999-02-18 | 2004-03-16 | Rohm Co., Ltd. | Semiconductor chip and production process therefor |
JP3480416B2 (ja) * | 2000-03-27 | 2003-12-22 | セイコーエプソン株式会社 | 半導体装置 |
JP3449333B2 (ja) * | 2000-03-27 | 2003-09-22 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP3829050B2 (ja) * | 2000-08-29 | 2006-10-04 | 松下電器産業株式会社 | 一体型電子部品 |
WO2002035602A1 (fr) * | 2000-10-23 | 2002-05-02 | Mitsubishi Denki Kabushiki Kaisha | Procede et dispositif de formation de bosses |
US6833620B1 (en) * | 2000-11-28 | 2004-12-21 | Ati Technologies, Inc. | Apparatus having reduced input output area and method thereof |
JP3526548B2 (ja) * | 2000-11-29 | 2004-05-17 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP4824228B2 (ja) * | 2001-09-07 | 2011-11-30 | 株式会社リコー | 半導体装置 |
US6715663B2 (en) * | 2002-01-16 | 2004-04-06 | Intel Corporation | Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method |
DE10234648A1 (de) * | 2002-07-29 | 2004-02-12 | Infineon Technologies Ag | Halbleiterwafer mit elektrisch verbundenen Kontakt- und Prüfflächen |
US6861749B2 (en) * | 2002-09-20 | 2005-03-01 | Himax Technologies, Inc. | Semiconductor device with bump electrodes |
DE10255378B4 (de) | 2002-11-27 | 2006-03-23 | Advanced Micro Devices, Inc., Sunnyvale | Teststruktur zum Bestimmen der Stabilität elektronischer Vorrichtungen die miteinander verbundene Substrate umfassen |
JP4150604B2 (ja) * | 2003-01-29 | 2008-09-17 | 日立マクセル株式会社 | 半導体装置 |
JP2005136246A (ja) * | 2003-10-31 | 2005-05-26 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
US7132303B2 (en) * | 2003-12-18 | 2006-11-07 | Freescale Semiconductor, Inc. | Stacked semiconductor device assembly and method for forming |
US7259468B2 (en) * | 2004-04-30 | 2007-08-21 | Advanced Chip Engineering Technology Inc. | Structure of package |
US7808115B2 (en) * | 2004-05-03 | 2010-10-05 | Broadcom Corporation | Test circuit under pad |
JP2006210438A (ja) * | 2005-01-25 | 2006-08-10 | Nec Electronics Corp | 半導体装置およびその製造方法 |
KR100699838B1 (ko) * | 2005-04-13 | 2007-03-27 | 삼성전자주식회사 | 롬 인터페이스 용 패드를 구비하는 반도체장치 |
JP4592634B2 (ja) * | 2005-06-17 | 2010-12-01 | パナソニック株式会社 | 半導体装置 |
CN100346467C (zh) * | 2005-07-19 | 2007-10-31 | 钰创科技股份有限公司 | 电路重布线方法及电路结构 |
JP4745007B2 (ja) * | 2005-09-29 | 2011-08-10 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP2007115958A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置 |
US7462038B2 (en) * | 2007-02-20 | 2008-12-09 | Qimonda Ag | Interconnection structure and method of manufacturing the same |
JP5114969B2 (ja) * | 2007-02-21 | 2013-01-09 | 富士通セミコンダクター株式会社 | 半導体装置、半導体ウエハ構造、及び半導体装置の製造方法 |
US7858438B2 (en) * | 2007-06-13 | 2010-12-28 | Himax Technologies Limited | Semiconductor device, chip package and method of fabricating the same |
US9267985B2 (en) * | 2009-07-31 | 2016-02-23 | Altera Corporation | Bond and probe pad distribution |
US8338287B2 (en) * | 2010-03-24 | 2012-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US9129973B2 (en) * | 2011-12-07 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit probing structures and methods for probing the same |
KR102372349B1 (ko) | 2015-08-26 | 2022-03-11 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
KR102357937B1 (ko) * | 2015-08-26 | 2022-02-04 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
JP6569901B2 (ja) * | 2015-08-28 | 2019-09-04 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
KR20190105337A (ko) * | 2018-03-05 | 2019-09-17 | 삼성전자주식회사 | 반도체 메모리 장치 |
US11342221B2 (en) * | 2019-09-04 | 2022-05-24 | Samsung Electronics Co., Ltd. | Semiconductor device |
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JPH0563029A (ja) * | 1991-09-02 | 1993-03-12 | Fujitsu Ltd | 半導体素子 |
US5249728A (en) * | 1993-03-10 | 1993-10-05 | Atmel Corporation | Bumpless bonding process having multilayer metallization |
KR950004464A (ko) * | 1993-07-15 | 1995-02-18 | 김광호 | 칩 범프의 제조방법 |
US5367763A (en) | 1993-09-30 | 1994-11-29 | Atmel Corporation | TAB testing of area array interconnected chips |
JP2570147B2 (ja) * | 1993-11-18 | 1997-01-08 | 日本電気株式会社 | 半導体装置 |
FR2714528B1 (fr) | 1993-12-27 | 1996-03-15 | Sgs Thomson Microelectronics | Structure de test de circuit intégré. |
US5891745A (en) * | 1994-10-28 | 1999-04-06 | Honeywell Inc. | Test and tear-away bond pad design |
US5973376A (en) * | 1994-11-02 | 1999-10-26 | Lsi Logic Corporation | Architecture having diamond shaped or parallelogram shaped cells |
US6204074B1 (en) * | 1995-01-09 | 2001-03-20 | International Business Machines Corporation | Chip design process for wire bond and flip-chip package |
US5517127A (en) | 1995-01-09 | 1996-05-14 | International Business Machines Corporation | Additive structure and method for testing semiconductor wire bond dies |
JPH09139471A (ja) * | 1995-09-07 | 1997-05-27 | Hewlett Packard Co <Hp> | オンサーキット・アレイ・プロービング用の補助パッド |
US5633210A (en) * | 1996-04-29 | 1997-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming damage free patterned layers adjoining the edges of high step height apertures |
US5719449A (en) * | 1996-09-30 | 1998-02-17 | Lucent Technologies Inc. | Flip-chip integrated circuit with improved testability |
JP3718360B2 (ja) * | 1999-02-09 | 2005-11-24 | ローム株式会社 | 半導体装置 |
-
1996
- 1996-06-12 JP JP8171664A patent/JPH09330934A/ja active Pending
-
1997
- 1997-06-04 TW TW086107705A patent/TW332900B/zh not_active IP Right Cessation
- 1997-06-06 US US08/870,654 patent/US6445001B2/en not_active Expired - Fee Related
- 1997-06-11 KR KR1019970023983A patent/KR100290193B1/ko not_active IP Right Cessation
- 1997-06-12 DE DE69735318T patent/DE69735318T2/de not_active Expired - Fee Related
- 1997-06-12 EP EP97109575A patent/EP0813238B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69735318T2 (de) | 2006-11-02 |
DE69735318D1 (de) | 2006-04-27 |
EP0813238A3 (en) | 1998-11-18 |
JPH09330934A (ja) | 1997-12-22 |
KR980005659A (ko) | 1998-03-30 |
KR100290193B1 (ko) | 2001-05-15 |
EP0813238A2 (en) | 1997-12-17 |
US6445001B2 (en) | 2002-09-03 |
EP0813238B1 (en) | 2006-03-01 |
US20010011771A1 (en) | 2001-08-09 |
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Legal Events
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MM4A | Annulment or lapse of patent due to non-payment of fees |