DE3786178D1 - Schaltung zum angleichen der signalverzoegerungszeiten. - Google Patents
Schaltung zum angleichen der signalverzoegerungszeiten.Info
- Publication number
- DE3786178D1 DE3786178D1 DE8787300348T DE3786178T DE3786178D1 DE 3786178 D1 DE3786178 D1 DE 3786178D1 DE 8787300348 T DE8787300348 T DE 8787300348T DE 3786178 T DE3786178 T DE 3786178T DE 3786178 D1 DE3786178 D1 DE 3786178D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- operable
- adjusting
- signal delay
- delay times
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/466—Sources with reduced influence on propagation delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Electromagnetism (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81978986A | 1986-01-16 | 1986-01-16 | |
US06/889,439 US5041747A (en) | 1986-07-23 | 1986-07-23 | Delay regulation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3786178D1 true DE3786178D1 (de) | 1993-07-22 |
DE3786178T2 DE3786178T2 (de) | 1993-09-23 |
Family
ID=27124393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19873786178 Expired - Fee Related DE3786178T2 (de) | 1986-01-16 | 1987-01-16 | Schaltung zum angleichen der signalverzoegerungszeiten. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0229726B1 (de) |
AU (1) | AU591747B2 (de) |
DE (1) | DE3786178T2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980586A (en) * | 1987-10-07 | 1990-12-25 | Tektronix, Inc. | Digital integrated circuit propagation delay regulator |
US5237224A (en) * | 1990-10-11 | 1993-08-17 | International Business Machines Corporation | Variable self-correcting digital delay circuit |
JP2547909B2 (ja) * | 1990-10-11 | 1996-10-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 可変自己補正ディジタル遅延回路 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4346343A (en) * | 1980-05-16 | 1982-08-24 | International Business Machines Corporation | Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay |
DE3483576D1 (de) * | 1983-12-09 | 1990-12-13 | Fujitsu Ltd | Tor-schaltungsanordnung. |
US4577125A (en) * | 1983-12-22 | 1986-03-18 | Advanced Micro Devices, Inc. | Output voltage driver with transient active pull-down |
-
1987
- 1987-01-14 AU AU67556/87A patent/AU591747B2/en not_active Ceased
- 1987-01-16 EP EP19870300348 patent/EP0229726B1/de not_active Expired - Lifetime
- 1987-01-16 DE DE19873786178 patent/DE3786178T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3786178T2 (de) | 1993-09-23 |
AU591747B2 (en) | 1989-12-14 |
EP0229726A1 (de) | 1987-07-22 |
AU6755687A (en) | 1987-07-23 |
EP0229726B1 (de) | 1993-06-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |