KR950004532A - 고집적 반도체 배선구조 및 그 제조방법 - Google Patents

고집적 반도체 배선구조 및 그 제조방법 Download PDF

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Publication number
KR950004532A
KR950004532A KR1019930014293A KR930014293A KR950004532A KR 950004532 A KR950004532 A KR 950004532A KR 1019930014293 A KR1019930014293 A KR 1019930014293A KR 930014293 A KR930014293 A KR 930014293A KR 950004532 A KR950004532 A KR 950004532A
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KR
South Korea
Prior art keywords
wiring
highly integrated
integrated semiconductor
wiring structure
manufacturing
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Application number
KR1019930014293A
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English (en)
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KR970004922B1 (ko
Inventor
심상필
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930014293A priority Critical patent/KR970004922B1/ko
Priority to TW083106202A priority patent/TW371794B/zh
Priority to JP16147194A priority patent/JP4171076B2/ja
Priority to DE4426311A priority patent/DE4426311B4/de
Priority to GB9414996A priority patent/GB2280545B/en
Priority to CN94114827A priority patent/CN1050448C/zh
Priority to US08/280,887 priority patent/US5567989A/en
Publication of KR950004532A publication Critical patent/KR950004532A/ko
Priority to US08/427,855 priority patent/US5597763A/en
Application granted granted Critical
Publication of KR970004922B1 publication Critical patent/KR970004922B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

자기정렬되는 콘택홀을 이용한 고집적 반도체 배선구조 및 그 제조방법이 제공된다. 다수의 전선배선층과 큰택홀이 형성되는 고집적 반도체 배선구조에 있어서, 상기 다수의 전선배선층들은, 콘택홀이 형성될 배선 부위는 배선넓이가 좁고 나머지 부위는 배선넓이가 넓게 형성된다. 상기 콘택홀은 자기정렬 방식으로 형성되기 때문에, 미스얼라인에 의한 단락을 방지할 수 있어 고집적 반도체 배선구조를 신뢰성있게 달성할 수 있다.

Description

고집적 반도체 배선구조 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 7 도는 본 발명의 배선구조를 적용한 반도체 메모리장치의 레이아웃도.

Claims (4)

  1. 다수의 전선배선층과 콘택홀이 형성되는 고집적 반도체 배선구조에 있어서, 콘택홀이 형성될 배선부위는 배선넓이가 좁고 나머지 부위는 배선넓은 것을 특징으로 하는 고집적 반도체 배선구조.
  2. 제 1 항에 있어서, 다수의 배선이 서로 이웃하여 일정한 방향을 가지고 형성된 것을 특징으로 하는 고집적 반도체 배선구조.
  3. 다수의 전선배선층과 콘택홀을 형성하는 고집적 반도체 배선구조의 제조방법에 있어서, 콘택홀이 형성될 부분은 배선넓이가 좁고 나머지 부위는 배선넓이가 넓은 제1배선층을 반도체기판 상에 형성하는 단계 ; 상기 기판상에 절연막을 형성한 다음, 이를 이방성식각하여 상기 넓이가 좁은 제 1 배선층의 주위에 콘택홀을 형성하는 단계 및 상기 콘택홀에 제 2 배선층을 형성하는 단계를 포함하는 것을 특징으로 하는 고집적 반도체 배선구조의 제조방법.
  4. 제 3 항에 있어서, 상기 절연막의 두께가 상기 제 1 배선층의 넓이가 넓은 부분의 간격의 1/2이상 두껍게 형성하는 것을 특징으로 하는 고집적 반도체 배선구조의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930014293A 1993-07-27 1993-07-27 고집적 반도체 배선구조 및 그 제조방법 KR970004922B1 (ko)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1019930014293A KR970004922B1 (ko) 1993-07-27 1993-07-27 고집적 반도체 배선구조 및 그 제조방법
TW083106202A TW371794B (en) 1993-07-27 1994-07-07 A highly integrated semiconductor wiring structure and a method for manufacturing the same
JP16147194A JP4171076B2 (ja) 1993-07-27 1994-07-13 半導体メモリ装置の製造方法
DE4426311A DE4426311B4 (de) 1993-07-27 1994-07-25 Leiterbahnstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung
GB9414996A GB2280545B (en) 1993-07-27 1994-07-26 A highly integrated semi-conductor wiring structure and a method for manufacturng the same
CN94114827A CN1050448C (zh) 1993-07-27 1994-07-27 具有高集成度布线结构的半导体器件及其制造方法
US08/280,887 US5567989A (en) 1993-07-27 1994-07-27 Highly integrated semiconductor wiring structure
US08/427,855 US5597763A (en) 1993-07-27 1995-04-26 Method for manufacturing a semiconductor wiring structure including a self-aligned contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930014293A KR970004922B1 (ko) 1993-07-27 1993-07-27 고집적 반도체 배선구조 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR950004532A true KR950004532A (ko) 1995-02-18
KR970004922B1 KR970004922B1 (ko) 1997-04-08

Family

ID=19360118

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Application Number Title Priority Date Filing Date
KR1019930014293A KR970004922B1 (ko) 1993-07-27 1993-07-27 고집적 반도체 배선구조 및 그 제조방법

Country Status (7)

Country Link
US (2) US5567989A (ko)
JP (1) JP4171076B2 (ko)
KR (1) KR970004922B1 (ko)
CN (1) CN1050448C (ko)
DE (1) DE4426311B4 (ko)
GB (1) GB2280545B (ko)
TW (1) TW371794B (ko)

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JPH10209393A (ja) * 1997-01-22 1998-08-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6221711B1 (en) 1998-05-11 2001-04-24 Micron Technology, Inc. Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry
US6410453B1 (en) 1999-09-02 2002-06-25 Micron Technology, Inc. Method of processing a substrate
KR100339683B1 (ko) 2000-02-03 2002-06-05 윤종용 반도체 집적회로의 자기정렬 콘택 구조체 형성방법
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JP5064651B2 (ja) * 2003-11-14 2012-10-31 ラピスセミコンダクタ株式会社 半導体記憶装置
US7918800B1 (en) * 2004-10-08 2011-04-05 Endovascular Technologies, Inc. Aneurysm sensing devices and delivery systems
US7709390B2 (en) * 2007-05-31 2010-05-04 Micron Technology, Inc. Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features
US10037941B2 (en) * 2014-12-12 2018-07-31 Qualcomm Incorporated Integrated device package comprising photo sensitive fill between a substrate and a die
TWI722418B (zh) * 2019-04-19 2021-03-21 華邦電子股份有限公司 半導體結構及其製造方法
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Also Published As

Publication number Publication date
DE4426311B4 (de) 2004-08-12
GB2280545B (en) 1997-08-13
CN1050448C (zh) 2000-03-15
JPH0758219A (ja) 1995-03-03
GB2280545A (en) 1995-02-01
US5567989A (en) 1996-10-22
TW371794B (en) 1999-10-11
US5597763A (en) 1997-01-28
KR970004922B1 (ko) 1997-04-08
DE4426311A1 (de) 1995-02-02
CN1102506A (zh) 1995-05-10
GB9414996D0 (en) 1994-09-14
JP4171076B2 (ja) 2008-10-22

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