WO2000049652A8 - Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique - Google Patents

Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique

Info

Publication number
WO2000049652A8
WO2000049652A8 PCT/JP2000/000710 JP0000710W WO0049652A8 WO 2000049652 A8 WO2000049652 A8 WO 2000049652A8 JP 0000710 W JP0000710 W JP 0000710W WO 0049652 A8 WO0049652 A8 WO 0049652A8
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
bonding material
circuit board
electronic device
semiconductor chip
Prior art date
Application number
PCT/JP2000/000710
Other languages
English (en)
Japanese (ja)
Other versions
WO2000049652A1 (fr
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corp
Nobuaki Hashimoto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Nobuaki Hashimoto filed Critical Seiko Epson Corp
Priority to JP2000600302A priority Critical patent/JP4029255B2/ja
Publication of WO2000049652A1 publication Critical patent/WO2000049652A1/fr
Publication of WO2000049652A8 publication Critical patent/WO2000049652A8/fr

Links

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention concerne un dispositif semi-conducteur (1) comprenant un microcircuit semi-conducteur (10), un substrat (20) pourvu de réseaux de câblage (22), et un matériau de liaison (30) qui relie électriquement le microcircuit semi-conducteur (10) et les réseaux de câblage (22). Le matériau de liaison (30) présente une structure bi-couche. En l'occurrence, la première couche (32), qui comporte une première base en résine, est tournée vers le microcircuit semi-conducteur (10), la seconde couche (34) qui comporte une seconde base en résine, est tournée vers le substrat (20). Les deux couches de résine présentent des propriétés physiques différentes telles que le coefficient de dilatation.
PCT/JP2000/000710 1999-02-18 2000-02-09 Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique WO2000049652A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000600302A JP4029255B2 (ja) 1999-02-18 2000-02-09 接着部材

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3962599 1999-02-18
JP11/39625 1999-02-18

Publications (2)

Publication Number Publication Date
WO2000049652A1 WO2000049652A1 (fr) 2000-08-24
WO2000049652A8 true WO2000049652A8 (fr) 2000-10-26

Family

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Country Link
JP (1) JP4029255B2 (fr)
KR (1) KR100514425B1 (fr)
TW (1) TW550714B (fr)
WO (1) WO2000049652A1 (fr)

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Publication number Priority date Publication date Assignee Title
FR2863767B1 (fr) * 2003-12-12 2006-06-09 Commissariat Energie Atomique Support memoire irreversible a deformation plastique et procede de realisation d'un tel support
JP2006100752A (ja) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd 回路装置およびその製造方法
KR102492533B1 (ko) 2017-09-21 2023-01-30 삼성전자주식회사 지지 기판, 이를 이용한 반도체 패키지의 제조방법 및 이를 이용한 전자 장치의 제조 방법
TWI714905B (zh) * 2018-11-08 2021-01-01 瑞昱半導體股份有限公司 電路裝置與電路設計及組裝方法
CN114023704B (zh) * 2022-01-05 2022-04-01 长鑫存储技术有限公司 非导电膜及其形成方法、芯片封装结构及方法
CN114374101A (zh) * 2022-01-12 2022-04-19 业成科技（成都）有限公司 连接结构和形成连接结构的方法

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JPH0513119A (ja) * 1991-07-04 1993-01-22 Sharp Corp 電子部品接続用テープコネクタ
JP2930186B2 (ja) * 1996-03-28 1999-08-03 松下電器産業株式会社 半導体装置の実装方法および半導体装置の実装体
JPH1013002A (ja) * 1996-06-20 1998-01-16 Matsushita Electric Ind Co Ltd 半導体素子の実装方法
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JPH10199930A (ja) * 1996-12-28 1998-07-31 Casio Comput Co Ltd 電子部品の接続構造および接続方法

Also Published As

Publication number Publication date
KR100514425B1 (ko) 2005-09-14
TW550714B (en) 2003-09-01
KR20010042822A (ko) 2001-05-25
WO2000049652A1 (fr) 2000-08-24
JP4029255B2 (ja) 2008-01-09

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