WO2000049652A8 - Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device - Google Patents

Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device

Info

Publication number
WO2000049652A8
WO2000049652A8 PCT/JP2000/000710 JP0000710W WO0049652A8 WO 2000049652 A8 WO2000049652 A8 WO 2000049652A8 JP 0000710 W JP0000710 W JP 0000710W WO 0049652 A8 WO0049652 A8 WO 0049652A8
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
bonding material
circuit board
electronic device
semiconductor chip
Prior art date
Application number
PCT/JP2000/000710
Other languages
French (fr)
Japanese (ja)
Other versions
WO2000049652A1 (en
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corp
Nobuaki Hashimoto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Nobuaki Hashimoto filed Critical Seiko Epson Corp
Priority to JP2000600302A priority Critical patent/JP4029255B2/en
Publication of WO2000049652A1 publication Critical patent/WO2000049652A1/en
Publication of WO2000049652A8 publication Critical patent/WO2000049652A8/en

Links

Classifications

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device (1) comprises a semiconductor chip (10), a substrate (20) with wiring patterns (22), and bonding material (30) that connects the semiconductor chip (10) and the wiring patterns (22) electrically. The bonding material (30) has a two-layer structure which includes a first layer (32) having a first resin base and opposed to the semiconductor chip (10) and a second layer (34) having a second resin base and opposed to the substrate (20). The first resin and the second resin have different physical properties such as thermal expansion coefficient.
PCT/JP2000/000710 1999-02-18 2000-02-09 Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device WO2000049652A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000600302A JP4029255B2 (en) 1999-02-18 2000-02-09 Adhesive member

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3962599 1999-02-18
JP11/39625 1999-02-18

Publications (2)

Publication Number Publication Date
WO2000049652A1 WO2000049652A1 (en) 2000-08-24
WO2000049652A8 true WO2000049652A8 (en) 2000-10-26

Family

ID=12558298

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/000710 WO2000049652A1 (en) 1999-02-18 2000-02-09 Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device

Country Status (4)

Country Link
JP (1) JP4029255B2 (en)
KR (1) KR100514425B1 (en)
TW (1) TW550714B (en)
WO (1) WO2000049652A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2863767B1 (en) * 2003-12-12 2006-06-09 Commissariat Energie Atomique IRREVERSIBLE MEMORY HOLDER WITH PLASTIC DEFORMATION AND METHOD OF MAKING SUCH A SUPPORT
JP2006100752A (en) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Circuit arrangement and its manufacturing method
KR102492533B1 (en) 2017-09-21 2023-01-30 삼성전자주식회사 Support substrate, Method of fabricating a semiconductor Package and Method of fabricating an electronic device
TWI714905B (en) * 2018-11-08 2021-01-01 瑞昱半導體股份有限公司 Circuit device and circuit design and assembly method
CN114023704B (en) * 2022-01-05 2022-04-01 长鑫存储技术有限公司 Non-conductive film, forming method thereof, chip packaging structure and method
CN114374101A (en) * 2022-01-12 2022-04-19 业成科技（成都）有限公司 Connection structure and method of forming a connection structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513119A (en) * 1991-07-04 1993-01-22 Sharp Corp Tape connector for connecting electronic parts
JP2930186B2 (en) * 1996-03-28 1999-08-03 松下電器産業株式会社 Semiconductor device mounting method and semiconductor device mounted body
JPH1013002A (en) * 1996-06-20 1998-01-16 Matsushita Electric Ind Co Ltd Method for mounting semiconductor element
JPH1084014A (en) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd Manufacture of semiconductor device
JPH10199930A (en) * 1996-12-28 1998-07-31 Casio Comput Co Ltd Connection structure of electronic components and connecting method therefor

Also Published As

Publication number Publication date
KR20010042822A (en) 2001-05-25
TW550714B (en) 2003-09-01
JP4029255B2 (en) 2008-01-09
WO2000049652A1 (en) 2000-08-24
KR100514425B1 (en) 2005-09-14

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