KR950021447A - 반도체 장치 및 그 제조방법 - Google Patents
반도체 장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR950021447A KR950021447A KR1019940024797A KR19940024797A KR950021447A KR 950021447 A KR950021447 A KR 950021447A KR 1019940024797 A KR1019940024797 A KR 1019940024797A KR 19940024797 A KR19940024797 A KR 19940024797A KR 950021447 A KR950021447 A KR 950021447A
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- electrode
- jumper
- package substrate
- contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
반도체 장치는 패키지 기판관 패키지 기판상에 제공된 반도체 칩을 포함하여 전극을 갖는 점퍼기판과 전극을 접속하는 도체패턴이 제공되어 있어서, 패키지 기판상에 제공된 통공에 대응하여 분리되는 전극과 반도체 칩상에 전극패트와의 전기접속하여 패키지 기판의 상면에 제공된 전극패턴 사이의 상호접속을 제공하기 위하여 패키지 기판상에 점퍼기판이 탑재된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 제1실시예에 따른 반도체 장치의 단면도.
제5도는 제4도의 반도체 장치의 일부의 평면도.
Claims (19)
- 전극패드를 갖는 반도체 칩 ; 상면과 하면을 갖고 상기 반도체 칩을 상면에 지지하기 위한 패키지 기판; 상기 반도체 칩상의 전극패드에 전기접속하여 제1면적에 패키지 기판의 상면에 제공된 제1그룹전극; 제1면적과 다른 제2면적에 패키지 기판의 상면에 제공된 제2그룹 전극; 외부접속하기 위하여 패키지 기판의 하면에 제공된 제3그룹전극; 패키지 기판의 상면에서 하면으로 연장되도록 패키지 기판상에 제공되고, 각각 제3그룹 전극중 대응하는 전극에 제2그룹 전극중 한 전극을 접속하고 제2그룹 전극에 제1그룹 전극을 전기접속하기 위한 도전부재를 포함하는 통공; 상면과 하면을 갖고 점퍼 (jumper)기판의 하면이 패키지 기판의 상면에 접하도록 패키지 기판의 상면에 배치되는 점퍼기판, 상기 점퍼기판은 패키지 기판의 상면에 제1그룹 전극과 전기 접속하여 하면에 제1접점,패키지 기판의 상면에 제2그룹 전극과 전기접속하여 하면에 제2접점과 상기 점퍼 기판상의 제2접점중 대응하는 접점에 상기 점퍼기판상의 제1접점의 각 접점을 접속하는 상호접속 패턴을 가지며, 상기 점퍼기판은 반도체 칩을 수납하기 위하여 점퍼기판의 상면에서 하면으로 연장되는 개구를 가지며; 패키지 기판의 상면의 점퍼 기판과 함께 반도체 칩을 밀봉하기 위하여 패키지 기판의 상면에 제공된 수지본체로 구성되는 반도체 장치.
- 제2항에 있어서, 상기 점퍼기판이 반도체 칩에서 발생되는 열을 방출하기 위하여 그 상면에 히트싱크 부재를 구비하는 반도체 장치.
- 제2항에 있어서, 상기 반도체 칩과 상기 히트싱크 부재 사이에 열 전도성 수지를 개재한 반도체 장치.
- 제1항에 있어서, 상기 반도체 칩이 반도체 칩상에 전극패드가 제1그룹 전극들중 대응하는 전극과의 접속을 하는 상태로 패키지 기판상에 탑재되는 반도체 장치.
- 제1항에 있어서, 상기 반도체 칩상에 전극패드의 각각이 본딩 화이어에 의해 제1그룹 전극들중 대응하는 전극에 접속되는 반도체 장치.
- 제1항에 있어서, 상기 점퍼기판이 다수의 기판층과 대응하는 다수의 도체 패턴을 포함하는 다층 인쇄 회로판으로 구성되는 반도체 장치.
- 상면에 제1그룹 전극과 제2그룹 전극 및 하면에 제3그룹 전극을 갖추고, 제2및 제3그룹 전극에 대응하여 각각 제2그룹 전극중 하전극과 제3그룹 전극중 대응하는 한 전극 사이에 상면에서 하면까지 연장되도록 통공을 더 갖는 패키지 기판상에 반도체 칩을 탑재하는 단계와, 이 탑재 단계는 반도체 칩상에 전극패드가 패키지 기판상에 제1그룹 전극과의 전기접속을 하도록 행해지며, 제1접점, 제2접점, 및 제1접점과 제2접점 사이에 연장되는 상호 접속 패턴을 갖는 점퍼기판을 패키지 기판상에 탑재하여, 제1접점의 각각이 제1그룹 전극중 대응하는 전극과의 접촉을 확립하고 제2접점의 각각이 제2그룹 전극중 대응하는 전극과의 접촉을 확립하는 단계로 구성되는 반도체 장치의 제조방법.
- 제7항에 있어서, 상기 반도체 칩을 탑재하는 단계가 플립-칩 공정에 의하여 행해지는 반도체 제조방법.
- 제7항에 있어서, 상기 반도체 칩을 탑재하는 단계가 본딩 와이어에 의하여 행해지는 반도체 제조방법.
- 제7항에 있어서, 상기 반도체 칩을 탑재하는 단계와 상기 점퍼기판을 탑재하는 단계가 리플로우 공정을 행함으로써 동시에 행해지는 반도체 장치의 제조방법.
- 제7항에 있어서, 상기 점퍼기판이 반도체 칩의 크기와 헝상에 대응하는 크기와 형상을 갖는 개구를 구비하며, 상기 점퍼기판을 탑재하는 단계는 상기 점퍼기판의 개구가 패키지 기판상에 반도체 칩을 지지하는 영역을 규정하도록 행해지고, 상기의 방법이 반도체 칩을 탑재하는 단계와 점퍼기판을 탑재하는 단계후에 수지에 의해 공간을 채우는 단계로 더 구성되는 반도체 장치의 제조방법.
- 제7항에 있어서, 상기의 방법이 점퍼기판상에 지지하도록 점퍼기판상에 히트싱크 구조를 제공하는 단계로 더 구성되며, 상기 히트싱크 구조를 제공하는 단계가 반도체 칩을 탑재하는 단계와 점퍼기판을 탑재하는 단계후에 행해지는 반도체 장치의 제조방법.
- 제12항에 있어서, 상기 히트싱크 구조를 제공하는 단계가 수지내에 반도체 칩을 내장하도록 수지에 의해 개구를 채우는 단계후에 행하여져서, 히트싱트 구조가 개구내에 수지와의 밀착상태를 확립하는 반도체 장치의 제조방법.
- 전극패드를 갖는 구성부분 ; 상면과 하면을 갖고 상기 구성부분을 상면에 지지하기 위한 패키지 기판; 상기 구성부분상의 전극패드에 전기접속하여 제1면적에 패키지 기판의 상면에 제공된 제1그룹전극; 제1면적과 다른 제면적에 패키지 기판의 상면에 제공된 제2그룹 전극; 외부접속하기 위하여 패키지 기판의 하면에 제공된 제3그룹전극; 패키지 기판의 상면에서 하면으로 연장되도록 패키지 기판상에 제공되고, 각각 제3그룹 전극중 대응하는 전극에 제2그룹 전극중 한 전극을 접속하고 제2그룹 전극에 제1그룹 전극을 전기접속하기 위한 도전부재를 포함하는 통공; 상면과 하면을 갖고 점퍼 (jumper)기판의 하면이 패키지 기판의 상면에 접하도록 패키지 기판의 상면에 배치되는 점퍼기판, 상기 점퍼기판은 패키지 기판의 상면에 제1그룹 전극과 전기 접속하여 하면에 제1접점, 패키지 기판의 상면에 제2그룹 전극과 전기접속하여 하면에 제2접점과 상기 점퍼 기판상의 제2접점중 대응하는 접점에 상기 점퍼기판상의 제1접점의 각 접점을 접속하는 상호접속 패턴을 가지며, 상기 점퍼기판은 구성부분을 수납하기 위하여 점퍼기관의 상면에서 하면으로 연장되는 개구를 가지며; 패키지 기판의 상면의 점퍼 기판과 함께 구성부분을 밀봉하기 위하여 패키지 기판의 상면에 제공된 수지본체로 구성되는 패키지 구조.
- 제14항에 있어서, 상기 점퍼기판이 구성부분에서 발생되는 열을 방출하기 위하여 그 상면에 히트싱크 부재를 구비하는 패키지 구조.
- 제15항에 있어서, 상기 구성부분과 상기 히트싱크 부재 사이에 열 전도성 수지를 개재하는 패키지 구조.
- 제14항에 있어서, 상기 구성부분은 구성부분상에 전극 패드의 각각이 제1그룹 전극들중 대응하는 전극과의 접촉을 확립하는 패키지 구조.
- 제17항에 있어서, 상기 구성부분에 전극패드의 각각이 본딩 와이어에 의하여 제1그롭 전극들중 대응하는 전극에 접속되는 패키지 구조.
- 제14항에 있어서, 상기 점퍼기판이 다수의 기판층과 대응하는 다수의 도체패턴을 포함하는 다층 인쇄 회로판으로 구성되는 패키지 구조.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-312302 | 1993-12-13 | ||
JP5312302A JPH07169872A (ja) | 1993-12-13 | 1993-12-13 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950021447A true KR950021447A (ko) | 1995-07-26 |
KR0156480B1 KR0156480B1 (ko) | 1998-10-15 |
Family
ID=18027620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940024797A KR0156480B1 (ko) | 1993-12-13 | 1994-09-29 | 반도체 장치 및 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US5521435A (ko) |
JP (1) | JPH07169872A (ko) |
KR (1) | KR0156480B1 (ko) |
Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07221105A (ja) * | 1994-01-31 | 1995-08-18 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
US5741729A (en) * | 1994-07-11 | 1998-04-21 | Sun Microsystems, Inc. | Ball grid array package for an integrated circuit |
JP2967697B2 (ja) * | 1994-11-22 | 1999-10-25 | ソニー株式会社 | リードフレームの製造方法と半導体装置の製造方法 |
JP3400877B2 (ja) * | 1994-12-14 | 2003-04-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
TW373308B (en) * | 1995-02-24 | 1999-11-01 | Agere Systems Inc | Thin packaging of multi-chip modules with enhanced thermal/power management |
US5637920A (en) * | 1995-10-04 | 1997-06-10 | Lsi Logic Corporation | High contact density ball grid array package for flip-chips |
JP3248149B2 (ja) * | 1995-11-21 | 2002-01-21 | シャープ株式会社 | 樹脂封止型半導体装置及びその製造方法 |
JPH09162320A (ja) * | 1995-12-08 | 1997-06-20 | Shinko Electric Ind Co Ltd | 半導体パッケージおよび半導体装置 |
US6861290B1 (en) * | 1995-12-19 | 2005-03-01 | Micron Technology, Inc. | Flip-chip adaptor package for bare die |
US5723369A (en) * | 1996-03-14 | 1998-03-03 | Lsi Logic Corporation | Method of flip chip assembly |
US5660321A (en) * | 1996-03-29 | 1997-08-26 | Intel Corporation | Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts |
KR100216839B1 (ko) * | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
US6169329B1 (en) * | 1996-04-02 | 2001-01-02 | Micron Technology, Inc. | Semiconductor devices having interconnections using standardized bonding locations and methods of designing |
US5774340A (en) * | 1996-08-28 | 1998-06-30 | International Business Machines Corporation | Planar redistribution structure and printed wiring device |
US6962829B2 (en) * | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
US5981314A (en) * | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
US5837153A (en) * | 1997-01-15 | 1998-11-17 | Kawan; Joseph C. | Method and system for creating and using a logotype contact module with a smart card |
US6034429A (en) * | 1997-04-18 | 2000-03-07 | Amkor Technology, Inc. | Integrated circuit package |
US6117705A (en) * | 1997-04-18 | 2000-09-12 | Amkor Technology, Inc. | Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate |
US6114763A (en) * | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
US5909056A (en) * | 1997-06-03 | 1999-06-01 | Lsi Logic Corporation | High performance heat spreader for flip chip packages |
JPH1168026A (ja) * | 1997-06-13 | 1999-03-09 | Ricoh Co Ltd | 配線用補助パッケージおよび印刷回路配線板構造 |
US5796038A (en) * | 1997-06-16 | 1998-08-18 | Vlsi Technology, Inc. | Technique to produce cavity-up HBGA packages |
US5981312A (en) * | 1997-06-27 | 1999-11-09 | International Business Machines Corporation | Method for injection molded flip chip encapsulation |
US5962810A (en) * | 1997-09-09 | 1999-10-05 | Amkor Technology, Inc. | Integrated circuit package employing a transparent encapsulant |
JP2954108B2 (ja) * | 1997-09-22 | 1999-09-27 | 九州日本電気株式会社 | 半導体装置およびその製造方法 |
SG71734A1 (en) * | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
JP3638771B2 (ja) * | 1997-12-22 | 2005-04-13 | 沖電気工業株式会社 | 半導体装置 |
US5953814A (en) * | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
US6125042A (en) * | 1998-04-10 | 2000-09-26 | Lucent Technologies, Inc. | Ball grid array semiconductor package having improved EMI characteristics |
USRE43112E1 (en) * | 1998-05-04 | 2012-01-17 | Round Rock Research, Llc | Stackable ball grid array package |
JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
DE69938582T2 (de) | 1998-09-09 | 2009-06-04 | Seiko Epson Corp. | Halbleiterbauelement, seine herstellung, leiterplatte und elektronischer apparat |
US6514845B1 (en) * | 1998-10-15 | 2003-02-04 | Texas Instruments Incorporated | Solder ball contact and method |
US6396136B2 (en) * | 1998-12-31 | 2002-05-28 | Texas Instruments Incorporated | Ball grid package with multiple power/ground planes |
US6297551B1 (en) * | 1999-09-22 | 2001-10-02 | Agere Systems Guardian Corp. | Integrated circuit packages with improved EMI characteristics |
JP2001144218A (ja) * | 1999-11-17 | 2001-05-25 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
US6396043B1 (en) | 1999-11-22 | 2002-05-28 | Amkor Technology, Inc. | Thin image sensor package fabrication method |
US6627864B1 (en) | 1999-11-22 | 2003-09-30 | Amkor Technology, Inc. | Thin image sensor package |
JP2001156251A (ja) * | 1999-11-25 | 2001-06-08 | Mitsubishi Electric Corp | 半導体装置 |
US6678167B1 (en) * | 2000-02-04 | 2004-01-13 | Agere Systems Inc | High performance multi-chip IC package |
JP3752949B2 (ja) * | 2000-02-28 | 2006-03-08 | 日立化成工業株式会社 | 配線基板及び半導体装置 |
US6571466B1 (en) | 2000-03-27 | 2003-06-03 | Amkor Technology, Inc. | Flip chip image sensor package fabrication method |
DE10034865B4 (de) * | 2000-07-18 | 2006-06-01 | Infineon Technologies Ag | Optoelektronisches oberflächenmontierbares Modul |
US6342406B1 (en) | 2000-11-15 | 2002-01-29 | Amkor Technology, Inc. | Flip chip on glass image sensor package fabrication method |
US6849916B1 (en) | 2000-11-15 | 2005-02-01 | Amkor Technology, Inc. | Flip chip on glass sensor package |
US6570259B2 (en) | 2001-03-22 | 2003-05-27 | International Business Machines Corporation | Apparatus to reduce thermal fatigue stress on flip chip solder connections |
US6954362B2 (en) * | 2001-08-31 | 2005-10-11 | Kyocera Wireless Corp. | System and method for reducing apparent height of a board system |
US20050051859A1 (en) * | 2001-10-25 | 2005-03-10 | Amkor Technology, Inc. | Look down image sensor package |
US6622380B1 (en) * | 2002-02-12 | 2003-09-23 | Micron Technology, Inc. | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
JP2003264260A (ja) * | 2002-03-08 | 2003-09-19 | Toshiba Corp | 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板 |
US7065113B2 (en) * | 2002-04-30 | 2006-06-20 | Mohammed Ershad Ali | Method and apparatus for interconnecting a laser array and an integrated circuit of a laser-based transmitter |
TW554500B (en) * | 2002-07-09 | 2003-09-21 | Via Tech Inc | Flip-chip package structure and the processing method thereof |
US6987032B1 (en) * | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US6979594B1 (en) | 2002-07-19 | 2005-12-27 | Asat Ltd. | Process for manufacturing ball grid array package |
US7087988B2 (en) * | 2002-07-30 | 2006-08-08 | Kabushiki Kaisha Toshiba | Semiconductor packaging apparatus |
US6965160B2 (en) * | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) * | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US7419852B2 (en) * | 2004-08-27 | 2008-09-02 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies |
US7528474B2 (en) * | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
US7414196B2 (en) * | 2005-06-13 | 2008-08-19 | John Mezzalingua Associates, Inc. | Casing for RF filter |
TWI269361B (en) * | 2005-06-17 | 2006-12-21 | Advanced Semiconductor Eng | Structure of substrate integrated embedded passive component and method of forming the same |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
JP5468242B2 (ja) * | 2008-11-21 | 2014-04-09 | 株式会社東芝 | Memsパッケージおよびmemsパッケージの製造方法 |
JP5814498B2 (ja) * | 2008-12-25 | 2015-11-17 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 高周波モジュール |
US8405115B2 (en) * | 2009-01-28 | 2013-03-26 | Maxim Integrated Products, Inc. | Light sensor using wafer-level packaging |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US20120314390A1 (en) * | 2010-03-03 | 2012-12-13 | Mutual-Tek Industries Co., Ltd. | Multilayer circuit board |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
JP2011155313A (ja) * | 2011-05-18 | 2011-08-11 | Casio Computer Co Ltd | 半導体装置 |
KR101257218B1 (ko) * | 2011-09-30 | 2013-04-29 | 에스티에스반도체통신 주식회사 | 패키지 온 패키지 및 이의 제조방법 |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
TWM458672U (zh) * | 2013-04-10 | 2013-08-01 | Genesis Photonics Inc | 光源模組 |
US9406641B2 (en) * | 2013-07-10 | 2016-08-02 | Kinsus Interconnect Technology Corp. | Compound carrier board structure of flip-chip chip-scale package and manufacturing method thereof |
US9496297B2 (en) | 2013-12-05 | 2016-11-15 | Optiz, Inc. | Sensor package with cooling feature and method of making same |
TWI553788B (zh) * | 2014-11-14 | 2016-10-11 | Modified composite wafer carrier structure | |
US10170403B2 (en) | 2014-12-17 | 2019-01-01 | Kinsus Interconnect Technology Corp. | Ameliorated compound carrier board structure of flip-chip chip-scale package |
KR101952862B1 (ko) * | 2016-08-30 | 2019-02-27 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US9996725B2 (en) | 2016-11-03 | 2018-06-12 | Optiz, Inc. | Under screen sensor assembly |
CN111199959B (zh) * | 2018-11-19 | 2021-11-02 | 台达电子企业管理(上海)有限公司 | 功率模块的封装结构 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2439478A1 (fr) * | 1978-10-19 | 1980-05-16 | Cii Honeywell Bull | Boitier plat pour dispositifs a circuits integres |
US4233620A (en) * | 1979-02-27 | 1980-11-11 | International Business Machines Corporation | Sealing of integrated circuit modules |
US4633573A (en) * | 1982-10-12 | 1987-01-06 | Aegis, Inc. | Microcircuit package and sealing method |
JPS61111561A (ja) * | 1984-10-05 | 1986-05-29 | Fujitsu Ltd | 半導体装置 |
CA1250634A (en) * | 1984-11-19 | 1989-02-28 | Melvin C. Maki | Simulated targets for detection systems |
JPS63124449A (ja) * | 1986-11-13 | 1988-05-27 | Hitachi Ltd | 高密度実装モジユ−ル |
US4835120A (en) * | 1987-01-12 | 1989-05-30 | Debendra Mallik | Method of making a multilayer molded plastic IC package |
US4769272A (en) * | 1987-03-17 | 1988-09-06 | National Semiconductor Corporation | Ceramic lid hermetic seal package structure |
US4901136A (en) * | 1987-07-14 | 1990-02-13 | General Electric Company | Multi-chip interconnection package |
US5206188A (en) * | 1990-01-31 | 1993-04-27 | Ibiden Co., Ltd. | Method of manufacturing a high lead count circuit board |
US5342807A (en) * | 1991-06-04 | 1994-08-30 | Micron Technology, Inc. | Soft bond for semiconductor dies |
US5102829A (en) * | 1991-07-22 | 1992-04-07 | At&T Bell Laboratories | Plastic pin grid array package |
JP2509027B2 (ja) * | 1991-10-16 | 1996-06-19 | 三菱電機株式会社 | 半導体装置 |
JP2982450B2 (ja) * | 1991-11-26 | 1999-11-22 | 日本電気株式会社 | フィルムキャリア半導体装置及びその製造方法 |
TW258829B (ko) * | 1994-01-28 | 1995-10-01 | Ibm | |
DE69527473T2 (de) * | 1994-05-09 | 2003-03-20 | Nec Corp., Tokio/Tokyo | Halbleiteranordnung bestehend aus einem Halbleiterchip, der mittels Kontakthöckern auf der Leiterplatte verbunden ist und Montageverfahren |
-
1993
- 1993-12-13 JP JP5312302A patent/JPH07169872A/ja not_active Withdrawn
-
1994
- 1994-09-08 US US08/301,403 patent/US5521435A/en not_active Expired - Fee Related
- 1994-09-29 KR KR1019940024797A patent/KR0156480B1/ko not_active IP Right Cessation
-
1996
- 1996-02-21 US US08/603,616 patent/US5578525A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5521435A (en) | 1996-05-28 |
US5578525A (en) | 1996-11-26 |
KR0156480B1 (ko) | 1998-10-15 |
JPH07169872A (ja) | 1995-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950021447A (ko) | 반도체 장치 및 그 제조방법 | |
KR930010086B1 (ko) | 반도체 집적회로장치 | |
US6396136B2 (en) | Ball grid package with multiple power/ground planes | |
US4710798A (en) | Integrated circuit chip package | |
US6921972B1 (en) | Leadless chip carrier design and structure | |
KR950030321A (ko) | 반도체장치 및 그 제조방법 및 기판 | |
KR940022755A (ko) | 반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame) | |
KR970030750A (ko) | 반도체장치 및 그것을 사용한 전자장치 | |
US7109573B2 (en) | Thermally enhanced component substrate | |
KR100386018B1 (ko) | 스택형반도체디바이스패키지 | |
US6034437A (en) | Semiconductor device having a matrix of bonding pads | |
US4964019A (en) | Multilayer bonding and cooling of integrated circuit devices | |
KR960706193A (ko) | 전도성 트레이스와 리드 프레임 리드를 결합하는 고밀도 집적회로 조립체(a high density integrated circuit assembly combining leadframe leads with conductive traces) | |
KR20000011282A (ko) | 반도체장치및그제조방법 | |
JP2001168233A (ja) | 多重回線グリッド・アレイ・パッケージ | |
US6249048B1 (en) | Polymer stud grid array | |
KR960035997A (ko) | 반도체 패키지 및 그 제조방법 | |
US7190056B2 (en) | Thermally enhanced component interposer: finger and net structures | |
JPH0917917A (ja) | 配線基板及び半導体装置 | |
JPH1093013A (ja) | 半導体装置 | |
KR970069482A (ko) | 반도체 장치 및 그의 제조방법과 그의 실장방법 | |
KR950021298A (ko) | 반도체 집적 회로 장치 | |
KR100367729B1 (ko) | 멀티플 라인 그리드 어레이 패키지 | |
KR960019683A (ko) | 반도체 장치 | |
JPH10150065A (ja) | チップサイズパッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040709 Year of fee payment: 7 |
|
LAPS | Lapse due to unpaid annual fee |