CN111199959B - 功率模块的封装结构 - Google Patents
功率模块的封装结构 Download PDFInfo
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
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Abstract
本发明揭露一种功率模块的封装结构,包括:散热基板;至少一第一功率器件,被配置于具有绝缘层的第一基板上,且所述第一基板被配置于所述散热基板上;至少一第二功率器件,其包括具有跳变电位的跳变电极,其中所述至少一第二功率器件被配置于具有绝缘层的至少一第二基板之上,且所述第二基板被配置于所述第一基板之上,以减小所述跳变电极与所述散热基板之间的寄生电容。本发明的功率模块的封装结构可减小功率模块跳变电极相对于散热基板的寄生电容,从而极大减小功率模块的在实际工作中的EMI噪声。
Description
技术领域
本发明是关于功率模块的封装结构,特别是关于一种低EMI(Electro-MagneticInterference,电磁干扰)噪声的功率模块的封装结构。
背景技术
随着电力电子器件朝着模块化、智能化的方向发展,各类IC芯片的集成度越来越高,功率密度也越来越大。功率半导体器件也取得了长足进步,朝着高温、高频、低功耗、高功率容量以及智能化、系统化的方向发展。同时,新结构、新工艺不断出现,以SiC为代表的功率半导体器件也得到了广泛应用,尤其在一些相对较大功率的应用场合,SiC功率模块的应用越来越多。
常见的分离器件通常采用标准化的封装,其可以保证较高的可靠性和较低的成本,但是其内部存在较大的寄生参数(parasitic parameter),使得其不适合应用于并联使用场合。而功率电子封装技术从解决模块的封装结构、模块内部芯片与基板互连等问题出发,可使各种元器件的不利寄生参数减小,同时具有更大的电流承载能力,减小模块体积重量,提高系统功率密度。
目前的功率模块的封装形式按组装工艺和安装固定方法主要分为:压接式结构、焊接结构以及直接敷铜(Direct Bonding Copper,DBC)基板结构等形式。其中DBC基板结构具有更好的热疲劳稳定性和很高的集成度。
现有的功率半导体芯片的基本结构如图1所示,对于常见的金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field Effect Transistor,MOSFET)、绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)、二极管(Diode)等功率半导体芯片,其中MOSFET芯片一般具有源极(Source)S、栅极(Gate)G和漏极(Drain)D,IGBT芯片一般具有发射极(Emitter)E、门极(Gate)G和集电极(Collect)C,二极管芯片一般具有阳极(Anode)A和阴极(Kathode)K,而这些芯片的漏极D、集电极C、阴极K等一般是被设置在芯片的底部。如图2所示,当采用DBC基板22进行功率模块封装时,一般会将这些芯片23的底部和DBC基板21焊接在一起,由此这些功率半导体芯片的漏极D、集电极C、阴极K会与散热器(Heatsink)21之间形成一个寄生电容(parasitic capacitance)CP。
如图3所示,中国专利申请CN104900546提出了一种IGBT功率模块封装结构,其包括一块焊接有IGBT芯片的DBC基板。其中IGBT芯片如上文所述及如图1所示,其中IGBT芯片的上表面具有门极G和发射级E,下表面具有集电极C,该IGBT芯片的集电极C是通过焊料焊接到DBC基板上表面的铜层上,该IGBT芯片的门极G通过引线连接于DBC基板上表面的铜层上以及该IGBT芯片的发射极E通过引线连接于DBC基板上表面的铜层上。DBC基板下表面的铜层是通过焊料焊接到散热基板上,DBC基板下表面的铜层与DBC基板上表面的铜层之间有一层陶瓷层。因此IGBT芯片的集电极C与散热基板(与系统保护地相连)之间,IGBT芯片的门极G与散热基板之间以及IGBT芯片的发射极E与散热基板之间均有寄生电容CP形成。
根据前文所述内容可知,上述封装技术所采用的内部结构均无法避免功率半导体芯片的一个电极或多个电极与散热基板(即电压静地点)之间寄生电容的产生,而此寄生电容的存在可能引入的共模电流将会对整个电力电子变换器产生电磁干扰(EMI)问题。尤其是对于SiC功率模块而言,虽然上述封装技术可以有效地减小功率器件内部的寄生电感参数,但是封装模块的寄生电容问题依然比较严重,其中一个重要的原因就是在SiC功率模块中为了散热的目的,必须要将SiC功率模块安装到一个散热器(或被称为“散热片”或“散热基板”,其例如可为金属材质)上,且功率模块的底面需要紧紧贴合到散热器上,而散热器的电位通常是功率变换器的保护地,这样就提供一个内部跳变电位到保护地之间的位移电流路径,由此更易产生了EMI(电磁干扰)问题。
同时,由于SiC功率模块是高速器件,对于工作在开关状态的SiC功率模块,其开关管内部会存在具有跳变电位的跳变点,且该跳变点的电压变化率dv/dt相对较大,因此EMI问题在SiC功率模块中会显得尤为突出,从而也导致其不适合应用于并联使用场合。
因此,迫切需要一种新的功率模块封装技术,可有效地减小功率模块与变换器保护地之间的寄生电容,从而抑制共模电磁干扰(EMI)的影响。
发明内容
有鉴于此,本发明的一目的在于提供一种改进的功率模块封装结构,可以有效缓解或避免现有模块封装技术中寄生电容所带来的EMI问题。
为了实现上述目的,本发明提供了一种功率模块的封装结构,其包括:散热基板;至少一第一功率器件,被配置于具有绝缘层的第一基板上,且所述第一基板被配置于所述散热基板上;至少一第二功率器件,其包括具有跳变电位的跳变电极,其中所述至少一第二功率器件被配置于具有绝缘层的至少一第二基板之上,且所述第二基板被配置于所述第一基板之上,以减小所述跳变电极与所述散热基板之间的寄生电容。
在本发明的一或多个实施例中,所述第一基板为DBC基板;所述至少一第二基板为DBC基板。
在本发明的一或多个实施例中,所述第一基板还包括二金属层,所述二金属层分别设置于所述第一基板的所述绝缘层的上表面和下表面。
在本发明的一或多个实施例中,所述至少一第二基板还包括二金属层,所述二金属层分别设置于所述至少一第二基板的所述绝缘层的上表面和下表面。
在本发明的一或多个实施例中,所述第一基板的所述绝缘层的材料为陶瓷;所述至少一第二基板的所述绝缘层的材料为陶瓷。
在本发明的一或多个实施例中,所述第一基板的所述绝缘层的材料为AlN或SiN;所述至少一第二基板的所述绝缘层的材料为AlN或SiN。
在本发明的一或多个实施例中,至少一所述第一功率器件为二极管芯片,所述二极管芯片的阳极位于所述二极管芯片的上表面,所述二极管芯片的阴极位于所述二极管芯片的下表面;或者,至少一所述第一功率器件为IGBT芯片,所述IGBT芯片的发射极和门极分别位于所述IGBT芯片的上表面,所述IGBT芯片的集电极位于所述IGBT芯片的下表面;或者,至少一所述第一功率器件为MOSFET芯片,所述MOSFET芯片的源极和栅极分别位于所述MOSFET芯片的上表面,所述MOSFET芯片的漏极位于所述MOSFET芯片的下表面。
在本发明的一或多个实施例中,至少一所述第二功率器件为二极管芯片,所述二极管芯片的阳极位于所述二极管芯片的上表面,所述二极管芯片的阴极位于所述二极管芯片的下表面;或者,至少一所述第二功率器件为IGBT芯片,所述IGBT芯片的发射极和门极分别位于所述IGBT芯片的上表面,所述IGBT芯片的集电极位于所述IGBT芯片的下表面;或者,至少一所述第二功率器件为MOSFET芯片,所述MOSFET芯片的源极和栅极分别位于所述MOSFET芯片的上表面,所述MOSFET芯片的漏极位于所述MOSFET芯片的下表面。
在本发明的一或多个实施例中,所述金属层的材料为铜。
在本发明的一或多个实施例中,所述第一基板通过焊料焊接到所述散热基板上。
为了实现上述目的,本发明还提供了一种功率模块的封装结构,其包括:散热基板;至少一第一功率器件;至少一第二功率器件,其包括具有跳变电位的跳变电极;承载基板,包括第一金属层、第二金属层、第一绝缘层、第二绝缘层和第三金属层,所述第一绝缘层被配置于所述第一金属层与所述第二金属层之间,所述第二绝缘层被配置于所述第二金属层和所述第三金属层之间;其中,所述第一金属层被配置于所述散热基板上,所述至少一第一功率器件被配置于所述第二金属层上,所述至少一第二功率器件被配置于所述第三金属层上,以减小所述跳变电极与所述散热基板之间的寄生电容。
在本发明的一或多个实施例中,所述第二金属层的部分上表面具有凸面,所述第二绝缘层被配置于所述凸面之上,所述第三金属层被配置于所述第二绝缘层之上。
在本发明的一或多个实施例中,所述承载基板是一体成型。
在本发明的一或多个实施例中,所述第一绝缘层及/或所述第二绝缘层的材料为陶瓷。
在本发明的一或多个实施例中,所述第一绝缘层及/或所述第二绝缘层的材料为AlN或SiN。
在本发明的一或多个实施例中,所述第二绝缘层、所述第三金属层以及所述凸面的投影面积相同。
本发明针对现有模块封装技术中寄生电容所带来的不利EMI影响,提出一种新的功率模块封装结构,可以降低功率模块中跳变点与电压静地点之间的寄生电容,从而极大地减小了功率模块在实际工作中的EMI噪声。
以下将以实施方式对上述的说明作详细的描述,并对本发明的技术方案提供更进一步的解释。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附附图的说明如下:
图1为常见的功率半导体的基本结构示意图;
图2为现有的功率模块封装结构示意图;
图3为中国专利申请CN104900546所提出的一种IGBT功率模块封装结构示意图;
图4为采用本发明的模块封装技术进行封装的半桥桥臂模块的电路结构示意图;
图5为对图4所示的模块进行封装得到的功率模块的封装结构示意图;
图6A示出了本发明的功率模块应用于半桥电路的电路拓扑示意图;
图6B示出了图5中当功率模块处于高频开关状态时桥臂中点N的电位发生高频跳变的等效电路图;
图7A~图7B示出了本发明的功率模块应用于常见的两电平电路拓扑结构示意图;
图8A~图8C示出了本发明的功率模块应用于常见的三电平电路拓扑结构示意图;
图9为采用本发明的模块封装技术对如图8A所示的功率模块的拓扑电路进行封装得到的封装结构示意图;
图10为采用本发明的另一模块封装技术对图4所示的模块进行封装得到的另一较佳的功率模块的封装结构。
具体实施方式
为了使本发明的叙述更加详尽与完备,可参照所附的附图及以下所述各种实施例,附图中相同的号码代表相同或相似的组件。另一方面,众所周知的组件与步骤并未描述于实施例中,以避免对本发明造成不必要的限制。此外,为简化附图起见,一些已知惯用的结构与元件在附图中将以简单示意的方式绘示。
本发明针对现有模块封装技术中的寄生电容所带来的不利EMI影响,提出了一种新的模块封装技术,可以降低模块内的跳变电位与电压静地点之间的寄生电容,从而可极大减小功率模块的在实际工作中的EMI噪声。
本发明提供了一种功率模块的封装结构,其可包括散热基板、至少一第一功率器件以及至少一第二功率器件。其中,所述至少一第一功率器件是被配置于具有绝缘层的第一基板上,且所述第一基板是被配置于所述散热基板上。所述至少一第二功率器件包括具有跳变电位的跳变电极,其中所述至少一第二功率器件是被配置于具有绝缘层的至少一第二基板之上,且所述第二基板是被配置于所述第一基板之上,以减小所述跳变电极与所述散热基板之间的寄生电容。
在本发明中,所谓的“跳变电位”一般是指相对于一参考点(例如电压静地点)具有较大的高低电平跳变(即例如电压变化率dv/dt大于10V/μs)。相对地,相对于该参考点(例如电压静地点)具有固定电位或具有较小的高低电平跳变(即例如电压变化率dv/dt小于2V/μs,可视为“基本无跳变”)可被称为“非跳变电位”(或是被称为“电压静地点”)。当然,可以理解的是,上述电压变换率dv/dt的临界值,例如2V/μs和10V/μs,也可以在一定范围内波动,例如百分之十、或者百分之五等,这些并不作为对本发明的限制。
以一个最简单的半桥桥臂模块为例,如图4所示,其结构可包括:由功率器件Q1和Q2(例如为MOSFET芯片)构成了一个半桥桥臂,其中功率器件Q2的漏极为桥臂中点Nt。因桥臂上的功率器件Q1和Q2切换,桥臂中点Nt的电位会存在跳变,故功率器件Q2的漏极(即桥臂中点Nt)为跳变点,即功率器件Q2的漏极为具有跳变电位的跳变电极;而功率器件Q1的漏极由于直接接到了输入端Ns(例如,电容的正极),可认为是电压静地点。
因此,在进行封装时,如图5所示,本发明是将功率器件Q1的下表面(具有漏极D)配置于具有绝缘层的第一基板S1上,亦即,功率器件Q1的下表面焊接于第一基板S1;并将具有跳变电极(例如漏极D)的功率器件Q2配置于具有绝缘层的第二基板S2上,亦即,功率器件Q2的下表面(具有漏极D)焊接于第二基板S2;该第二基板S2被配置于该第一基板S1之上,亦即,该第二基板S2焊接于该第一基板S1,而该第一基板S1是被配置于一散热基板SH上,亦即,该第一基板S1是焊接于散热基板SH,该散热基板SH为电压静地点。其中,第一基板S1使功率器件Q1的下表面与该散热基板SH(电压静地点)之间形成寄生电容,但由于功率器件Q1的下表面为漏极,其电位相对稳定,故由此寄生电容引入的共模电流将大大降低。功率器件Q2的下表面通过第一基板S1和第二基板S2连接散热基板SH,能够减小电压跳变点(例如功率器件Q2的漏极)与电压静地点(例如散热基板SH)的寄生电容,改善功率模块的EMC性能。
如图6A所示,其示出了本发明的功率模块在半桥电路中的应用。其中,图6A所示为一个半桥电路拓扑结构,其输出带有一级共模电感LCM,同时输出正端Vo+与输出负端Vo-均通过电容Cy1~Cy4与大地连接,并在输出端接入线性阻抗网络(LISN)用以测量整个装置的传导干扰。图6A中的电容Cp1、Cp2即为功率模块封装引入产生的寄生电容。当功率模块处于高频开关状态时,桥臂中点N的电位会发生高频跳变,即该桥臂中点N为跳变点。此时电路可等效为如图6B所示,其中寄生电容Cp1、Cp2形成一个共模电流回路(如图中箭头所示),这部分共模电流会经过测试EMI用的LISN的电阻。采用本发明的封装方法封装的功率模块,其寄生电容Cp1、Cp2明显较采用传统封装方法封装的功率模块要小,也即,其寄生电容Cp1、Cp2对EMI产生的不利影响明显比传统方法要小得多。换句话说,采用本发明的封装方法封装的功率模块可以有效地缓解功率模块所带来的EMI问题。
在上述实施例中,该第一基板S1及该第二基板S2可为DBC基板,即中间为绝缘层而上下表面为铜层的结构。该第一基板S1可通过焊料焊接到该散热基板SH上。该第一基板S1及该第二基板S2的绝缘层的材料可为陶瓷,其例如可为具有高导热性能的AlN或SiN,可使功率模块具有较好的散热效果。但是,可以理解的是,该第一基板S1及该第二基板S2并不局限于DBC基板结构,其也可以为其它结构,例如,该第一基板S1可包括二金属层M11和M12,所述二金属层M11和M12分别设置于该第一基板S1的绝缘层I1的上表面和下表面。例如,该第二基板S2也可包括二金属层M21和M22,所述二金属层M21和M22分别设置于该第二基板S2的绝缘层I2的上表面和下表面。其中,这些金属层的材料可为铜或其它金属材料。并且,该第一基板S1也可通过其它方式连接到该散热基板SH上。这些均不作为对本发明的限制。
在图4和图5所示的实施例中,该功率器件Q1和Q2是为MOSFET芯片。但可以理解的是,在本发明的其它实施例中,该功率器件Q1及/或该功率器件Q2也可以为二极管芯片或IGBT芯片,且这些功率器件所构成的电路结构也并不局限于如图4所示的电路结构,其也可以构成如图7A~7B、8A~8C所示的电路拓扑结构,或者是构成其它电路拓扑结构,这些都并不作为对本发明的限制。例如,图7A~图7B即示出了本发明的功率模块应用于常见的两电平电路拓扑结构,图8A~图8C则示出了本发明的功率模块应用于常见的三电平电路拓扑结构,其中,这些图中的圆圈所圈出的部分即为可能通过功率模块的寄生电容对系统EMI造成影响的功率器件,因此,在对如图7A~7B、8A~8C所示的电路拓扑结构中的功率器件采用本发明的封装方法进行封装时,可以将这些图中的圆圈所圈出的部分所对应的功率器件设置在第二基板S2上,而其它功率器件设置在第一基板S1上,该第一基板S1则连接到散热基板SH上,如此即可减小拓扑结构中电压跳变点与电压静地点之间的寄生电容,从而改善整个系统的EMC性能。
并且,当该功率器件为二极管芯片时,所述二极管芯片的阳极A可以是位于所述二极管芯片的上表面,所述二极管芯片的阴极K可以是位于所述二极管芯片的下表面。当该功率器件为IGBT芯片时,所述IGBT芯片的发射极E和门极G可以是分别位于所述IGBT芯片的上表面,所述IGBT芯片的集电极C可以是位于所述IGBT芯片的下表面。当该功率器件为MOSFET芯片时,所述MOSFET芯片的源极S和栅极G可以是分别位于所述MOSFET芯片的上表面,所述MOSFET芯片的漏极D可以是位于所述MOSFET芯片的下表面。
由此可见,本发明的功率模块封装结构通过将具有跳变电位的跳变电极(例如漏极D、阴极K、集电极C等)的芯片置于一个额外的基板(即第二基板)的上表面,可保证第一基板S1的上层金属层为电压静地点(即例如图5中的功率器件Q1的漏极为电压静地点),虽然仍无法避免第一基板S1的上层金属层与散热基板SH(电压静地点)之间的寄生电容,但由于该第一基板S1的上层金属层不再为电位跳变点,因此寄生电容带来的共模电流和共模干扰效应将大大降低。同时,与利用现有的模块封装结构相比,本发明的封装结构中功率器件Q2是通过两个基板S1、S2连接至散热基板SH,且两个基板S1、S2内部的绝缘层可以采用高导热的陶瓷如AlN、SiN,故可获得更好的散热效果。
如图9所示,其示出了利用本发明的模块封装技术对如图8A所示的功率模块的拓扑电路进行封装得到的封装结构,其中是将具有跳变电位电极的功率器件(例如二极管芯片D1、IGBT芯片Q2、IGBT芯片Q3和IGBT芯片Q4)配置于第二基板S2之上,将具有稳定电位的功率器件(例如二极管芯片D2和IGBT芯片Q1)配置于第一基板S1之上,且第二基板S2是被配置于第一基板S1之上,第一基板S1是被配置于散热基板SH之上,如此即可保证第一基板S1的上层金属层为电压静地点,即不为电位跳变点,因此将大大降低第一基板S1的上层的金属层与散热基板SH(电压静地点)之间的寄生电容所带来的共模电流和共模干扰效应,进而改善整个系统的EMC性能。
较佳地,本发明还提供了另一种功率模块的封装结构,其包括散热基板、至少一第一功率器件、至少一第二功率器件、以及承载基板。其中,所述至少一第二功率器件可包括具有跳变电位的跳变电极。所述承载基板可包括第一金属层、第二金属层、第一绝缘层、第二绝缘层和第三金属层,其中,所述第一绝缘层可被配置于所述第一金属层与所述第二金属层之间,所述第二绝缘层可被配置于所述第二金属层和所述第三金属层之间。并且,所述第一金属层可被配置于所述散热基板上,所述至少一第一功率器件可被配置于所述第二金属层上,所述至少一第二功率器件可被配置于所述第三金属层上,从而可以减小所述跳变电极与所述散热基板之间的寄生电容。
如图10所示,其示出了采用本发明的另一模块封装技术对图4所示的模块进行封装得到的另一较佳的功率模块的封装结构,其中,与图5所示的实施例不同的是,所述承载基板SB是一体成型,其包括第一金属层M1、第二金属层M2、第一绝缘层I1、第二绝缘层I2和第三金属层M3,且所述第二金属层M2的部分上表面形成有凸面M20,所述第二绝缘层I2是被配置于所述凸面M20之上,所述第三金属层M3是被配置于所述第二绝缘层I2之上。较佳的,所述第二绝缘层I2、所述第三金属层M3以及所述凸面M20的投影面积相同。较佳的,所述第一绝缘层I1及/或所述第二绝缘层I2的材料可为陶瓷,例如可为AlN或SiN。
本发明的功率模块的封装结构,可以有效降低功率模块内跳变电位与电压静地点之间的寄生电容,从而极大地减小功率模块在实际工作中的EMI噪声,故可在大功率电力电子装置中使用本发明的集成功率模块以提高功率密度。
虽然本发明已以实施方式揭露如上,然其并非用以限定本发明,任何熟悉此技艺者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当视所附的权利要求书所界定的范围为准。
Claims (9)
1.一种功率模块的封装结构,其特征在于,包括:
散热基板;
至少一第一功率器件;
至少一第二功率器件,其包括具有跳变电位的跳变电极;
承载基板,包括第一金属层、第二金属层、第一绝缘层、第二绝缘层和第三金属层,所述第一绝缘层被配置于所述第一金属层与所述第二金属层之间,所述第二绝缘层被配置于所述第二金属层和所述第三金属层之间;
其中,所述第一金属层被配置于所述散热基板上,所述至少一第一功率器件被配置于所述第二金属层上,所述至少一第二功率器件被配置于所述第三金属层上,以减小所述跳变电极与所述散热基板之间的寄生电容;
其中,所述第二金属层的部分上表面具有凸面,所述第二绝缘层被配置于所述凸面之上,所述第三金属层被配置于所述第二绝缘层之上。
2.根据权利要求1所述的功率模块的封装结构,其特征在于,至少一所述第一功率器件为二极管芯片,所述二极管芯片的阳极位于所述二极管芯片的上表面,所述二极管芯片的阴极位于所述二极管芯片的下表面;
或者,至少一所述第一功率器件为IGBT芯片,所述IGBT芯片的发射极和门极分别位于所述IGBT芯片的上表面,所述IGBT芯片的集电极位于所述IGBT芯片的下表面;
或者,至少一所述第一功率器件为MOSFET芯片,所述MOSFET芯片的源极和栅极分别位于所述MOSFET芯片的上表面,所述MOSFET芯片的漏极位于所述MOSFET芯片的下表面。
3.根据权利要求1所述的功率模块的封装结构,其特征在于,至少一所述第二功率器件为二极管芯片,所述二极管芯片的阳极位于所述二极管芯片的上表面,所述二极管芯片的阴极位于所述二极管芯片的下表面;
或者,至少一所述第二功率器件为IGBT芯片,所述IGBT芯片的发射极和门极分别位于所述IGBT芯片的上表面,所述IGBT芯片的集电极位于所述IGBT芯片的下表面;
或者,至少一所述第二功率器件为MOSFET芯片,所述MOSFET芯片的源极和栅极分别位于所述MOSFET芯片的上表面,所述MOSFET芯片的漏极位于所述MOSFET芯片的下表面。
4.根据权利要求1所述的功率模块的封装结构,其特征在于,所述第一金属层、所述第二金属层和所述第三金属层的材料均为铜。
5.根据权利要求1所述的功率模块的封装结构,其特征在于,所述承载基板通过焊料焊接到所述散热基板上。
6.根据权利要求1所述的功率模块的封装结构,其特征在于,所述承载基板是一体成型。
7.根据权利要求1所述的功率模块的封装结构,其特征在于,所述第一绝缘层及/或所述第二绝缘层的材料为陶瓷。
8.根据权利要求1所述的功率模块的封装结构,其特征在于,所述第一绝缘层及/或所述第二绝缘层的材料为AlN或SiN。
9.根据权利要求1所述的功率模块的封装结构,其特征在于,所述第二绝缘层、所述第三金属层以及所述凸面的投影面积相同。
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