JP4257526B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4257526B2 JP4257526B2 JP2004163010A JP2004163010A JP4257526B2 JP 4257526 B2 JP4257526 B2 JP 4257526B2 JP 2004163010 A JP2004163010 A JP 2004163010A JP 2004163010 A JP2004163010 A JP 2004163010A JP 4257526 B2 JP4257526 B2 JP 4257526B2
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- external terminal
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2924/01004—Beryllium [Be]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
前記半導体基板に設けられた、複数層の導電体及び1層又は複数層の絶縁体の積層体と、
前記積層体上に設けられてなる外部端子と、
を含み、
前記外部端子の直下で1つの前記絶縁体の上面及び下面にそれぞれ接触するとともに前記外部端子の直下で相互にオーバーラップする部分を有する一対の前記導電体は、全て、電気的に接続されてなる。本発明によれば、一対の導電体のオーバーラップする部分が導通しても、元々、これらは電気的に接続されているので支障がない。
(2)本発明に係る半導体装置は、集積回路が作り込まれてなる半導体基板と、
前記半導体基板に設けられた、複数層の導電体及び1層又は複数層の絶縁体の積層体と、
前記積層体上に設けられてなる外部端子と、
を含み、
前記外部端子の直下で1つの前記絶縁体の上面及び下面にそれぞれ接触するとともに電気的に切断されてなる一対の前記導電体は、全て、前記外部端子の直下でオーバーラップしないように配置されてなる。本発明によれば、一対の導電体は、オーバーラップしないように配置されているので導通しにくくなっている。
(3)この半導体装置において、
前記集積回路は、前記一対の導電体を電気的に切断するスイッチング素子を含み、
前記スイッチング素子は、前記外部端子の直下に一部または全体が含まれるように配置されていてもよい。
(4)この半導体装置において、
前記外部端子は、最上層の前記導電体上に設けられて電気的に接続され、
前記最上層の前記導電体は、前記外部端子の前記積層体への投影面よりも小さく形成されていてもよい。
Claims (4)
- 半導体基板と、
前記半導体基板上に設けられ、異なる電位となる一対の導電体を含む複数の導電体と、
1層又は複数層の絶縁体と、を含み、
前記複数の導電体と前記絶縁体とを含む積層体上に設けられた外部端子の前記積層体への投影面内で、
前記一対の導電体は前記絶縁体の上面及び下面にそれぞれ接触し、
前記外部端子の前記積層体への投影面内で、
前記複数の導電体のうち、前記異なる電位となる一対の導電体は、すべて相互にオーバーラップしないように配置されてなる半導体装置。 - 請求項1に記載の半導体装置において、
パッシベーション膜をさらに含み、
前記パッシベーション膜は、最上層の前記導電体をその一部を除いて覆うこと、
を特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記外部端子は、最上層の前記導電体上に設けられていること、
を特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記外部端子は、前記パッシベーション膜上にも載るように形成されていること、
を特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004163010A JP4257526B2 (ja) | 2004-06-01 | 2004-06-01 | 半導体装置 |
CNB200510069092XA CN100431146C (zh) | 2004-06-01 | 2005-05-10 | 半导体装置 |
US11/141,270 US20050263889A1 (en) | 2004-06-01 | 2005-05-31 | Semiconductor device |
US11/945,498 US7936071B2 (en) | 2004-06-01 | 2007-11-27 | Semiconductor device having a specified terminal layout pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004163010A JP4257526B2 (ja) | 2004-06-01 | 2004-06-01 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005347381A JP2005347381A (ja) | 2005-12-15 |
JP4257526B2 true JP4257526B2 (ja) | 2009-04-22 |
Family
ID=35424277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004163010A Expired - Fee Related JP4257526B2 (ja) | 2004-06-01 | 2004-06-01 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20050263889A1 (ja) |
JP (1) | JP4257526B2 (ja) |
CN (1) | CN100431146C (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4851255B2 (ja) * | 2006-07-14 | 2012-01-11 | 株式会社 日立ディスプレイズ | 表示装置 |
US10481709B2 (en) * | 2016-11-03 | 2019-11-19 | Jui-Jen Yueh | Electronic device |
CN117949516A (zh) * | 2024-03-22 | 2024-04-30 | 山西天和盛环境检测股份有限公司 | 一种水体检测装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5106461A (en) * | 1989-04-04 | 1992-04-21 | Massachusetts Institute Of Technology | High-density, multi-level interconnects, flex circuits, and tape for tab |
EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
JPH09283525A (ja) * | 1996-04-17 | 1997-10-31 | Sanyo Electric Co Ltd | 半導体装置 |
US6316801B1 (en) * | 1998-03-04 | 2001-11-13 | Nec Corporation | Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same |
JP2001110810A (ja) * | 1999-10-06 | 2001-04-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2001196413A (ja) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置、該半導体装置の製造方法、cmp装置、及びcmp方法 |
JP2002198374A (ja) | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
KR100390905B1 (ko) * | 2001-05-10 | 2003-07-12 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 센스앰프 레이아웃 구조 |
DE10139956A1 (de) | 2001-08-21 | 2003-03-13 | Koninkl Philips Electronics Nv | ESD Schutz für CMOS-Ausgangsstufe |
JP2004153003A (ja) * | 2002-10-30 | 2004-05-27 | Sanyo Electric Co Ltd | 不揮発性半導体記憶装置 |
-
2004
- 2004-06-01 JP JP2004163010A patent/JP4257526B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-10 CN CNB200510069092XA patent/CN100431146C/zh not_active Expired - Fee Related
- 2005-05-31 US US11/141,270 patent/US20050263889A1/en not_active Abandoned
-
2007
- 2007-11-27 US US11/945,498 patent/US7936071B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100431146C (zh) | 2008-11-05 |
US20050263889A1 (en) | 2005-12-01 |
JP2005347381A (ja) | 2005-12-15 |
US7936071B2 (en) | 2011-05-03 |
US20080088024A1 (en) | 2008-04-17 |
CN1705116A (zh) | 2005-12-07 |
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