KR920015494A - 수지 봉지형 반도체 집적 회로 - Google Patents

수지 봉지형 반도체 집적 회로 Download PDF

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Publication number
KR920015494A
KR920015494A KR1019920000832A KR920000832A KR920015494A KR 920015494 A KR920015494 A KR 920015494A KR 1019920000832 A KR1019920000832 A KR 1019920000832A KR 920000832 A KR920000832 A KR 920000832A KR 920015494 A KR920015494 A KR 920015494A
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KR
South Korea
Prior art keywords
semiconductor integrated
encapsulated semiconductor
wiring layer
integrated circuit
interlayer insulating
Prior art date
Application number
KR1019920000832A
Other languages
English (en)
Other versions
KR950012657B1 (en
Inventor
쇼조 니시모또
Original Assignee
세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세끼모또 다다히로, 니뽄 덴끼 가부시끼가이샤 filed Critical 세끼모또 다다히로
Publication of KR920015494A publication Critical patent/KR920015494A/ko
Application granted granted Critical
Publication of KR950012657B1 publication Critical patent/KR950012657B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

내용 없음

Description

수지 봉지형 반도체 집적 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도는 본 발명의 한 실시예를 개략적으로 나타내는 평면도, 제1B도는 제 1A도의 X-X선에 있어서 확대단면도, 제2도는 배선층이 슬라이드를 일으키는 폭의 상한과 반도체 칩의 한 모서리에서의 거리 관계를 나타내는 그래프, 제3도는 본 발명의 한 실시예의 변형을 개략적으로 나타내는 평면도이다.

Claims (3)

  1. 층간절연막을 가지는 방형상의 반도체칩과, 상기 층간절연막에 선택적으로 피착되고, 상기 반도체 칩의 한 모서리에서의 거리에 따라 합계폭이 불연속적으로 끼우게 되는 배선층 및 상기 한 모서리에서의 거리에 따라 상기 배선층을 폭방향으로 복수의 부분에 구절하는 수단에서 되는 전원 배선 또는 접지 배선과, 상기 배선층이 설치된 층간절연막을 피복하는 패시베이션막을 가지는 수지 봉지형 반도체 집적 회로.
  2. 제1항에 있어서, 상기 배선층을 구절하는 수단은 폭이상기 패시 베이션 막두께의 적어도 2배 슬릿인 수지 봉지형 반도체 집적 회로.
  3. 제1항에 있어서, 상기 패시베이션막을 실리콘 옥시나이드라이드막 또는 질화 실리콘막인 수지 봉지형 반도체 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR92000832A 1991-01-22 1992-01-22 Resin sealed semiconductor integrated circuit KR950012657B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP547091 1991-01-22

Publications (2)

Publication Number Publication Date
KR920015494A true KR920015494A (ko) 1992-08-27
KR950012657B1 KR950012657B1 (en) 1995-10-19

Family

ID=11612132

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92000832A KR950012657B1 (en) 1991-01-22 1992-01-22 Resin sealed semiconductor integrated circuit

Country Status (4)

Country Link
US (1) US5289036A (ko)
EP (2) EP1587143A1 (ko)
KR (1) KR950012657B1 (ko)
DE (1) DE69233550T2 (ko)

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KR100353091B1 (ko) * 1999-08-30 2002-09-16 넥스콘 테크놀러지 주식회사 무광원 스케닝방법 및 그 장치

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JP2755239B2 (ja) * 1995-11-25 1998-05-20 日本電気株式会社 半導体装置用パッケージ
JP3500308B2 (ja) 1997-08-13 2004-02-23 インターナショナル・ビジネス・マシーンズ・コーポレーション 集積回路
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* Cited by examiner, † Cited by third party
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KR100353091B1 (ko) * 1999-08-30 2002-09-16 넥스콘 테크놀러지 주식회사 무광원 스케닝방법 및 그 장치

Also Published As

Publication number Publication date
KR950012657B1 (en) 1995-10-19
EP1587143A1 (en) 2005-10-19
EP0499063A3 (en) 1992-10-14
DE69233550D1 (de) 2006-02-09
DE69233550T2 (de) 2006-06-22
US5289036A (en) 1994-02-22
EP0499063A2 (en) 1992-08-19
EP0499063B1 (en) 2005-09-28

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