KR900004022A - 불휘발성 반도체 기억장치 - Google Patents
불휘발성 반도체 기억장치 Download PDFInfo
- Publication number
- KR900004022A KR900004022A KR1019890012171A KR890012171A KR900004022A KR 900004022 A KR900004022 A KR 900004022A KR 1019890012171 A KR1019890012171 A KR 1019890012171A KR 890012171 A KR890012171 A KR 890012171A KR 900004022 A KR900004022 A KR 900004022A
- Authority
- KR
- South Korea
- Prior art keywords
- conductor
- insulating film
- main surface
- semiconductor memory
- semiconductor substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000004020 conductor Substances 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 이 발명의 한 실시예에 의한 불휘발성 반도체기억장치의 평면도.
제 2 도는 제 1도의 Ⅱ-Ⅱ단면도.
제 3 도는 제 1도의 Ⅲ-Ⅲ단면도.
Claims (1)
- 공통의 소스선에 접속된 복수의 메모리 트랜지스터를 가지는 불휘발성반도체 기억장치에 있어서 상기 메모리 트랜지스터는 공통의 주면을 가지는 제 1도전형의 반도체기판에 형성되고 상기 메모리트랜지스터의 각각은 상기 반도체기판의 주면에 소정간격으로 형성되고 그 사이의 상기 반도체기판의 주면의 영역을 제 1 및 제 2의 채널영역으로서 규정하는 제 1도전형과 반대 형식의 제 2도전형의 제1, 제2 및 제3의 불순물영역과 상기 제 2의 채널영역상에 절연막을 거쳐서 형성된 제 1의 도전체와 상기 제1의 채널영역상의 절연막을 거쳐서 형성되고 다시 상기 제 1의 도전체상에 절연막을 거쳐서 형성되어 전하의 축적을 행할 수 있는 제 2의 도전체와 상기 제 2의 도전체상에 절연막을 거쳐서 형성되고 상기 제 1의 도전체와 전기적으로 접속되는 제 3의 도전체를 구비하고 상기 제 3의 불순물영역은 상기 공통의 소스선에 접속되는 불휘발성반도체기억장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-213202 | 1988-08-26 | ||
JP63213202A JP2547622B2 (ja) | 1988-08-26 | 1988-08-26 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900004022A true KR900004022A (ko) | 1990-03-27 |
KR930004986B1 KR930004986B1 (ko) | 1993-06-11 |
Family
ID=16635226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890012171A KR930004986B1 (ko) | 1988-08-26 | 1989-08-25 | 불휘발성 반도체 기억장치 |
Country Status (3)
Country | Link |
---|---|
US (2) | US4989054A (ko) |
JP (1) | JP2547622B2 (ko) |
KR (1) | KR930004986B1 (ko) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5223731A (en) * | 1988-06-30 | 1993-06-29 | Goldstar Electron Co., Ltd. | EPROM cell using trench isolation to provide leak current immunity |
JP2529885B2 (ja) * | 1989-03-10 | 1996-09-04 | 工業技術院長 | 半導体メモリ及びその動作方法 |
JPH03245575A (ja) * | 1990-02-22 | 1991-11-01 | Mitsubishi Electric Corp | 半導体記憶装置及びその製造方法 |
JP3124334B2 (ja) * | 1991-10-03 | 2001-01-15 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
US5291439A (en) * | 1991-09-12 | 1994-03-01 | International Business Machines Corporation | Semiconductor memory cell and memory array with inversion layer |
US7071060B1 (en) | 1996-02-28 | 2006-07-04 | Sandisk Corporation | EEPROM with split gate source side infection with sidewall spacers |
US5262353A (en) * | 1992-02-03 | 1993-11-16 | Motorola, Inc. | Process for forming a structure which electrically shields conductors |
US5723888A (en) * | 1993-05-17 | 1998-03-03 | Yu; Shih-Chiang | Non-volatile semiconductor memory device |
US5436480A (en) * | 1993-02-22 | 1995-07-25 | Yu; Shih-Chiang | Integrated circuit interconnection programmable and erasable by a plurality of intersecting control traces |
US5427963A (en) * | 1993-12-10 | 1995-06-27 | Advanced Micro Devices, Inc. | Method of making a MOS device with drain side channel implant |
US5445983A (en) * | 1994-10-11 | 1995-08-29 | United Microelectronics Corporation | Method of manufacturing EEPROM memory device with a select gate |
US5482881A (en) * | 1995-03-14 | 1996-01-09 | Advanced Micro Devices, Inc. | Method of making flash EEPROM memory with reduced column leakage current |
JP3366173B2 (ja) * | 1995-07-31 | 2003-01-14 | シャープ株式会社 | 不揮発性半導体メモリの製造方法 |
DE19534780A1 (de) * | 1995-09-19 | 1997-03-20 | Siemens Ag | Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat |
DE19643185C2 (de) * | 1996-10-18 | 1998-09-10 | Siemens Ag | Dual-Gate-Speicherzelle und Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle |
US6835979B1 (en) * | 1997-04-11 | 2004-12-28 | Altera Corporation | Nonvolatle memory |
US5867429A (en) * | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
US6168995B1 (en) * | 1999-01-12 | 2001-01-02 | Lucent Technologies Inc. | Method of fabricating a split gate memory cell |
KR100701716B1 (ko) * | 1999-07-29 | 2007-03-29 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 비휘발성 반도체 메모리 디바이스 |
US6798012B1 (en) * | 1999-12-10 | 2004-09-28 | Yueh Yale Ma | Dual-bit double-polysilicon source-side injection flash EEPROM cell |
JP2001176990A (ja) | 1999-12-21 | 2001-06-29 | Nec Corp | 半導体装置とその製造方法 |
JP2001308205A (ja) * | 2000-04-19 | 2001-11-02 | Nec Corp | 不揮発性半導体記憶装置及びその製造方法 |
KR100355662B1 (ko) * | 2001-08-25 | 2002-10-11 | 최웅림 | 반도체 비휘발성 메모리 및 어레이 그리고 그것의 동작 방법 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5780779A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor non-volatile memory |
JPS5791561A (en) * | 1980-11-28 | 1982-06-07 | Fujitsu Ltd | Semiconductor non-volatile memory device and manufacture therefor |
US4513397A (en) * | 1982-12-10 | 1985-04-23 | Rca Corporation | Electrically alterable, nonvolatile floating gate memory device |
JPS59500343A (ja) * | 1982-03-09 | 1984-03-01 | ア−ルシ−エ− コ−ポレ−シヨン | 電気的に改変可能の不揮発性浮動ゲ−ト記憶装置 |
JPS58166773A (ja) * | 1982-03-09 | 1983-10-01 | ア−ルシ−エ− コ−ポレ−ション | 浮動ゲ−ト・メモリ装置 |
US4455742A (en) * | 1982-06-07 | 1984-06-26 | Westinghouse Electric Corp. | Method of making self-aligned memory MNOS-transistor |
JPS6288369A (ja) * | 1985-10-15 | 1987-04-22 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0640586B2 (ja) * | 1986-12-05 | 1994-05-25 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
JPS63199464A (ja) * | 1987-02-16 | 1988-08-17 | Nippon Denso Co Ltd | 不揮発性半導体記憶装置 |
JPH07120719B2 (ja) * | 1987-12-02 | 1995-12-20 | 三菱電機株式会社 | 半導体記憶装置 |
JPH07101713B2 (ja) * | 1988-06-07 | 1995-11-01 | 三菱電機株式会社 | 半導体記憶装置の製造方法 |
JPH0728030B2 (ja) * | 1988-09-07 | 1995-03-29 | 三菱電機株式会社 | 電荷結合素子 |
FR2642900B1 (fr) * | 1989-01-17 | 1991-05-10 | Sgs Thomson Microelectronics | Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques |
-
1988
- 1988-08-26 JP JP63213202A patent/JP2547622B2/ja not_active Expired - Lifetime
-
1989
- 1989-04-17 US US07/339,546 patent/US4989054A/en not_active Expired - Fee Related
- 1989-08-25 KR KR1019890012171A patent/KR930004986B1/ko not_active IP Right Cessation
-
1991
- 1991-01-04 US US07/637,423 patent/US5100818A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR930004986B1 (ko) | 1993-06-11 |
JP2547622B2 (ja) | 1996-10-23 |
JPH0262074A (ja) | 1990-03-01 |
US4989054A (en) | 1991-01-29 |
US5100818A (en) | 1992-03-31 |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19980526 Year of fee payment: 6 |
|
LAPS | Lapse due to unpaid annual fee |