KR890017769A - 반도체 장치 및 제조방법 - Google Patents

반도체 장치 및 제조방법 Download PDF

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Publication number
KR890017769A
KR890017769A KR1019890006700A KR890006700A KR890017769A KR 890017769 A KR890017769 A KR 890017769A KR 1019890006700 A KR1019890006700 A KR 1019890006700A KR 890006700 A KR890006700 A KR 890006700A KR 890017769 A KR890017769 A KR 890017769A
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region
voltage transistor
semiconductor substrate
high breakdown
breakdown voltage
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KR1019890006700A
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KR950014807B1 (ko
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유따까 마루오
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야마무라 가쯔미
세이꼬 엡슨 가부시끼 가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 장치 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 이 발명의 한 실시예를 표시한 고내압용 CMOS트랜스터의 구성을 설명하는 요부 단면 모식도, 제2A도 내지 제2C도는 이 발명의 다른 실시예를 표시한 고내압 n채널 트린지스터를 사용한 EEPROM메모리 셀부분의 트랜지스터의 모식 설명도.

Claims (4)

  1. 제 1 도 전형의 제 1 고내압 트랜지스터에 의하여 구성된 복수의 메모리 트랜지스터 및 제 1 도 전형의 제 2 고내압 트랜지스터에 의하여 구성되는 복수의 선택용 트랜지스터로 된 메모리 셀 영역과, 제 2 도 전형의 제 3 고내압 트랜지스터에 의하여 일부가 구성되는 주변 회로영역을 보유하는 반도체 장치에 있어서, 상기 제 1 고내압 트랜지스터 및 상기 제 2 고내압 트랜지스터는 제 1 게이트 전극 단부하의 기판에 인접한 기판중에 표면이 대략 평탄하고, 저농도의 불순물로된 제 1 오프셋 영역을 보유한 구조로 되어 있으며, 상기 제 3 고내압 트랜지스터는, 제 2 게이트 전극횡에 일부가 상기 기판중에 배치된 상태로 설치된 절연막과, 상기 두꺼운 절연막하의 상기 가판중에 설치된 저농도의 불순물 영역으로된 제 2 오프셋 영역을 보유한 구조로 되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제 1 항에 있어서, 상기 제 1 고내압 트랜지스터 및 상기 제 2 고내압 트랜지스터는 공통으로 n채널형의 고내압 트랜지스터이며, 상기 제 3 고내압 트랜지스터는 p채널형 고내압 트랜지스터인 것을 특징으로 하는 반도체 장치.
  3. 제 1 항에 있어서, 상기 제 1 오프셋 영역은 n형 불순물 영역이며, 상기 제 2 오프셋 영역은 p형 불순물 영역인 것을 특징으로 하는 반도체 장치.
  4. 제 1 게이트 전극단부하의 반도체 기판에 인접한 상기 반도체 기판중에 표면이 대략 평탄하고 저농도의 불순물 영역으로된 제 1 오프셋 영역을 보유하는 제 1 도 전형의 제 1 고내압 트랜지스터, 제 2 게이트 전극횡에 일부가 상기 반도체 기판중에 매치되어서 설치된 두꺼운 절연막 및 상기 두꺼운 절연막하의 상기 반도체 기판중에 설치된 저농도의 불순물 영역으로된 제 2 오프셋 영역을 보유하는 제 2 도전형의 제 2 고내압 트랜지스터를 구비하는 반도체 장치의 제조 방법에 있어서, 상기 반도체 기판의 제 1 도전형 영역상에 제 2 도전 형의 상기 제 2 오프셋 영역을 형성하고, 또 상기 반도체 기판의 제 2 도전형 영역상에 제 2 도전형의 스토퍼 영역을 형성하는 공정과, 상기 스토퍼 영역상에 일부가 상기 반도체 기판에 매치된 두꺼운 절연막을 형성하는 공정과, 상기 반도체 기판의 제 2 도전형 영역위쪽에 상기 제 1 게이트 전극을 형성하고, 또, 상기 반도체 기판의 상기 제 1 도전형 영역위쪽에 상기 제 2 게이트 전극을 형성하는 공정과, 상기 제 1 게이트 전극의 양측의 상기 반도체 기판에 제 1 도전형의 제 1 오프셋 영영을 형성하는 공정과,상기 제 1 오프셋 영역에 인접하여 제 1 도전형의 제 1 소스, 드레인 영역을 형성하는 공정과, 상기 두꺼운 절연막하의 상기 제 2 오프셋 영역에 인접하여 제 2 도전형의 제 2 소스, 드레인 영역을 형성하는 공정을 보유하는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890006700A 1988-05-25 1989-05-19 반도체 장치 및 제조 방법 KR950014807B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP125634 1988-05-25
JP63125634A JP2705106B2 (ja) 1988-05-25 1988-05-25 半導体装置の製造方法

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KR890017769A true KR890017769A (ko) 1989-12-18
KR950014807B1 KR950014807B1 (ko) 1995-12-15

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US (1) US5181090A (ko)
EP (1) EP0355951B1 (ko)
JP (1) JP2705106B2 (ko)
KR (1) KR950014807B1 (ko)
DE (1) DE68923742T2 (ko)

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KR20100020928A (ko) * 2008-08-13 2010-02-23 세이코 인스트루 가부시키가이샤 반도체 장치 및 그 제조 방법

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JP2000311957A (ja) * 1999-04-27 2000-11-07 Seiko Instruments Inc 半導体装置
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JP4471815B2 (ja) * 2004-11-05 2010-06-02 日本テキサス・インスツルメンツ株式会社 半導体装置およびその製造方法
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JP6077291B2 (ja) * 2012-12-10 2017-02-08 エスアイアイ・セミコンダクタ株式会社 不揮発性メモリ回路
CN113540252B (zh) * 2021-09-16 2022-01-28 晶芯成(北京)科技有限公司 半导体器件及制造方法
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Also Published As

Publication number Publication date
EP0355951A2 (en) 1990-02-28
EP0355951A3 (en) 1992-02-19
DE68923742D1 (de) 1995-09-14
DE68923742T2 (de) 1996-01-18
KR950014807B1 (ko) 1995-12-15
JP2705106B2 (ja) 1998-01-26
US5181090A (en) 1993-01-19
JPH01296661A (ja) 1989-11-30
EP0355951B1 (en) 1995-08-09

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