KR900002462A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR900002462A
KR900002462A KR1019890009587A KR890009587A KR900002462A KR 900002462 A KR900002462 A KR 900002462A KR 1019890009587 A KR1019890009587 A KR 1019890009587A KR 890009587 A KR890009587 A KR 890009587A KR 900002462 A KR900002462 A KR 900002462A
Authority
KR
South Korea
Prior art keywords
planar pattern
impurity diffusion
diffusion region
region
semiconductor device
Prior art date
Application number
KR1019890009587A
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English (en)
Other versions
KR920010673B1 (ko
Inventor
히데미 이시우치
도시하루 와타나베
기누요 다나카
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900002462A publication Critical patent/KR900002462A/ko
Application granted granted Critical
Publication of KR920010673B1 publication Critical patent/KR920010673B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

내용 없음.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(a)도는 본 발명의 1실시예에 따른 반도체장치의 평면패턴을 나타낸 도면.
제1(b)도는 제1a도의 B-B선에 따른 단면도.
제2(a)도는 본 발명의 다른 실시예에 따른 반도체장치의 평면패턴을 나타낸 도면.
제2(b)도는 제2(a)도에 도시된 MOS트랜지스터의 등가회로를 나타낸 회로도.

Claims (3)

  1. 반도체기판(1)의 표면에 선택적으로 형성된 凸부(2)의 측면중 최소한 대향되는 2개의 측면에 게이트산화막(3)을 매개해서 대향되도록 게이트전극(4)이 형성되고, 상기 凸부(2)의 선단표면에 소오스 또는 드레인 영역으로 되는 제1불순물확산영역(5)이 형성되며, 상기 凸부(2)의 저면주변부에 해당되면서 상기 게이트전극(4)의 하단부근방에 위치하는 기판표면의 소정영역에 드레인 또는 소오스영역으로 되는 제2불순물확산영역(6a,6b)이 형성되어 있는 반도체장치에 있어서, 상기 凸부(2)의 측면전체에 게이트전극(4)이 형성된 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 凸부(2)는 소정영역의 기판표면주위를 거의 에워싸는 평면패턴을 갖추게 되고, 이 평면패턴의 내측에 형성되어 있는 상기 제2불순물확산영역(6a)과 그 평면패턴외측에 형성되어 있는 상기 제2불순물확산영역(6b)이 평면패턴의 절단부분을 매개해서 연속적으로 형성된 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 凸부(2)는 소정영역의 기판표면주변을 거의 에워싸는 평면패턴을 갖추게 되고, 이 평면패턴의 내측에 형성되어 있는 상기 제2불순물확산영역(6a)과 평면패턴의 외측에 형성되어 있는 상기 제2불순물확산영역(6b)이 연속적으로 형성되어 있지 않은 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890009587A 1988-07-06 1989-07-06 반도체장치 KR920010673B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63168018A JPH0770721B2 (ja) 1988-07-06 1988-07-06 半導体装置
JP63-168018 1988-07-06
JP88-168018 1988-07-06

Publications (2)

Publication Number Publication Date
KR900002462A true KR900002462A (ko) 1990-02-28
KR920010673B1 KR920010673B1 (ko) 1992-12-12

Family

ID=15860283

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890009587A KR920010673B1 (ko) 1988-07-06 1989-07-06 반도체장치

Country Status (3)

Country Link
US (1) US4975754A (ko)
JP (1) JPH0770721B2 (ko)
KR (1) KR920010673B1 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03187272A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ及びその製造方法
JPH0831569B2 (ja) * 1990-01-20 1996-03-27 株式会社東芝 半導体記憶装置およびその製造方法
JPH07112067B2 (ja) * 1990-01-24 1995-11-29 株式会社東芝 半導体装置
JPH07120800B2 (ja) * 1990-01-25 1995-12-20 株式会社東芝 半導体装置およびその製造方法
US5214301A (en) * 1991-09-30 1993-05-25 Motorola, Inc. Field effect transistor having control and current electrodes positioned at a planar elevated surface
KR100242379B1 (ko) * 1992-04-17 2000-02-01 김영환 수직찬넬 mosfet 및 그 제조방법
JP2748072B2 (ja) * 1992-07-03 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
US5324673A (en) * 1992-11-19 1994-06-28 Motorola, Inc. Method of formation of vertical transistor
US5567553A (en) * 1994-07-12 1996-10-22 International Business Machines Corporation Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures
US5675164A (en) * 1995-06-07 1997-10-07 International Business Machines Corporation High performance multi-mesa field effect transistor
JPH098290A (ja) * 1995-06-20 1997-01-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6605501B1 (en) * 2002-06-06 2003-08-12 Chartered Semiconductor Manufacturing Ltd. Method of fabricating CMOS device with dual gate electrode
KR100673105B1 (ko) * 2005-03-31 2007-01-22 주식회사 하이닉스반도체 반도체 소자의 수직형 트랜지스터 및 그의 형성 방법
KR100796505B1 (ko) * 2006-12-29 2008-01-21 동부일렉트로닉스 주식회사 플래시 기억 소자의 형성 방법
JP2009004425A (ja) * 2007-06-19 2009-01-08 Elpida Memory Inc 半導体装置及び半導体装置の製造方法
US9711596B2 (en) 2014-06-24 2017-07-18 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125873A (ja) * 1982-01-22 1983-07-27 Hitachi Ltd 絶縁ゲ−ト形半導体装置
JPS6046074A (ja) * 1983-08-24 1985-03-12 Toshiba Corp 電界効果トランジスタの製造方法
JPS63115382A (ja) * 1986-11-04 1988-05-19 Matsushita Electronics Corp 半導体装置

Also Published As

Publication number Publication date
KR920010673B1 (ko) 1992-12-12
JPH0770721B2 (ja) 1995-07-31
US4975754A (en) 1990-12-04
JPH0217675A (ja) 1990-01-22

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