EP1374302A2 - Interconnection for accomodating thermal expansion for low elastic modulus dielectrics - Google Patents

Interconnection for accomodating thermal expansion for low elastic modulus dielectrics

Info

Publication number
EP1374302A2
EP1374302A2 EP01953389A EP01953389A EP1374302A2 EP 1374302 A2 EP1374302 A2 EP 1374302A2 EP 01953389 A EP01953389 A EP 01953389A EP 01953389 A EP01953389 A EP 01953389A EP 1374302 A2 EP1374302 A2 EP 1374302A2
Authority
EP
European Patent Office
Prior art keywords
interconnect
interconnect structure
integrated circuit
layer
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01953389A
Other languages
German (de)
French (fr)
Inventor
Gerald Matusiewicz
Gabriela Brase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Publication of EP1374302A2 publication Critical patent/EP1374302A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention generally relates to integrated circuits and packaging therefor and, more particularly, to metal interconnect structures to vias .
  • metal interconnects are constrained to expand and contract with temperature at about the same rate as the semiconductor substrate of the chip. That is, metal adhered to the relatively high elastic modulus insulator would be elastically deformed as the chip expanded and contracted with temperature changes .
  • the dimensional change in the metal with temperature also increases with the dimensions of the metal interconnect and shear forces are increased accordingly.
  • the length of numerous metal interconnects tends to increase with increased integration density since increased functionality of the chip often results in designs having different functions in different areas of the chip and long interconnects are required between such sections.
  • increased integration density implies finer interconnect pitch and corresponding use of insulators with reduced elastic modulus that tends to concentrate shear forces due to differences in CTEs of metal and semiconductor materials at vias and contacts.
  • via and contact size must be reduced with increasing integration density reducing the ability to withstand shear forces while some increased lengths of metal interconnects associated with increased integration density increase the shear forces which are generated and further concentrated at the vias and device contacts. These forces are generated not only by thermal cycling after the device is placed in service but also during manufacture and burn- in such that vias may fail with significant frequency before the chip is complete. Therefore, either manufacturing yield or reliability can be compromised if shear forces are not suitably limited while known instrumentalities by which shear forces have been limited do not support current and foreseeable integration densities .
  • an integrated circuit including an interconnect structure, a layer having a coefficient of thermal expansion which differs from that of the interconnect structure, the interconnect structure and the layer being separated by an insulator having a modulus of elasticity less than that of the layer and connected by at least one via connection through the insulator, wherein the interconnect structure changes direction within its length and axial length of the interconnect structure adjacent the connection is limited in accordance with respective different coefficients of thermal expansion of the interconnect and said layer.
  • Figure 1A is a plan view of a metal pad and interconnect illustrating the problem solved by the present invention
  • Figure IB is a cross-sectional view of and exemplary type of damage which may result in the structure of Figure 1A,
  • Figure 2A is a plan view of an exemplary metal pad and interconnect in accordance with a first embodiment of the invention.
  • Figure 2B is a plan view of an exemplary metal pad and interconnect in accordance with a second embodiment of the invention .
  • Figure 1A there is shown, in plan view, a metal pad and interconnect structure 10 that is likely to be damaged by shear stresses in a manner similar to the damage illustrated in Figure IB.
  • Figures are designated as "Related Art" and it should be understood that, while these Figures do not illustrate the invention, the illustrations are arranged to facilitate an understanding of the problem addressed by the invention and not portion of either Figure is admitted to be prior art in regard to the invention.
  • Figure 1A illustrates a relatively large rectangular metal pad 12 and a relatively long metal interconnect trace 14 terminating in a via or device contact 16.
  • the metal pad and interconnect trace are formed on an insulator 22 ( Figure IB) , possibly including a mitride cap layer 24 (to avoid contact between metal and resist or otherwise facilitate manufacture) and/or an adhesion layer 28, covering another layer or substrate 20 having a coefficient of thermal expansion (CTE) which differs from that of the metal pad and interconnect trace material .
  • CTE coefficient of thermal expansion
  • the metal connection 14 is fabricated as a damascene structure in a recess formed in a further insulator layer 30, preferable using a hard mask 32, as is well -understood in the art.) As temperature changes the metal 14, insulator 22 and underlying material 20 will expand and contract at different rates and develop a difference in dimensions.
  • the shear force which will be developed is a function of the dimensional difference and the elastic modulus of the metal and underlying material, as is well -understood by those skilled in the art. (The low elastic modulus of organic insulators has no significant effect on the development of shear forces.)
  • the dimensional difference and the shear forces developed will be increased over increased distances such as the length of the elongated metal interconnect trace over the distance from the nearest via connecting a metal pad to the substrate (or the center of the metal pad if not so connected) to a via separated from the metal pad. Shear forces will also be developed over the dimensions of the pad, increasing from the center outward and can be of concern if a via connects near the periphery of a large pad.
  • the insulator has a high modulus of elasticity compared to the metal and comparable to that to the underlying layer or substrate, as is the case with oxides and nitrides, the shear forces will be distributed over the dimensions of the pad and the length of the metal interconnect trace and the metal will be constrained to follow the dimensional changes of the underlying material. If, however, the elastic modulus of the insulator is low compared with that of the substrate, underlying layer or metal, particularly where the metal pad is anchored to the substrate with a plurality of vias, the insulator will be elastically deformed by the dimensional differences developed between the metal and the underlying material and the shear forces will be concentrated at the relatively rigid via or device contact connecting the metal and underlying layer.
  • the transverse dimension of the via or contact is limited by the feature size corresponding to the integration density and increased height of the via would merely tend to concentrate shear forces at a different location within the via or to develop tensile stresses at the corners (e.g. 25 and/or 26) where the via contacts the metal trace and underlying layer 20, respectively. Reduced height and increased rigidity of the via would, conversely, concentrate force in the trace 14 may cause breakage thereof near the via.
  • some process techniques are known to increase the strength of connections such as vias, the shear stresses will be developed in any case and may lead to failure at some location in an interconnection,
  • the elongated metal interconnect trace 24 includes one or more jogs or bends, While the overall length of the trace 24 is somewhat increased relative to trace 14, the segments between bends 26 are reduced and shear forces developed over the length and along the axis of each segment are reduced. Moreover, the different directions of the respective axes of the segments allows relief of the shear stresses which develop since the metal traces may be elastically flexed laterally over their narrow width. This combination of effects prevents transfer of the shear forces to and concentration of the forces at the via or device contact 16.
  • connection to pad 12 is made at a location which differs from that of Figure 1A. While such a change may usually be accommodated in device designs, the second embodiment of the invention, illustrated in Figure 2B, allows the location of the connection to remain the same as in Figure 1A. As with Figure 2A, the relative locations of the pad 12 and via 16 remain the same as in Figure 1A.
  • the interconnect 24 is configured in a meandering or serpentine form.
  • This form increases the number of jogs or bends and reduces segment length relative to the embodiment of Figure 2A while not significantly further increasing trace length.
  • the interconnect traces of Figures 2A and 2B are of metal, the resistance increase with trace length is minimal and, if found to be critical, can generally be adequately reduced or eliminated by increased cross-sectional area. In this regard, the thickness of the trace can be increased without compromising interconnect pitch.
  • Damascene conductors are preferred for increased strength, adhesion and resistance to metal migration.
  • shear forces are reduced by the reduced trace segment length, relieved by the changes in direction of trace segment axes and the ability of the traces to be elastically deformed across their narrow width and concentration of forces at the via or device contact 16 avoided. No process changes are required to form the metallization.
  • the parameter of interest for any given design is the length of any given interconnect trace and the design rule may be simplified to require utilization of the invention on all interconnect traces that exceed a particular length. It may also be desirable to impose requirements on maximum and minimum trace segment length, as well, but such a requirement is considered to be substantially less critical.
  • the invention provides an interconnect structure and ground rule for integrated circuit design which includes insulators of low modulus of elasticity which is capable of completely avoiding interconnect an via damage due to temperature excursions.
  • the invention may be implemented at no cost in regard to fabrication processes since no changes therein are required while substantial improvements are realized in manufacturing yield and reliability.
  • the invention thus supports increased integration density and designs employing interconnects of increased length as may be required by increased chip functionality.
  • the interconnect in accordance with the invention can take any form as long as a change in direction is provided within the length of the interconnect and the length of any straight segment including a connection to a via or device contact is limited.
  • the interconnect need not even be formed in segments and curved interconnects would be effective to avoid interconnect damage, as well.
  • the principles of the invention as considered to be most advantageously applied to interconnect layers of integrated circuit chips but may be employed in device layers thereof and any level of chip package structure .

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

Damage to interconnect structures including vias and/or device interconnects through insulators having a low modulus of elasticity between materials having different coefficients of thermal expansion (CTEs) by providing bends or jogs in an interconnect which limit the axial length of the interconnect adjacent the via or device contact in accordance with the difference in CTEs. The interconnect thus limits the development of shear forces and serves to relieve them by flexure of the interconnect across portions of the narrow width of the interconnect; preventing concentration of shear forces near the via or device contact. Implementation as a design rule based on limitation of length of a straight segment of an interconnect trace is preferred.

Description

INTERCONNECTION FOR ACCOMMODATING THERMAL EXPANSION FOR LOW ELASTIC MODULUS DIELECTRICS
DESCRIPTION
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to integrated circuits and packaging therefor and, more particularly, to metal interconnect structures to vias .
Description of the Prior Art
Recent trends in semiconductor integrated circuit devices have been toward increased integration density and complexity in view of both manufacturing economies and increased device performance and functionality to be derived therefrom. This, in turn, leads to increased complexity of interconnect circuits at both the chip and package level and fabrication of such interconnect structures therein at smaller sizes and finer pitch. Increased proximity between signal lines also increases capacitive coupling when using insulators of a given dielectric constant. Therefore, insulating materials which have been used in the past such as oxides and nitrides are often unsuitable for current and foreseeable generations of integrated circuit devices.
Increased integration density and switching frequencies increases the amount of heat which must be dissipated from an integrated circuit chip and large temperature excursions of the chip and the circuit package are often encountered. Substantial amounts of thermal cycling also occurs during manufacture; often significantly reducing manufacturing yield.
When oxides and nitrides are used as insulators in chip wiring layers, metal interconnects are constrained to expand and contract with temperature at about the same rate as the semiconductor substrate of the chip. That is, metal adhered to the relatively high elastic modulus insulator would be elastically deformed as the chip expanded and contracted with temperature changes .
In such a case, shear stresses due to differences in the coefficient of thermal expansion (CTE) between the metal and insulator and/or chip are distributed relatively evenly over the length of the interconnect and remain well within the range of elastic deformation throughout the interconnect structure including vias (through which connections between wiring levels can be made) and contacts to active devices having dimensions suitable for prior feature size regimes. However, as integration density is increased, the physical dimensions of vias and device contacts must also be reduced in size and are less able to withstand shear forces without damage. Therefore, metal interconnects are less well constrained to expand and contract with the chip during thermal excursions . Reduced constraint on the dimensional changes of metal interconnects tends to concentrate shear forces at vias and device contacts.
The dimensional change in the metal with temperature also increases with the dimensions of the metal interconnect and shear forces are increased accordingly. Paradoxically, the length of numerous metal interconnects tends to increase with increased integration density since increased functionality of the chip often results in designs having different functions in different areas of the chip and long interconnects are required between such sections.
Therefore, it is seen that increased integration density implies finer interconnect pitch and corresponding use of insulators with reduced elastic modulus that tends to concentrate shear forces due to differences in CTEs of metal and semiconductor materials at vias and contacts. At the same time, via and contact size must be reduced with increasing integration density reducing the ability to withstand shear forces while some increased lengths of metal interconnects associated with increased integration density increase the shear forces which are generated and further concentrated at the vias and device contacts. These forces are generated not only by thermal cycling after the device is placed in service but also during manufacture and burn- in such that vias may fail with significant frequency before the chip is complete. Therefore, either manufacturing yield or reliability can be compromised if shear forces are not suitably limited while known instrumentalities by which shear forces have been limited do not support current and foreseeable integration densities .
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an interconnect structure which relieves shear forces which occur during temperature excursions of an integrated circuit chip and/or package.
It is another object of the invention to provide design rules for metal interconnects including vias and device contacts which avoids damage to vias and device contacts where insulators of low elastic modulus are employed.
In order to accomplish these and other objects of the invention, an integrated circuit is provided including an interconnect structure, a layer having a coefficient of thermal expansion which differs from that of the interconnect structure, the interconnect structure and the layer being separated by an insulator having a modulus of elasticity less than that of the layer and connected by at least one via connection through the insulator, wherein the interconnect structure changes direction within its length and axial length of the interconnect structure adjacent the connection is limited in accordance with respective different coefficients of thermal expansion of the interconnect and said layer. BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Figure 1A is a plan view of a metal pad and interconnect illustrating the problem solved by the present invention,
Figure IB is a cross-sectional view of and exemplary type of damage which may result in the structure of Figure 1A,
Figure 2A is a plan view of an exemplary metal pad and interconnect in accordance with a first embodiment of the invention, and
Figure 2B is a plan view of an exemplary metal pad and interconnect in accordance with a second embodiment of the invention .
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
Referring now to the drawings, and more particularly to Figure 1A, there is shown, in plan view, a metal pad and interconnect structure 10 that is likely to be damaged by shear stresses in a manner similar to the damage illustrated in Figure IB. These Figures are designated as "Related Art" and it should be understood that, while these Figures do not illustrate the invention, the illustrations are arranged to facilitate an understanding of the problem addressed by the invention and not portion of either Figure is admitted to be prior art in regard to the invention.
Specifically, Figure 1A illustrates a relatively large rectangular metal pad 12 and a relatively long metal interconnect trace 14 terminating in a via or device contact 16. The metal pad and interconnect trace are formed on an insulator 22 (Figure IB) , possibly including a mitride cap layer 24 (to avoid contact between metal and resist or otherwise facilitate manufacture) and/or an adhesion layer 28, covering another layer or substrate 20 having a coefficient of thermal expansion (CTE) which differs from that of the metal pad and interconnect trace material . (While not important to the practice of the invention, it is preferred that the metal connection 14 is fabricated as a damascene structure in a recess formed in a further insulator layer 30, preferable using a hard mask 32, as is well -understood in the art.) As temperature changes the metal 14, insulator 22 and underlying material 20 will expand and contract at different rates and develop a difference in dimensions.
The shear force which will be developed is a function of the dimensional difference and the elastic modulus of the metal and underlying material, as is well -understood by those skilled in the art. (The low elastic modulus of organic insulators has no significant effect on the development of shear forces.) The dimensional difference and the shear forces developed will be increased over increased distances such as the length of the elongated metal interconnect trace over the distance from the nearest via connecting a metal pad to the substrate (or the center of the metal pad if not so connected) to a via separated from the metal pad. Shear forces will also be developed over the dimensions of the pad, increasing from the center outward and can be of concern if a via connects near the periphery of a large pad. If the insulator has a high modulus of elasticity compared to the metal and comparable to that to the underlying layer or substrate, as is the case with oxides and nitrides, the shear forces will be distributed over the dimensions of the pad and the length of the metal interconnect trace and the metal will be constrained to follow the dimensional changes of the underlying material. If, however, the elastic modulus of the insulator is low compared with that of the substrate, underlying layer or metal, particularly where the metal pad is anchored to the substrate with a plurality of vias, the insulator will be elastically deformed by the dimensional differences developed between the metal and the underlying material and the shear forces will be concentrated at the relatively rigid via or device contact connecting the metal and underlying layer.
These forces may become large enough at a particular temperature and for a given distance to inelastically deform the via or contact material or even large enough to reach the yield point of the material. In the latter case, the via of contact may be broken by a single large temperature excursion.
In the former case, inelastic deformation may lead to an effect comparable to fatigue (although the mechanism by which this effect occurs in conductors which may have cross- sectional dimensions as small as several hundred atomic diameters has not been determined since some artifacts associated with fatigue and other known effects have not been observed) ; causing fracture over a largely unpredictable number of smaller temperature excursions. An exemplary form of such breakage 28 is illustrated in Figure IB in which diagonal fracture lines characteristic of shear force fracture are seen at the via 16 where metal line 14 is attached thereto .
It should be appreciated from Figure IB that avoidance of such damage cannot, as a practical matter, be avoided by changes in the via or contact structure 16. For example, the transverse dimension of the via or contact is limited by the feature size corresponding to the integration density and increased height of the via would merely tend to concentrate shear forces at a different location within the via or to develop tensile stresses at the corners (e.g. 25 and/or 26) where the via contacts the metal trace and underlying layer 20, respectively. Reduced height and increased rigidity of the via would, conversely, concentrate force in the trace 14 may cause breakage thereof near the via. Although some process techniques are known to increase the strength of connections such as vias, the shear stresses will be developed in any case and may lead to failure at some location in an interconnection,
Referring now to Figure 2A, a first embodiment of the invention is shown in plan view. It should be appreciated that the relative positions of pad 12 and via 16 are the same as in Figure 1A. However, in the case of the invention, the elongated metal interconnect trace 24 includes one or more jogs or bends, While the overall length of the trace 24 is somewhat increased relative to trace 14, the segments between bends 26 are reduced and shear forces developed over the length and along the axis of each segment are reduced. Moreover, the different directions of the respective axes of the segments allows relief of the shear stresses which develop since the metal traces may be elastically flexed laterally over their narrow width. This combination of effects prevents transfer of the shear forces to and concentration of the forces at the via or device contact 16.
It should be noted that, to achieve the jogs or bends 26 in the embodiment of Figure 2A, the connection to pad 12 is made at a location which differs from that of Figure 1A. While such a change may usually be accommodated in device designs, the second embodiment of the invention, illustrated in Figure 2B, allows the location of the connection to remain the same as in Figure 1A. As with Figure 2A, the relative locations of the pad 12 and via 16 remain the same as in Figure 1A.
In the case of the embodiment of Figure 2B, the interconnect 24 is configured in a meandering or serpentine form. This form increases the number of jogs or bends and reduces segment length relative to the embodiment of Figure 2A while not significantly further increasing trace length. (Since the interconnect traces of Figures 2A and 2B are of metal, the resistance increase with trace length is minimal and, if found to be critical, can generally be adequately reduced or eliminated by increased cross-sectional area. In this regard, the thickness of the trace can be increased without compromising interconnect pitch. Damascene conductors, alluded to above, are preferred for increased strength, adhesion and resistance to metal migration.) As with the embodiment of Figure 2A, shear forces are reduced by the reduced trace segment length, relieved by the changes in direction of trace segment axes and the ability of the traces to be elastically deformed across their narrow width and concentration of forces at the via or device contact 16 avoided. No process changes are required to form the metallization.
It is preferred to implement the invention as a design rule requiring employment of the invention in any portion of an integrated circuit design where there is an empirically determined significant possibility of breakage similar to that of Figure IB. That is, it is preferred at the present time to apply the invention on all interconnects having a length exceeding a length at which no via fractures are observed to occur in circuits having vias and interconnects of similar dimensions. Alternatively, this possibility can readily be estimated by a relatively simple computation based on the length of the trace, the greatest anticipated temperature excursion, the CTEs and elastic moduli of the metal and underlying material and the dimensions and metallurgical properties of the via or device contact material which may be empirically determined. As a practical matter, the latter three of these factors will be substantially the same for given combinations of materials and minimum feature size regime of the design. Therefore, the parameter of interest for any given design is the length of any given interconnect trace and the design rule may be simplified to require utilization of the invention on all interconnect traces that exceed a particular length. It may also be desirable to impose requirements on maximum and minimum trace segment length, as well, but such a requirement is considered to be substantially less critical.
In view of the foregoing, it is seen that the invention provides an interconnect structure and ground rule for integrated circuit design which includes insulators of low modulus of elasticity which is capable of completely avoiding interconnect an via damage due to temperature excursions. The invention may be implemented at no cost in regard to fabrication processes since no changes therein are required while substantial improvements are realized in manufacturing yield and reliability. The invention thus supports increased integration density and designs employing interconnects of increased length as may be required by increased chip functionality.
The interconnect in accordance with the invention can take any form as long as a change in direction is provided within the length of the interconnect and the length of any straight segment including a connection to a via or device contact is limited. The interconnect need not even be formed in segments and curved interconnects would be effective to avoid interconnect damage, as well. The principles of the invention as considered to be most advantageously applied to interconnect layers of integrated circuit chips but may be employed in device layers thereof and any level of chip package structure .
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims .

Claims

CLAIMSHaving thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows:
1. An integrated circuit including an interconnect structure, a layer having a coefficient of thermal expansion which differs from that of the interconnect structure, said interconnect structure and said layer being separated by an insulator having a modulus of elasticity less than that of said layer, and at least one via connection connecting said interconnect structure and said layer through said insulator, wherein said interconnect structure changes direction within its length and axial length of said interconnect structure adjacent said connection is limited in accordance with respective different coefficients of thermal expansion of said interconnect and said layer.
2. An integrated circuit device as recited in claim 1, wherein said interconnect structure includes two segments joined at and angle.
3. An integrated circuit device as recited in claim 1, wherein said interconnect structure has a serpentine configuration .
4. An integrated circuit device as recited in claim 1, wherein said interconnect structure connects said via structure and a metal pad.
5. An integrated circuit device as recited in claim 4, including a further via connection connecting said metal pad to said layer.
6. An integrated circuit device as recited in claim 1, wherein said interconnect structure is formed in a recess in an insulator layer.
7. An integrated circuit device as recited in claim 2, wherein said interconnect structure is formed in a recess in an insulator layer.
8. An integrated circuit device as recited in claim 3, wherein said interconnect structure is formed in a recess in an insulator layer.
9. An integrated circuit device as recited in claim 4, wherein said interconnect structure is formed in a recess in an insulator layer.
10. An integrated circuit device as recited in claim 5, wherein said interconnect structure is formed in a recess in an insulator layer.
EP01953389A 2000-06-27 2001-06-27 Interconnection for accomodating thermal expansion for low elastic modulus dielectrics Withdrawn EP1374302A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60453400A 2000-06-27 2000-06-27
US604534 2000-06-27
PCT/US2001/020354 WO2002001632A2 (en) 2000-06-27 2001-06-27 Interconnection for accomodating thermal expansion for low elastic modulus dielectrics

Publications (1)

Publication Number Publication Date
EP1374302A2 true EP1374302A2 (en) 2004-01-02

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EP01953389A Withdrawn EP1374302A2 (en) 2000-06-27 2001-06-27 Interconnection for accomodating thermal expansion for low elastic modulus dielectrics

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EP (1) EP1374302A2 (en)
JP (1) JP2004507883A (en)
KR (1) KR100525212B1 (en)
TW (1) TW529148B (en)
WO (1) WO2002001632A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69233550T2 (en) * 1991-01-22 2006-06-22 Nec Corp. Plastic coated semiconductor integrated circuit with a wiring layer
JP3332456B2 (en) * 1992-03-24 2002-10-07 株式会社東芝 Semiconductor device manufacturing method and semiconductor device
US5358733A (en) * 1993-01-08 1994-10-25 United Microelectronics Corporation Stress release metallization for VLSI circuits
JP3152180B2 (en) * 1997-10-03 2001-04-03 日本電気株式会社 Semiconductor device and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0201632A2 *

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Publication number Publication date
KR100525212B1 (en) 2005-11-01
TW529148B (en) 2003-04-21
WO2002001632A2 (en) 2002-01-03
KR20030020308A (en) 2003-03-08
JP2004507883A (en) 2004-03-11
WO2002001632A3 (en) 2003-10-23

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