Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Geometry or layout of the interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention generally relates to integrated circuits and packaging therefor and, more particularly, to metal interconnect structures to vias .
• metal interconnects are constrained to expand and contract with temperature at about the same rate as the semiconductor substrate of the chip. That is, metal adhered to the relatively high elastic modulus insulator would be elastically deformed as the chip expanded and contracted with temperature changes .
• the dimensional change in the metal with temperature also increases with the dimensions of the metal interconnect and shear forces are increased accordingly.
• the length of numerous metal interconnects tends to increase with increased integration density since increased functionality of the chip often results in designs having different functions in different areas of the chip and long interconnects are required between such sections.
• increased integration density implies finer interconnect pitch and corresponding use of insulators with reduced elastic modulus that tends to concentrate shear forces due to differences in CTEs of metal and semiconductor materials at vias and contacts.
• via and contact size must be reduced with increasing integration density reducing the ability to withstand shear forces while some increased lengths of metal interconnects associated with increased integration density increase the shear forces which are generated and further concentrated at the vias and device contacts. These forces are generated not only by thermal cycling after the device is placed in service but also during manufacture and burn- in such that vias may fail with significant frequency before the chip is complete. Therefore, either manufacturing yield or reliability can be compromised if shear forces are not suitably limited while known instrumentalities by which shear forces have been limited do not support current and foreseeable integration densities .
• an integrated circuit including an interconnect structure, a layer having a coefficient of thermal expansion which differs from that of the interconnect structure, the interconnect structure and the layer being separated by an insulator having a modulus of elasticity less than that of the layer and connected by at least one via connection through the insulator, wherein the interconnect structure changes direction within its length and axial length of the interconnect structure adjacent the connection is limited in accordance with respective different coefficients of thermal expansion of the interconnect and said layer.
• Figure 1A is a plan view of a metal pad and interconnect illustrating the problem solved by the present invention
• Figure IB is a cross-sectional view of and exemplary type of damage which may result in the structure of Figure 1A,
• Figure 2A is a plan view of an exemplary metal pad and interconnect in accordance with a first embodiment of the invention.
• Figure 2B is a plan view of an exemplary metal pad and interconnect in accordance with a second embodiment of the invention .
• Figure 1A there is shown, in plan view, a metal pad and interconnect structure 10 that is likely to be damaged by shear stresses in a manner similar to the damage illustrated in Figure IB.
• Figures are designated as "Related Art" and it should be understood that, while these Figures do not illustrate the invention, the illustrations are arranged to facilitate an understanding of the problem addressed by the invention and not portion of either Figure is admitted to be prior art in regard to the invention.
• Figure 1A illustrates a relatively large rectangular metal pad 12 and a relatively long metal interconnect trace 14 terminating in a via or device contact 16.
• the metal pad and interconnect trace are formed on an insulator 22 ( Figure IB) , possibly including a mitride cap layer 24 (to avoid contact between metal and resist or otherwise facilitate manufacture) and/or an adhesion layer 28, covering another layer or substrate 20 having a coefficient of thermal expansion (CTE) which differs from that of the metal pad and interconnect trace material .
• CTE coefficient of thermal expansion
• the metal connection 14 is fabricated as a damascene structure in a recess formed in a further insulator layer 30, preferable using a hard mask 32, as is well -understood in the art.) As temperature changes the metal 14, insulator 22 and underlying material 20 will expand and contract at different rates and develop a difference in dimensions.
• the shear force which will be developed is a function of the dimensional difference and the elastic modulus of the metal and underlying material, as is well -understood by those skilled in the art. (The low elastic modulus of organic insulators has no significant effect on the development of shear forces.)
• the dimensional difference and the shear forces developed will be increased over increased distances such as the length of the elongated metal interconnect trace over the distance from the nearest via connecting a metal pad to the substrate (or the center of the metal pad if not so connected) to a via separated from the metal pad. Shear forces will also be developed over the dimensions of the pad, increasing from the center outward and can be of concern if a via connects near the periphery of a large pad.
• the insulator has a high modulus of elasticity compared to the metal and comparable to that to the underlying layer or substrate, as is the case with oxides and nitrides, the shear forces will be distributed over the dimensions of the pad and the length of the metal interconnect trace and the metal will be constrained to follow the dimensional changes of the underlying material. If, however, the elastic modulus of the insulator is low compared with that of the substrate, underlying layer or metal, particularly where the metal pad is anchored to the substrate with a plurality of vias, the insulator will be elastically deformed by the dimensional differences developed between the metal and the underlying material and the shear forces will be concentrated at the relatively rigid via or device contact connecting the metal and underlying layer.
• the transverse dimension of the via or contact is limited by the feature size corresponding to the integration density and increased height of the via would merely tend to concentrate shear forces at a different location within the via or to develop tensile stresses at the corners (e.g. 25 and/or 26) where the via contacts the metal trace and underlying layer 20, respectively. Reduced height and increased rigidity of the via would, conversely, concentrate force in the trace 14 may cause breakage thereof near the via.
• some process techniques are known to increase the strength of connections such as vias, the shear stresses will be developed in any case and may lead to failure at some location in an interconnection,
• the elongated metal interconnect trace 24 includes one or more jogs or bends, While the overall length of the trace 24 is somewhat increased relative to trace 14, the segments between bends 26 are reduced and shear forces developed over the length and along the axis of each segment are reduced. Moreover, the different directions of the respective axes of the segments allows relief of the shear stresses which develop since the metal traces may be elastically flexed laterally over their narrow width. This combination of effects prevents transfer of the shear forces to and concentration of the forces at the via or device contact 16.
• connection to pad 12 is made at a location which differs from that of Figure 1A. While such a change may usually be accommodated in device designs, the second embodiment of the invention, illustrated in Figure 2B, allows the location of the connection to remain the same as in Figure 1A. As with Figure 2A, the relative locations of the pad 12 and via 16 remain the same as in Figure 1A.
• the interconnect 24 is configured in a meandering or serpentine form.
• This form increases the number of jogs or bends and reduces segment length relative to the embodiment of Figure 2A while not significantly further increasing trace length.
• the interconnect traces of Figures 2A and 2B are of metal, the resistance increase with trace length is minimal and, if found to be critical, can generally be adequately reduced or eliminated by increased cross-sectional area. In this regard, the thickness of the trace can be increased without compromising interconnect pitch.
• Damascene conductors are preferred for increased strength, adhesion and resistance to metal migration.
• shear forces are reduced by the reduced trace segment length, relieved by the changes in direction of trace segment axes and the ability of the traces to be elastically deformed across their narrow width and concentration of forces at the via or device contact 16 avoided. No process changes are required to form the metallization.
• the parameter of interest for any given design is the length of any given interconnect trace and the design rule may be simplified to require utilization of the invention on all interconnect traces that exceed a particular length. It may also be desirable to impose requirements on maximum and minimum trace segment length, as well, but such a requirement is considered to be substantially less critical.
• the invention provides an interconnect structure and ground rule for integrated circuit design which includes insulators of low modulus of elasticity which is capable of completely avoiding interconnect an via damage due to temperature excursions.
• the invention may be implemented at no cost in regard to fabrication processes since no changes therein are required while substantial improvements are realized in manufacturing yield and reliability.
• the invention thus supports increased integration density and designs employing interconnects of increased length as may be required by increased chip functionality.
• the interconnect in accordance with the invention can take any form as long as a change in direction is provided within the length of the interconnect and the length of any straight segment including a connection to a via or device contact is limited.
• the interconnect need not even be formed in segments and curved interconnects would be effective to avoid interconnect damage, as well.
• the principles of the invention as considered to be most advantageously applied to interconnect layers of integrated circuit chips but may be employed in device layers thereof and any level of chip package structure .

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Geometry (AREA)
• Manufacturing & Machinery (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Coupling Device And Connection With Printed Circuit (AREA)

Applications Claiming Priority (3)

Publications (1)

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• 2001
  • 2001-06-27 JP JP2002505678A patent/JP2004507883A/ja active Pending
  • 2001-06-27 EP EP01953389A patent/EP1374302A2/de not_active Withdrawn
  • 2001-06-27 KR KR10-2002-7017781A patent/KR100525212B1/ko not_active IP Right Cessation
  • 2001-06-27 WO PCT/US2001/020354 patent/WO2002001632A2/en not_active Application Discontinuation
  • 2001-06-27 TW TW090115596A patent/TW529148B/zh not_active IP Right Cessation

Non-Patent Citations (1)

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