529148 A7 B7 五、發明説明 發明背景 發明範疇 本發明通常和積體電路及其封裝，更特別是和通道之金 屬互連架構有關。 先前技術描述 因製造成本及增加裝置性能及功能之考量，現今半導體 積體電路裝置之趨勢是增加積體密度及複雜性。這使得大 小較小及節距較細之互連電路晶片及封裝程度及製造複雜 性增加。當使用既定介電常數之絕緣體時，信號線間越接 近亦增加電容耦合。故過去所用如氧化物及氮化物之絕緣 材料常不適於目前及最近之積體電路裝置。 增加積體密度及切換頻率會增加積體電路晶片必需耗散 之熱量，且晶片及晶片封裝常有大溫度偏移。在製造中亦 常有大量熱循環，常使製造良率大幅降低。常使用氧化物 及氮化物做為晶片接線層之絕緣體，金屬互連限制為約和 曰曰片半導體基體相同之溫度縮脹率。即和極高彈性模數絕 緣體黏合之金屬在晶片因溫度變化而脹縮時會彈性變形。 在此情形，因金屬及絕緣體及/或晶片間之熱膨脹係數 (CTE)差造成之剪力相當均勻分佈於互連長上，且在包含通 道油之可連接接線程度及接觸之互連架構至尺寸適於先前 特性大小之作用裝置均維持於彈性變形範圍中。但當積體 密度增加，通道及裝置接觸之物理尺寸亦需降低且較無法 承受剪力而不損壞。故在熱偏移時較無法限制金屬互連隨 晶片縮脹。金屬互連尺寸變化限制降低，將使剪力集中在 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)529148 A7 B7 V. Description of the Invention Background of the Invention The present invention relates generally to integrated circuits and their packages, and more particularly to the metal interconnect architecture of channels. Description of the prior art Due to manufacturing cost and consideration of increasing device performance and functions, the current trend of semiconductor integrated circuit devices is to increase the density and complexity of the integrated circuits. This results in smaller and finer interconnect circuit chips and packages, as well as increased manufacturing complexity. When an insulator with a predetermined dielectric constant is used, the closer the signal lines are, the more capacitive coupling is increased. Therefore, insulating materials such as oxides and nitrides used in the past are often not suitable for current and recent integrated circuit devices. Increasing the density of the integrated circuit and the switching frequency will increase the heat that the integrated circuit chip must dissipate, and the chip and the chip package often have large temperature deviations. There are also a large number of thermal cycles in manufacturing, which often reduce manufacturing yields significantly. Oxides and nitrides are often used as insulators for wafer wiring layers, and metal interconnects are limited to about the same rate of thermal expansion as a semiconductor substrate. That is, the metal bonded to the extremely high elastic modulus insulator will elastically deform when the wafer expands and contracts due to temperature changes. In this case, the shear force caused by the difference in the coefficient of thermal expansion (CTE) between the metal and the insulator and / or the wafer is fairly evenly distributed on the interconnect length, and the interconnect structure including the connectable wiring degree and contact of the channel oil to The action devices with dimensions suitable for the previous characteristics are maintained in the elastic deformation range. However, as the density of the product increases, the physical dimensions of the channels and devices need to be reduced and they are less able to withstand the shear forces without damage. Therefore, it is less able to limit the expansion of the metal interconnect with the wafer during thermal offset. Restrictions on the dimensional change of metal interconnects will be reduced, which will focus the shear force on -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
裝 訂 529148 A7 B7 五、發明説明（2 ) 通道及裝置接觸上。 金屬因溫度而尺寸變更，亦使金屬互連尺寸及剪力隨之 增加。矛盾的是許多金屬互連長呈隨積體密度增加而增 加，因晶片功能增加常有在晶片不同區具不同功能之設 計，而在這些區間需長互連。 故可發現增加積體密度表示互連節距較細，而對應使用 之彈性模數降低之絕緣體，因在通道及接觸之金屬及半導 體材料CTEs差而使剪力集中。而增加積體密度需降低通道 及接觸大小而使承受剪力之能力降低，同時和積體密度增 加有關之金屬互連長增加會增加產生及集中在通道及裝置 接觸上之剪力。這些剪力除在裝置作用之熱循環產生，也 在製造及老煉時產生使得通道常在晶片完成前即失效。莖 若未適當限制剪力，同時剪力之已知方沬無法支援目前及 近來之積體密度，將會犧牲良率或可靠度。 發明概論 故本發明之一目的是提供釋放積體電路晶片及/或封裝溫 度偏移時發生之剪力之互連架構。 本發明另一目的是提供避免在實施低彈性模數之絕緣體 時損壞通道及裝置接觸之包含通道及裝置接觸之金屬互連 設計準則。 為達到本發明這些及其它目的提供之積體晶片包含互連 架構、熱膨脹係數和互連架構不阔之層，該互連架構及該 層由彈性模數較該層低之絕緣體分隔及由經絕緣體之至少 一通道連接，其中之互連架構在其長中變更方向及 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 529148 A7 B7 五、發明説明（4 ) 溫度變化，金屬14、絕緣體22及其下材料20將以不同速率 脹縮，且在尺寸上產生差異。 如精於本技術者所熟知，所發展剪力為金屬及其下材料 彈性模數及尺寸差之函數。（有機絕緣體之低彈性模數對剪 力之發展並無很大影響）。所發展剪力及尺寸差在增加之距 離將會增加，如自連接金屬墊和基體之最近通道（或在未如 此連接時之金屬墊中央）至和金屬墊分開之通道之距離之拉 長金屬互連trace。在該墊上亦會發展剪力由中央向外增 加，且若通道靠近大墊周圍連接將更重要。若絕緣體之彈 性模數較金屬高且和其下層或基體差不多，當為氮化物或 氧化物時，剪力將分佈在該墊上，而金屬及金屬互連trace 長將限制為跟隨其下材料之尺寸變化。但若絕緣體之彈性 模數較基體、其下層或金屬低，特別是金屬墊以多個通道 固定在基體上，絕緣體將因金屬及其下材料間之尺寸差而 彈性變形’而剪力將集中在連接金屬及其下層之極硬通道 或裝置中。 這些剪力可能大到足以在特定溫度及既定距離將通道或 接觸材料非彈性變形或甚至大到達材料之屈服點。在後者 接觸之通道可能因單一大溫度偏移而破損。在前者，非彈 1±、菱形可導致當於疲乏之效應（但尚未決定對於側面尺寸小 到幾百原子直徑之導體發生此效應之機構，因尚未發現和 疲乏有關之外來物質及其它已知效應）；在許多無法預知數 目之小溫度偏移造成斷裂。此斷線28之範例形式於圖1B說 明’其中在金屬線14附著之通道16可看到剪力斷裂之對角Binding 529148 A7 B7 V. Description of the invention (2) Channels and devices are in contact. The change in the size of metal due to temperature also increases the size and shear of the metal interconnect. Paradoxically, the length of many metal interconnects increases as the density of the product increases. Because of the increase in chip functions, there are often designs with different functions in different regions of the chip, and long interconnects are required in these regions. Therefore, it can be found that increasing the density of the product indicates that the interconnect pitch is thinner, and the correspondingly used insulator with a reduced elastic modulus has concentrated shear forces due to poor CTEs of the metal and semiconductor materials in the channel and contact. Increasing the density of the product needs to reduce the channel and contact size to reduce the ability to withstand shear forces. At the same time, the increase in the metal interconnect length associated with the increase of the product density will increase the shear force generated and concentrated on the channel and device contacts. In addition to these shear forces, which are generated during the thermal cycling of the device, they are also produced during manufacturing and aging so that the channels often fail before the wafer is completed. If the stem is not properly restricted, and the known shear strength of the stem cannot support the current and recent volume densities, yield or reliability will be sacrificed. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an interconnect architecture that releases shear forces that occur when integrated circuit chips and / or package temperature shifts occur. Another object of the present invention is to provide design guidelines for metal interconnections including channels and device contacts, which avoid damage to channels and device contacts when implementing insulators with low elastic modulus. The integrated chip provided to achieve these and other objects of the present invention includes a layer having an interconnect structure, a thermal expansion coefficient, and an interconnect structure that is not wide. The interconnect structure and the layer are separated by an insulator having a lower elastic modulus than the layer, and the At least one channel connection of the insulator, the interconnection structure of which changes direction in its length and -5- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 529148 A7 B7 V. Description of the invention (4) As the temperature changes, the metal 14, the insulator 22, and the underlying material 20 will expand and contract at different rates, and there will be differences in size. As is well known to those skilled in the art, the developed shear force is a function of the elastic modulus and dimensional difference of the metal and its underlying material. (The low elastic modulus of organic insulators does not significantly affect the development of shear forces). The distance between the developed shear force and the dimensional difference will increase, such as the lengthened metal from the distance between the nearest channel connecting the metal pad and the substrate (or the center of the metal pad when not so connected) to the channel separated from the metal pad Interconnect trace. Shear force will also develop from the center to the outside, and it will be more important if the channel is connected near the big pad. If the elastic modulus of the insulator is higher than that of metal and is similar to the underlying layer or substrate, when it is nitride or oxide, the shear force will be distributed on the pad, and the trace length of the metal and metal interconnect will be limited to follow the material below it. Size changes. However, if the elastic modulus of the insulator is lower than that of the substrate, its underlying layer or metal, especially the metal pad is fixed on the substrate with multiple channels, the insulator will be elastically deformed due to the size difference between the metal and the underlying material, and the shear force will be concentrated In extremely hard channels or devices that connect metal and its underlying layers. These shear forces may be large enough to inelastically deform the channel or contact material or even reach the material's yield point at a specific temperature and a predetermined distance. Channels in contact with the latter may be damaged by a single large temperature shift. In the former, non-elastic 1 ±, rhombus can lead to fatigue effects (but the mechanism for this effect has not yet been determined for conductors with side dimensions as small as a few hundred atomic diameters, because foreign matter and other known materials related to fatigue have not been found Effect); fracture at many unpredictable numbers of small temperature excursions. An example form of this disconnection 28 is illustrated in FIG. 1B, where the diagonal of the shear fracture can be seen in the channel 16 where the metal wire 14 is attached
X 297公釐） 529148 A7 B7 五、發明説明（5 斷裂線特性。 由圖1B應了解實際上無法由變更通道或接觸架構16避免 此損壞。例如通道或接觸之橫向尺寸受和積體密度對應之 特性大小限制及通道高度增加只會將剪力集中在孔之不同 位置或在通道分別和金屬trace及其下層20接觸之角落（如 25及/或26)發展張應力。通道高度降低及剛性增加將相反 地集中剪力於trace 14而造成其靠近通道處斷線。雖已知有 些處理技術可增加如通道之連接強度，但隨時會發展剪力 且可使互連一些位置失效。 現參照圖2A顯示本發明第一實施例俯視圖。應了解墊12 及通道16之相對位置和圖ία相同。但在本發明拉長金屬互 連trace 24包含一或多個接合或彎曲，而trace 24總長較 trace 14增加，彎曲26間之線段降低且各線段軸及長上發 展之剪力降低。另外線段不同方向之個別軸釋放發展之剪 力’因金屬traces可橫向在其窄寬度彈性屈曲。此效應之組 合防止剪力轉移及集中在通道或裝置接觸16。 要知道為達成圖2A實施例之接合或彎曲26，和塾12之連 接位置和圖1A不同。此變動雖常納入裝置設計中，圖2B說 明之本發明第二實施例使連接位置仍和圖1A相同。但圖2A 之墊12和通道16之相對位置仍和圖1A相同。 在圖2B之實施例，互連24架構為曲折或蛇形。此形式增 加接合或彎曲數目並降低相對於圖2A實施例之線段長度， 同時未再大幅增加trace長。（因圖2A及2B之互連traces為 金屬故trace長電阻之增加並不重要，而若為重要時通常可 -8- 529148 A7 B7 五、發明説明（ 利用增加剖面積適當將之降低或消除。關於這點可增加 trace厚而不犧牲互連節距。最好為上述之鑲嵌導體以增加 金屬徒動之電阻、黏附及強度。）在圖2八之實施例，剪力因 降低trace線段長而降低，由變更忱“€線段軸方向及忱“。 在窄寬度之彈性變形能力而減輕，且避免剪力集中在通道 或裝置接觸16。在形成金屬化時無需變化處理。 對於經驗上發現極可能有和圖丨B斷線類似之積體電路設 计所有部份最好以本發明做為設計準則。即目前最好在所 有長度超過具類似尺寸通道及互連之電路未發現通道斷裂 之長度時，引用本發明。替代地根據以下因數估計此機率 可很簡單：trace長，最大預值溫度偏移、金屬及其下材料 之CTEs及彈性模數及通道或裝置接觸材料之尺寸及治金特 性這可由經驗決定。實際上以上之後三個因數在設計最小 祷性大小制度及材料既定組合是實質相同。故任何既定設 計希望之參數為既定互連仃&(^長，而可簡化設計準則為要 求超過特定長之所有互連traces使用本發明。亦希望限制最 大及最小trace片段長，但此要求實質上較不重要。 由上述可知本發明提供一互連架構及積體電路設計之基 本規則’包含之低彈性模數絕緣體可完全避免溫度偏移造 成之互連及通道損壞。實施本發明在製程上因並無變動而 不需增加成本，實質上卻改良製迫良率及可靠度。故本發 明支援積體密度增加及增加晶片功能所需互連長增加之設 計。 依照本發明之互連可為任何形式，只要方向之變更在互 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)X 297 mm) 529148 A7 B7 V. Description of the invention (5 Breaking line characteristics. It should be understood from Figure 1B that this damage cannot actually be avoided by changing the channel or contact structure 16. For example, the lateral dimension of the channel or contact corresponds to the volume density Due to the characteristic size limitation and the increase of the channel height, only the shear force is concentrated at different positions of the hole or the tensile stress is developed at the corners (such as 25 and / or 26) where the channel is in contact with the metal trace and its lower layer 20. The channel height is reduced and the rigidity is increased. Increasing will conversely concentrate the shear force on trace 14 and cause it to break near the channel. Although some processing techniques are known to increase the strength of the connection such as the channel, the shear force may develop at any time and may cause some locations of the interconnect to fail. FIG. 2A shows a top view of the first embodiment of the present invention. It should be understood that the relative positions of the pad 12 and the channel 16 are the same as those in the figure. However, in the present invention, the elongated metal interconnect trace 24 includes one or more joints or bends, and the total length of the trace 24 is Compared with trace 14, the line segments between bends 26 are reduced and the shear force of each line segment axis and length is reduced. In addition, the individual axes of different directions of the line segments release the shear force of development The traces can be elastically buckled laterally across their narrow width. The combination of this effect prevents shear forces from shifting and concentrating on the channel or device contact 16. It is necessary to know the connection position and diagram of the joint or bend 26 of the embodiment of Fig. 2A and Fig. 1A is different. Although this change is often incorporated into the device design, the second embodiment of the present invention illustrated in FIG. 2B makes the connection position the same as that in FIG. 1A. However, the relative positions of the pad 12 and the channel 16 in FIG. 2A are still the same as in FIG. 1A. In the embodiment of FIG. 2B, the interconnect 24 structure is zigzag or serpentine. This form increases the number of joints or bends and reduces the length of the line segment compared to the embodiment of FIG. 2A, while the trace length is not significantly increased. Interconnection traces are metal, so the increase of long trace resistance is not important, but if it is important, it can usually be increased by -8-529148 A7 B7. 5. Description of the invention (Use an increase in cross-sectional area to appropriately reduce or eliminate it. About this, you can increase the trace. Thick without sacrificing the interconnect pitch. It is best to use the above-mentioned inlaid conductor to increase the resistance, adhesion and strength of the metal.) In the embodiment of Fig. 2-8, the shear force is reduced by reducing the length of the trace line segment. "€ Segment axis direction and enthusiasm." The ability to reduce the elastic deformation in a narrow width is reduced, and to avoid shear forces concentrated on the channel or device contact 16. No change processing is required when forming metallization. It is found that there is a possibility of summing up with experience. All parts of integrated circuit designs with similar broken wires are best based on the present invention as a design criterion. That is, it is best to cite this when all the lengths of the circuits with similar size channels and interconnections are not found to have broken channels. Invention. Alternatively, it is easy to estimate this probability based on the following factors: long trace, maximum predicted temperature deviation, CTEs and elastic modulus of metal and its underlying materials, and the dimensions and metallographic characteristics of the material in contact with the channel or device. This can be learned from experience. Decide. In fact, the above three factors are essentially the same when designing the minimum prayer size system and the given combination of materials. Therefore, the parameter desired for any given design is the given interconnect length, and the design criteria can be simplified to require the use of the present invention for all interconnect traces exceeding a certain length. It is also desirable to limit the maximum and minimum trace segment lengths, but this requirement It is substantially less important. From the above, it can be known that the present invention provides a basic rule for interconnect architecture and integrated circuit design. The included low elastic modulus insulator can completely avoid interconnection and channel damage caused by temperature deviation. Because there is no change in the manufacturing process without increasing costs, it actually improves the yield and reliability of the system. Therefore, the present invention supports the design of increasing the density of the integrated structure and increasing the interconnection length required to increase the chip function. The connection can be in any form, as long as the change of direction is within the mutual -9- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)