TWI524440B - 具有貫穿之半導體通孔之積體電路封裝系統及其製造方法 - Google Patents

具有貫穿之半導體通孔之積體電路封裝系統及其製造方法 Download PDF

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TWI524440B
TWI524440B TW099130278A TW99130278A TWI524440B TW I524440 B TWI524440 B TW I524440B TW 099130278 A TW099130278 A TW 099130278A TW 99130278 A TW99130278 A TW 99130278A TW I524440 B TWI524440 B TW I524440B
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integrated circuit
circuit die
package substrate
package
die
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TW099130278A
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TW201130063A (en
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陳治強
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星科金朋有限公司
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

具有貫穿之半導體通孔之積體電路封裝系統及其製造方法
本發明係大致關於積體電路封裝系統，且尤係關於用以在堆疊中形成具有貫穿之半導體通孔(through semiconductor via)的多晶片封裝件的系統。
電子元件的製造的目標之一係使各種元件的尺寸最小化。舉例來說，要求例如行動電話與個人數位助理(PDA)的手持裝置愈小愈好。為了達成此目標，包含在該裝置內的半導體電路應該是愈小愈好。使這些電路更小的一個方式是堆疊帶有該電路的晶片。
許多在該堆疊內互連該等晶片的方式是眾所皆知的。舉例來說，可將形成在各晶片表面處的接合墊(bond pad)線接合(wire-bond)至共用基板或至該堆疊中的其他晶片。另一例子是所謂的微凸塊3D封裝件(micro-bump 3D package)，其中，各晶片包含許多微凸塊，該微凸塊是排定路線(route)至電路板，例如沿著該晶片的外邊緣。
還有另一個在該堆疊內互連晶片的方式是使用貫穿之半導體通孔。該貫穿之半導體通孔延伸通過該基板，進而容許許多晶片上電路之間的電性互連。相較於其他技術，貫穿之半導體通孔互連在互連密度方面可提供優勢。然而，此種互連的引入可能引入額外的挑戰。
在3D中的晶片整合產生許多需要對付的新挑戰。因此，所屬技術領域需要的是改良的結構與製造3D晶片整合結構的方法。
因此，可協助封裝件縮小製程的具有貫穿之半導體通孔的積體電路封裝系統的需求仍然持續。鑒於持續增加的功能轉變製程及高品質與實體小裝置的消費者需求，找到這些問題的答案是愈來愈關鍵。鑒於愈趨增加的商業競爭壓力，連同成長的消費者期待且市場中有意義的產品差異的機會減少，找到這些問題的答案是關鍵的。此外，減低成本、增進效率與效能、及達到競爭壓力的需求更大大地增加了對於找到這些問題的答案的關鍵必要的迫切性。
已經思考過這些問題的解決方案許久，但是先前的發展並未教示或建議任何解決方案，而因此這些問題的解決方案已經長期困擾所屬技術領域中具有通常知識者。
本發明提供一種積體電路封裝系統的製造方法，包含：提供封裝基板；在該封裝基板上安裝具有貫穿之矽通孔的第一積體電路晶粒；將圓柱立柱耦合至鄰接該第一積體電路晶粒的該封裝基板；以及，在該第一積體電路晶粒與該圓柱立柱上安裝具有貫穿之矽通孔的第二積體電路晶粒，以在該第二積體電路晶粒、該第一積體電路晶粒、該封裝基板、或其組合之中形成電性連接。
本發明提供一種積體電路封裝系統，包含：封裝基板；第一積體電路晶粒，係具有貫穿之矽通孔且安裝在該封裝基板上；圓柱立柱，係耦合至鄰接該第一積體電路晶粒的該封裝基板；以及，第二積體電路晶粒，係具有貫穿之矽通孔且安裝在該第一積體電路晶粒與該圓柱立柱上，並在該第二積體電路晶粒、該第一積體電路晶粒、該封裝基板、或其組合之中提供電性連接。
本發明的一些實施例具有除上述提及的那些之外或代替上述提及的那些的其他步驟或元件。對於所屬技術領域中具有通常知識者而言，當閱讀下列詳細描述並參照所附圖式後，該等步驟或元件將變得顯而易見。
為了使所屬技術領域中具有通常知識者能夠製造與使用本發明，下列實施例是以足夠的細節來描述。應瞭解，基於本發明，其他實施例將是顯而易見的，且在不背離本發明的範疇下，可進行系統、製程、或機構的改變。
在下列描述中，將提供許多具體細節，以徹底瞭解本發明。然而，應明白，可不需這些具體細節來實施本發明。為了避免模糊本發明，將不詳細揭露一些習知的電路、系統組構、與製程步驟。
顯示系統實施例的圖式是部分圖解而非按照比例，特別是一些尺寸係為了清楚表示而在圖式中誇大顯示。同樣地，雖然圖式中的圖樣為了描述方便而一般顯示為相似的方向，但是圖式中的表示大部分是任意的。一般來說，本發明可操作在任何方向上。
在揭露與描述具有一些共同特徵的多個實施例之處，為了清楚與簡單地說明、描述及理解，彼此相同與相似的特徵通常將以相同的元件符號來描述。為了描述方便，實施例已經被標號成第一實施例、第二實施例等等，而並非意欲有任何其他意義或用以限制本發明。
為了說明的目的，在此使用的用語「水平的(horizontal)」係定義成平行於積體電路基板的平面或表面的平面，而不論其方向。用語「垂直的(vertical)」係參照至垂直於剛才定義的該水平的方向。例如「上方(above)」、「下方(below)」、「底部(bottom)」、「頂部(top)」、「側邊(side)」(如在「側壁(sidewall)中」)、「較高(higher)」、「較低(lower)」、「上面的(upper)」、「在…上方(over)」、與「在…之下(under)」的用語係相對於圖式中所顯示的該水平面來定義。用語「在…上(on)」意指在元件之間有直接接觸。
在此使用的用語「加工(processing)」包含形成所述結構所需的材料或光阻(photoresist)的沉積、圖案化、曝光、顯影、蝕刻、清潔、及/或該材料或光阻的移除。
現在參照第1圖，其顯示在本發明的實施例中的積體電路封裝系統100的剖視圖。該積體電路封裝系統100的剖視圖描述具有系統側104與元件側106的封裝基板102。可透過該封裝基板102將元件墊108耦合至系統互連110，可使用該系統互連110以將該積體電路封裝系統100電性連接至下一層級系統(例如印刷電路板)(未圖示)。
可將具有主動側觸點(contact)114與貫穿之矽通孔(through silicon via)116的第一積體電路晶粒112安裝在該元件側106上。該貫穿之矽通孔116使得可在該第一積體電路晶粒112的背側上取得來自該主動側觸點114的介面訊號。可藉由晶片互連118(例如焊料凸塊(solder bump)、焊料球(solder ball)、焊料柱(solder column)、或柱形凸塊(stud bump))將該貫穿之矽通孔116耦合至該元件墊108。該主動側觸點114的位置只是例子，且該第一積體電路晶粒112的主動側可朝向或遠離該元件側106。
在該第一積體電路晶粒112與該封裝基板102的元件側106之間可敷設黏著層(adhesive layer)120，例如預成形底填充材料或薄膜壓合形式的底填充材料(underfill material)。該晶片互連118可栓住(captive)在該黏著層120中並敷設為一單元以簡化該製造製程。
可將圓柱立柱(cylindrical stud)122(例如特定尺寸的焊料球)敷設至直接鄰接該第一積體電路晶粒112的元件墊108。該圓柱立柱122可為稍微在該第一積體電路晶粒112上方延伸的足夠尺寸且是實質相同於該主動側觸點114的高度。
可將具有貫穿之矽通孔126與晶片觸點128的第二積體電路晶粒124安裝在該第一積體電路晶粒112的主動側觸點114上。為了在該第二積體電路晶粒124與該系統互連110之間形成電性連接且不衝擊該第一積體電路晶粒112，在該第二積體電路晶粒124的貫穿之矽通孔126與該圓柱立柱122之間可耦合圓柱立柱觸點130。
因為該貫穿之矽通孔126提供至兩側的介面訊號，所以該晶片觸點128可耦合至該第二積體電路晶粒124的主動側或背側。藉由在組合前將第二黏著層132敷設至該第二積體電路晶粒124或藉由在組合期間的薄膜壓合製程，可以非流動製程敷設該第二黏著層132，例如預成形底填充材料或薄膜壓合形式的底填充材料。
可視需要地將模製封裝本體134(例如環氧樹脂模製化合物)形成在該封裝基板102的元件側106、該圓柱立柱122、該第一積體電路晶粒112、與該第二積體電路晶粒124上。為了在該系統互連110與該第二積體電路晶粒124之間形成額外的訊號連接而不衝擊該第一積體電路晶粒112，接合線136可視需要地將該第二積體電路晶粒124耦合至該元件墊108。
已經發現敷設鄰接該第一積體電路晶粒112的圓柱立柱122可提供用以支撐較大尺寸的該第二積體電路晶粒124的額外介面能力。單一列的該圓柱立柱122的附接(attachment)只是例子，而多列的該圓柱立柱122是可能的。該圓柱立柱122可大於標準焊料球，且它們敷設的方法(降球製程(ball drop process))容許特定尺寸的圓柱立柱122準確地置於該封裝基板102上。
現在參照第2圖，其顯示在本發明的第一替代實施例中的積體電路封裝系統200的剖視圖。該積體電路封裝系統200的剖視圖描述具有該系統側104與該元件側106的封裝基板102。透過該封裝基板102可將該元件墊108耦合至該系統互連110，可使用該系統互連110以將該積體電路封裝系統200電性連接至下一層級系統(例如印刷電路板)(未圖示)。
可將具有該主動側觸點114與該貫穿之矽通孔116的第一積體電路晶粒112安裝在該元件側106上。該貫穿之矽通孔116使得可在該第一積體電路晶粒112的背側上取得來自該主動側觸點114的介面訊號。可藉由晶片互連118(例如焊料凸塊、焊料球、焊料柱、或柱形凸塊)將該貫穿之矽通孔116耦合至該元件觸點。該主動側觸點114的位置只是例子，且該第一積體電路晶粒112的主動側可朝向或遠離該元件側106。
可將圓柱立柱122(例如特定尺寸的焊料球)敷設至直接鄰接該第一積體電路晶粒112的元件墊108。該圓柱立柱122可為稍微在該第一積體電路晶粒112上方延伸的足夠尺寸且是實質相同於該主動側觸點114的高度。
可將具有貫穿之矽通孔126與晶片觸點128的第二積體電路晶粒124安裝在該第一積體電路晶粒112的主動側觸點114上。為了在該第二積體電路晶粒124與該系統互連110之間形成電性連接且不衝擊該第一積體電路晶粒112，在該第二積體電路晶粒124的貫穿之矽通孔126與該圓柱立柱122之間可耦合圓柱立柱觸點130。
因為該貫穿之矽通孔126提供至兩側的介面訊號，所以該晶片觸點128可耦合至該第二積體電路晶粒124的主動側或背側。藉由在組合前將第二黏著層132敷設至該第二積體電路晶粒124或藉由薄膜壓合製程，可以非流動製程敷設該第二黏著層132，例如底填充材料。
可將具有該貫穿之矽通孔126的第三積體電路晶粒202安裝在該第二積體電路晶粒124上且電性連接至該第二積體電路晶粒124。為了在該兩個積體電路之間提供高速介面，可將該第三積體電路晶粒202的晶片觸點128耦合至該第二積體電路晶粒124的主動側觸點114。
可將具有該貫穿之矽通孔126的第四積體電路晶粒204安裝在該第三積體電路晶粒202上且電性連接至該第三積體電路晶粒202。為了在該兩個積體電路之間提供高速介面，可將該第四積體電路晶粒204的晶片觸點128耦合至該第三積體電路晶粒202的主動側觸點114。
可視需要地將模製封裝本體134(例如環氧樹脂模製化合物)形成在該封裝基板102的元件側106、該圓柱立柱122、該第一積體電路晶粒112、該第二積體電路晶粒124、該第三積體電路晶粒202、與該第四積體電路晶粒204上。為了在該系統互連110與該第四積體電路晶粒204之間形成額外的訊號連接而不衝擊該第一積體電路晶粒112、該第二積體電路晶粒124、或該第三積體電路晶粒202，該接合線136可視需要地將該第四積體電路晶粒204耦合至該元件墊108。
已經發現在本發明的積體電路晶粒之間提供高速電性互連也可藉由將該貫穿之矽通孔熱耦合至該封裝基板以提供貫穿該堆疊的有效熱路徑。這容許藉由縮減平均溫度以改進該堆疊中間的積體電路晶粒的可靠度。
現在參照第3圖，其顯示在本發明的第二替代實施例中的積體電路封裝系統300的剖視圖。該積體電路封裝系統300的剖視圖描述具有該系統側104與該元件側106的封裝基板102。透過該封裝基板102可將該元件墊108耦合至該系統互連110，可使用該系統互連110以將該積體電路封裝系統200電性連接至下一層級系統(例如印刷電路板)(未圖示)。
可將具有該主動側觸點114與該貫穿之矽通孔116的第一積體電路晶粒112安裝在該元件側106上。該貫穿之矽通孔116使得可在該第一積體電路晶粒112的背側上取得來自該主動側觸點114的介面訊號。可藉由晶片互連118(例如焊料凸塊、焊料球、焊料柱、或柱形凸塊)將該貫穿之矽通孔116耦合至該元件觸點。該主動側觸點114的位置只是例子，且該第一積體電路晶粒112的主動側可朝向或遠離該元件側106。
可將圓柱立柱122(例如特定尺寸的焊料球)敷設至直接鄰接該第一積體電路晶粒112的元件墊108。該圓柱立柱122可為稍微在該第一積體電路晶粒112上方延伸的足夠尺寸且是實質相同於該主動側觸點114的高度。
可將具有貫穿之矽通孔126與晶片觸點128的第二積體電路晶粒124以主動側對主動側的組構來安裝在該第一積體電路晶粒112的主動側觸點114上。為了在該第二積體電路晶粒124與該系統互連110之間形成電性連接且不衝擊該第一積體電路晶粒112，在該第二積體電路晶粒124的貫穿之矽通孔126與該圓柱立柱122之間可耦合圓柱立柱觸點130。
該第二積體電路晶粒124可大於該第一積體電路晶粒112很多。在此情況中，可提供額外列的圓柱立柱122以支撐該第二積體電路晶粒124且提供至該元件墊108的電性連接。本發明顯示為具有兩列的圓柱立柱122，但是這只是例子，且可視需要敷設任何數量列的圓柱立柱122。
現在參照第4圖，其顯示在本發明的實施例中的積體電路封裝系統的製造方法400的流程圖。該方法400包含：在方塊402中，提供封裝基板；在方塊404中，在該封裝基板上安裝具有貫穿之矽通孔的第一積體電路晶粒；在方塊406中，將圓柱立柱耦合至鄰接該第一積體電路晶粒的該封裝基板；以及，在方塊408中，在該第一積體電路晶粒與該圓柱立柱上安裝具有貫穿之矽通孔的第二積體電路晶粒，以在該第二積體電路晶粒、該第一積體電路晶粒、該封裝基板、或其組合之中形成電性連接。
所產生的方法、製程、設備、裝置、產品、及/或系統係直接了當的、有成本效益的、不複雜的、高度多用途的、且有效的，並可藉由改造已知技術來出人意外地和不明顯地實作，且因此是立即地適合於有效率地與經濟地製造完全相容於習知製造方法或製程與技術的積體電路系統。本發明的另一重要態樣是它大大地支持並幫助降低成本、簡化系統、及增進效能的歷史趨勢。
本發明的這些與其他有價值的態樣因此促進該技術的狀態至至少下一層級。
雖然本發明已經結合具體最佳模式來描述，但是應瞭解的是，對於所屬技術領域中具有通常知識者而言，按照先前的描述，許多替代、修改、與變化型式將是顯而易知的。據此，本發明是要涵蓋落入所附申請專利範圍之範疇內的所有此種替代、修改、與變化型式。在此提出或在所附圖式中顯示的所有內容應解讀成說明及非限制的意思。
100、200、300．．．積體電路封裝系統
102．．．封裝基板
104．．．系統側
106．．．元件側
108．．．元件墊
110．．．系統互連
112．．．第一積體電路晶粒
114．．．主動側觸點
116、126．．．貫穿之矽通孔
118．．．晶片互連
120．．．黏著層
122．．．圓柱立柱
124．．．第二積體電路晶粒
128．．．晶片觸點
130．．．圓柱立柱觸點
132．．．第二黏著層
134．．．模製封裝本體
136．．．接合線
202．．．第三積體電路晶粒
204．．．第四積體電路晶粒
400．．．方法
402、404、406、408．．．方塊
第1圖係在本發明的實施例中的積體電路封裝系統的剖視圖；
第2圖係在本發明的第一替代實施例中的積體電路封裝系統的剖視圖；
第3圖係在本發明的第二替代實施例中的積體電路封裝系統的剖視圖；以及
第4圖係在本發明的實施例中的積體電路封裝系統的製造方法的流程圖。
100．．．積體電路封裝系統
102．．．封裝基板
104．．．系統側
106．．．元件側
108．．．元件墊
110．．．系統互連
112．．．第一積體電路晶粒
114．．．主動側觸點
116、126．．．貫穿之矽通孔
118．．．晶片互連
120．．．黏著層
122．．．圓柱立柱
124．．．第二積體電路晶粒
128．．．晶片觸點
130．．．圓柱立柱觸點
132．．．第二黏著層
134．．．模製封裝本體
136．．．接合線

Claims (10)

  1. 一種積體電路封裝系統的製造方法，包括：提供封裝基板；在該封裝基板上安裝具有貫穿之矽通孔的第一積體電路晶粒；將圓柱立柱耦合至鄰接該第一積體電路晶粒的該封裝基板；在該第一積體電路晶粒與該圓柱立柱上安裝具有貫穿之矽通孔的第二積體電路晶粒，以在該第二積體電路晶粒、該第一積體電路晶粒、該封裝基板、或其組合之中形成電性連接；以及形成圓柱立柱觸點，該圓柱立柱觸點耦合至該第二積體電路晶粒上的該貫穿之矽通孔，以耦合該圓柱立柱。
  2. 如申請專利範圍第1項所述的積體電路封裝系統的製造方法，進一步包括耦合該第二積體電路晶粒上的晶片觸點與該第一積體電路晶粒上的主動側觸點，以形成該電性連接。
  3. 如申請專利範圍第1項所述的積體電路封裝系統的製造方法，進一步包括將系統互連連接至該封裝基板，該系統互連係電性連接於該圓柱立柱觸點。
  4. 如申請專利範圍第1項所述的積體電路封裝系統的製造方法，進一步包括在該第一積體電路晶粒與該第二積體電路晶粒之間敷設黏著層。
  5. 如申請專利範圍第1項所述的積體電路封裝系統的製造方法，進一步包括：在該封裝基板與該第二積體電路晶粒之間耦合接合線；以及在該封裝基板、該第一積體電路晶粒、該圓柱立柱、該第二積體電路晶粒、與該接合線上形成模製封裝本體。
  6. 一種積體電路封裝系統，包括：封裝基板；第一積體電路晶粒，係具有貫穿之矽通孔且安裝在該封裝基板上；圓柱立柱，係耦合至鄰接該第一積體電路晶粒的該封裝基板；第二積體電路晶粒，係具有貫穿之矽通孔且安裝在該第一積體電路晶粒與該圓柱立柱上，並在該第二積體電路晶粒、該第一積體電路晶粒、該封裝基板、或其組合之中提供電性連接；以及圓柱立柱觸點，該圓柱立柱觸點耦合至該第二積體電路晶粒上的該貫穿之矽通孔，以耦合該圓柱立柱。
  7. 如申請專利範圍第6項所述的積體電路封裝系統，進一步包括晶片觸點，係位於該第二積體電路晶粒上且耦合至該第一積體電路晶粒上的主動側觸點，以提供該電性連接。
  8. 如申請專利範圍第6項所述的積體電路封裝系統，進一 步包括系統互連，係連接至該封裝基板，且該系統互連係電性連接於該圓柱立柱觸點。
  9. 如申請專利範圍第6項所述的積體電路封裝系統，進一步包括黏著層，係位於該第一積體電路晶粒與該第二積體電路晶粒之間。
  10. 如申請專利範圍第6項所述的積體電路封裝系統，進一步包括：接合線，係位於該封裝基板與該第二積體電路晶粒之間；以及模製封裝本體，係位於該封裝基板、該第一積體電路晶粒、該圓柱立柱、該第二積體電路晶粒、與該接合線上。
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