WO2000019514A1 - Boitier de semiconducteur et procede correspondant de soudage de puce - Google Patents

Boitier de semiconducteur et procede correspondant de soudage de puce Download PDF

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Publication number
WO2000019514A1
WO2000019514A1 PCT/JP1998/004337 JP9804337W WO0019514A1 WO 2000019514 A1 WO2000019514 A1 WO 2000019514A1 JP 9804337 W JP9804337 W JP 9804337W WO 0019514 A1 WO0019514 A1 WO 0019514A1
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WO
WIPO (PCT)
Prior art keywords
bonding
chip
substrate
bumps
semiconductor chip
Prior art date
Application number
PCT/JP1998/004337
Other languages
English (en)
Japanese (ja)
Inventor
Ryouichi Kajiwara
Masahiro Koizumi
Toshiaki Morita
Kazuya Takahashi
Asao Nishimura
Kunihiro Tsubosaki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to CN98814031A priority Critical patent/CN1299518A/zh
Priority to KR1020007003151A priority patent/KR20010030703A/ko
Priority to PCT/JP1998/004337 priority patent/WO2000019514A1/fr
Publication of WO2000019514A1 publication Critical patent/WO2000019514A1/fr

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Definitions

  • the present invention relates to a semiconductor package having a structure in which a semiconductor chip such as an LSI chip is mounted on a carrier substrate made of an organic material.
  • solder bumps are formed on the A1 electrode pad on the chip side via a barrier metal, and the connection terminals on the board side are plated with Au with good solder wettability to achieve a fluxless, non-oxidizing atmosphere. This is a method in which solder is reflowed and joined. If the substrate is a ceramic substrate, use it in a hermetically sealed state.If the substrate is an organic substrate, fill it with a resin and silicon compound whose thermal expansion coefficient is adjusted between the chip and resin. Used with increased reliability of solder joints.
  • thermocompression bonding and thermocompression bonding using ultrasonic waves have been known as flip chip bonding of Au bumps and Au pads without using solder.
  • Conventional thermocompression bonding conditions are a heating temperature of 350 ° C, a load of 150 to 250 g Z bumps, and chips with less than 50 bumps are bonded.
  • a chip having a heating temperature of 200 ° C., a load of 300 g and approximately 6 bumps is bonded.
  • the carrier substrate is made of ceramic.
  • the load is reduced by increasing the heating temperature, but it still requires 150 g Z bumps.
  • the heating temperature is reduced to 200 ° C in thermocompression bonding with ultrasonic waves.
  • the load is as high as 300 g Z bump. This is a condition that has been studied and found in order to reliably join AuZAu in the atmosphere.Because the joining becomes unstable at lower temperatures and load conditions, it is not suitable for actual product assembly. Not applicable.
  • the crimped shape of the Au bump is a junction having a shape that is largely crushed with a typical size of 15 to 25 tm in thickness and a diameter of 15 O ⁇ m or more.
  • connection method As another conventional Au bump connection method, there is also known a connection method in which a conductive resin is used as an adhesive and heated and pressed between the two. In this method, a predetermined long-term reliability is obtained by filling and solidifying the resin between the chip and the substrate.
  • a method to cope with this is to mount the electrode terminals of the chip by arranging them in an elliptical manner over the entire surface of the chip.
  • the solder bump bonding method (C 4) which has already been adopted in the field of conventional large computers, can solve the above two problems, but when applied to semiconductor packages, there is a problem in terms of soldering temperature. appear.
  • large-scale computers use high-melting-point solder (95 Pb-15Sn solder with a melting point of 300 ° C) because of the necessity of performing subsequent layer soldering for the chip soldering material.
  • the soldering temperature is higher than the melting point of the solder.
  • solder having a solidus temperature in the range of 200 ° C to 240 ° C the solder joints inside the package will be partially removed during the eutectic soldering process of mounting the semiconductor package on the wiring board. Problems such as re-melting and defective disconnection occur. In other words, in the internal connection of the semiconductor package, a connection part having a heat resistance of 250 ° C. or more must be realized at a low connection temperature of 250 ° C. or less.
  • This bonding method is a method in which Au, which has a high melting point and excellent bonding properties, is formed into a bump shape and pressed in a solid phase using heating or ultrasonic waves. You can get it.
  • the conventional Au bump bonding method requires a bonding load of 300 g per bump, and a chip of about 100 to 2000 bumps is actually considered.
  • the load applied to the tool is 30 to 600 kg, and chipping or cracking of the chip due to one-sided contact of the press tool becomes a serious problem.
  • the maximum load that can be applied to the chip is empirically estimated to be about 20 to 40 kg, reliable bonding must be performed under the condition that the bonding load per bump is 20 to 80 g. If so, practical application is difficult.
  • the bonding temperature can be increased by the conventional thermocompression bonding method, reliable bonding can be achieved under low load conditions. The temperature cannot be raised to more than 250 ° C even for mid-air and 200 ° C for epoxy.
  • Ultrasonic thermocompression bonding which enables reliable bonding with low heating temperature and relatively low load, requires high ultrasonic energy to obtain a reliable joint. Therefore, there is a problem that the chip is damaged.
  • the method using the Au bump and the conductive resin is a method of performing pressure bonding with a low heating temperature and a low bonding load as connection conditions, so that the connection can be performed with a small deformation of the bump.
  • a resin is filled between the chip and the substrate in advance in the connection step and then pressure-bonded, it is possible to assemble a good package free of voids and the like.
  • a conductive resin there is a reliability problem that the contact state of the conductive particles deteriorates due to volume expansion due to moisture absorption, and the resistance increases with time.
  • the bonding temperature in the conventional technology is 70 ° C or more in view of the improvement of the bonding property by desorption of adsorbed molecules and interface diffusion, and 200 ° C
  • the shape after crimping is used as the aspect ratio (height Z diameter ratio).
  • the thermal strain of the joined body when the joining temperature is assumed to be 70 ° C is roughly estimated.
  • the Young's modulus of each member is as follows: Si: 190 GPa, Au pump: 88 GPa, polyimide substrate
  • the bump height when the bonding temperature is 70 ° C, the bump height must be 50 m or more even if the bump has sufficient bonding strength. A height of at least 8 O zm is required. If the bonding strength between the Au bump and the chip or substrate is weak, a higher bump height is required. For this reason, the Au bump height is the minimum height at which the Au bump is not damaged by thermal contraction after bonding, that is, the crimping diameter when the bump height is 50 ⁇ m when the bonding temperature is 70 ° C. : 500 ⁇ m or more, and when the bonding temperature is 200 ° C. and the bump height is 80 tm, the pressure bonding diameter is 400 im or more. For this reason, it has been difficult to reduce the bump pitch to 500 ⁇ m or less in consideration of the variation in the crimping diameter and the variation in the shape. Disclosure of the invention
  • Another object of the present invention is to provide a mounting structure which does not cause a problem of joint damage due to thermal strain in a cooling process after bonding the organic carrier substrate to the substrate when mounting at an wafer level. Providing a mounting structure that can reduce the pitch, and providing a low-cost package mounting method at the wafer stage. To provide.
  • the substrate and the chip are formed by using Au bumps arranged in an area as an intermediate material.
  • the structure is such that metal is firmly joined and the gap between the two is filled with resin.
  • the material composition of the flip chip bonding surface is assumed to be AuZAu, the cleanliness of the bonding surface is specified, and the water content is determined by the water vapor partial pressure: l OOP Heat-weld or heat-weld by applying scrubbing or weak ultrasonic vibration in a dry atmosphere of a or less. According to this bonding method, the semiconductor package according to the present invention can be manufactured.
  • Au has a strength of about 14 to 25 kg / 2 and is a material that does not harden due to work, so its fatigue life is at least one order of magnitude longer than that of solder materials. Bonding improves the package's temperature cycle reliability. However, if the Au bumps are not severely crushed, a reliable joint with sufficient joint strength cannot be obtained.Therefore, there is the problem of chip damage due to joining load and ultrasonic vibration, There is a problem when the gap between the holes becomes too narrow and the resin cannot be sufficiently filled. For this reason, it is difficult to apply Au bumps to a semiconductor package using an organic substrate.
  • FIG. 12 shows the bonding results when the Au pole was ultrasonically bonded to the Au deposited film at a heating temperature of 100 ° C. in the case where the bonding atmosphere was in the air or in nitrogen.
  • the joining load is 50 g.
  • the horizontal axis indicates the ultrasonic output, and the vertical axis indicates the ratio at which the bonding strength becomes 16 g or more.
  • Bonding success rate 100% ultrasonic output is obtained.
  • the ultrasonic output is 0 mW, that is, bonding can be performed only with load, and it cannot be cleaned in nitrogen. At least at 1.4 mW, it reaches 100%.
  • a bonding success rate of 100% can be obtained even with purification at 15 mW, and if not, 151 mW is required.
  • bonding in a nitrogen atmosphere to a surface that is not cleaned has better re-bonding properties than cleaning and bonding in the air.
  • Figure 13 shows the results of an Auger analysis of the surface contamination. The untreated sample is clearly contaminated with organic matter and S, and the Au concentration on the surface is as low as 33 atomic%.
  • the sample subjected to the surface cleaning treatment has a low contamination level even when exposed to nitrogen or the atmosphere, and maintains a high Au concentration of 55 to 61 atomic% on the surface as compared with the untreated one. ing.
  • a u In welding the bonding properties are not determined only by the surface contamination level, and the influence of the atmospheric gas is large.
  • Fig. 14 shows the gas composition of the atmosphere (air). Oxygen and moisture can be considered as gases that affect the bondability. Therefore, an atmosphere containing these gases was created and bonding was performed in the atmosphere, and the bonding properties were compared.
  • Fig. 15 shows the results of bonding when Ar gas was bonded to a gas containing oxygen or moisture in an atmosphere of air and nitrogen. The shaded area is the ultrasonic output area where the bonding success rate: 100% can be obtained. Oxygen did not affect the bonding at all, indicating that the moisture was poor. Fig.
  • 16 shows the relationship between the water content in the atmospheric gas and the minimum ultrasonic output that gives a bonding success rate of 100%.
  • the water content is in the range of about 0.03 to 0.1 vo 1%, and the bondability rapidly deteriorates. That is, if the moisture content in the atmosphere is 0.03 to 0.1 vol% or less, a surface cleaning treatment is performed to obtain a bonding temperature of 100 ° C and a bonding load of 50 ° C. Under low temperature and low load conditions of g, the Au pole and Au pad can be crimped to a joint strength of 16 g or more. From these results, it is clear that control of moisture in the bonding atmosphere is very important in Au bonding. If the moisture control is sufficient, sufficient bonding strength can be obtained by cleaning the Au bonding surface so that the Au concentration becomes 20 atomic% or more.
  • the chip on which the Au bump is formed can be used as the Au pad or Au bump on the organic substrate.
  • Load ⁇ 50 bumps, Bonding temperature: 100 to 200 ° C suppresses bump deformation and provides high strength It becomes possible to join to.
  • an Au bump ZA u pad bonding method with controlled surface cleaning and atmosphere it is possible to house ultra-high pin count or high speed operation LSI chips and maximize their chip performance. And a package structure with high long-term reliability of the joint can be realized.
  • the semiconductor package can be assembled with good productivity and a good yield.
  • Figures 17 and 18 show the results of a reliability test conducted by assembling a semiconductor package using this method.
  • Fig. 17 shows the temperature cycle test results of packages with various Au bump heights. The tip size ranges from 5 thighs to 10 mm square. There is clearly a correlation between the bump height and the rupture life, and the practically required life of more than 100 times is about 5 ⁇ or more in bump height.
  • Fig. 18 shows the results of examining the relationship between the bump joint strength and the rate of breakage when solder reflow is repeated. At a bump strength of 20 g, fracture is observed with a small probability. Therefore, from the viewpoint of package reliability, it is desirable that the bump height is 5 or more and the bump strength is 30 g or more.
  • joining can be performed at a joining temperature of 70 ° C. to 100 ° C. with a small crushing rate as shown in FIG.
  • the strain between the Si wafer and the carrier substrate is about 60 m under the model conditions in FIG. 19, and there is a relationship between the bump height and the main strain as shown in FIG.
  • the bonding temperature is 70 ° C. and the bump height is 50 m
  • the main strain is about 3%, and a stress of 13 to 20 kg / mm 2 is generated. If the bonding interface strength of the Au bump is lower than this value, it will break at the interface, so the bonding strength must be sufficiently high.
  • the bump crush rate must be increased to 50% or more.
  • the bump diameter becomes 420 ⁇ m, making it difficult to achieve a pitch of 500 ⁇ m or less.
  • bonding can be achieved with a crush ratio of 22% and an aspect ratio of 0.52.
  • a bump height of 50 m can be realized with a crimping diameter of 10 ⁇ m ⁇ . That is, bonding at a pitch of 200 ⁇ m is possible.
  • the bump diameter to 200 ⁇ and the bump height to 100 >> 1
  • the distortion can be reduced to 0.3% and the stress generated in the bump is 2.6.
  • kg / mm 2 suppresses deformation within the elastic range, so there is no risk of breakage of the joint.
  • the present invention has been made on a cleaning method for the Au surface and a bonding atmosphere in consideration of the water content of the bonding atmosphere, which will be described later in detail. Then, according to the bonding method of the present invention, the following novel semiconductor packages can be obtained.
  • the electrode terminals of the semiconductor chip and the internal connection terminals of the organic substrate are connected via an Au bump with a diameter of 300 ⁇ or less, a height of 50 ⁇ or more and a height ratio of 1/5 or more.
  • Au bump with a diameter of 300 ⁇ or less, a height of 50 ⁇ or more and a height ratio of 1/5 or more.
  • the semiconductor chip and the plurality of internal connection terminals of the organic substrate are flip-chip bonded via Au bumps with a pitch of 400 m or less, and the area of the external connection terminal and the internal connection terminal on the organic substrate are connected.
  • the area is divided by slits, and the external connection terminal and the internal connection terminal are connected by wiring passing through the slit Semiconductor package.
  • the semiconductor chip and the plurality of internal connection terminals arranged in an area on the organic substrate are joined face-down via Au bumps, and the area of the internal connection terminal and the area of the external connection terminal are connected. Is a semiconductor package that overlaps on the projection surface.
  • a plurality of semiconductor chips having electrode terminals and arranged with a gap of 1 mm or less and a plurality of internal connection terminals of the organic substrate are connected via Au bumps, and the external connection terminals of the organic substrate are connected to the liquid.
  • FIG. 1 is an embodiment of a sectional structure of a semiconductor package according to the present invention.
  • FIG. 2 is a diagram showing an Au bump shape.
  • FIG. 3 is another embodiment of the sectional structure of the semiconductor package according to the present invention.
  • FIG. 4 is another embodiment of the sectional structure of the semiconductor package according to the present invention.
  • FIG. 5 is a plan view of an organic carrier substrate used for the semiconductor package of FIG.
  • FIG. 6 is an embodiment of a cross-sectional structure of a multi-chip semiconductor package according to the present invention.
  • FIG. 7 is an example of a joining procedure showing a joining method of a chip and a carrier substrate according to the present invention.
  • FIG. 8 is an embodiment of an apparatus configuration for realizing the joining method of FIG.
  • FIG. 9 shows another joining method of a chip and a carrier substrate according to the present invention. Example procedure.
  • FIG. 10 is an embodiment of an apparatus configuration for realizing the joining method of FIG. 9.
  • FIG. 11 is an embodiment of an apparatus configuration of the pretreatment chamber and the joining chamber of FIG. Figure 12 shows the experimental results showing the effect of the nitrogen and atmospheric bonding atmosphere on the bonding results.
  • Fig. 13 shows Auger analysis results showing the contamination on the joint surface.
  • Fig. 14 shows the gas composition in the atmosphere.
  • Fig. 15 shows the experimental results showing the effect of various bonding atmospheres on the bonding results.
  • Fig. 16 shows the experimental results showing the effect of the moisture content of the bonding atmosphere on the bonding results.
  • FIG. 17 is a result of a temperature cycle test of the semiconductor package according to the present invention.
  • FIG. 18 is a result of a repeated solder reflow test of the semiconductor package according to the present invention.
  • Figure 19 shows a model of a semiconductor package.
  • Figure 20 shows the relationship between bump height and distortion.
  • Fig. 21 shows the relationship between the crushing rate and the joint strength.
  • FIG. 1 shows a sectional structure of a semiconductor package according to the present invention.
  • Au bumps 7 are formed on A 1 or Au electrode pads 2 of semiconductor chip 1 (hereinafter referred to as chip 1) by pole bonding.
  • the organic carrier substrate includes an organic insulating plate 3, an internal connection terminal 4 provided on one surface of the organic insulating plate 3, an external connection terminal 5 provided on the back surface of one surface, and an external connection terminal 5
  • the plating resist covering the insulating plate surface around the It is composed of
  • the internal connection terminals 4 and the external connection terminals 5 are formed by Cu plating or a method of attaching and etching Cu foil, and the connection terminals are electrically connected by through holes provided in the organic insulating plate 3 and wiring. It is connected to.
  • connection terminal is provided with Ni or Pd plating on the base and then Au plating on the outermost surface.
  • the Au bumps 8 are formed on the internal connection terminals 4 of the carrier board by pole bonding, and are aligned with the Au bumps 6 of the chip 1 so that the Au bumps come into contact with each other.
  • the atmosphere is evacuated to 1 Pa or less and heated to 15 O to 250 ° C to perform pressure bonding.
  • the load is 30 to 80 g Z bump, and the joining is performed by controlling the amount of displacement so that the bump is not crushed too much.
  • Fig. 2 shows the initial Au bump shape formed by pole bonding.
  • the tip-side pole bump shape (A) has a crimp diameter D c of 110 soil 10 m, a shoulder height H c at which the tip surface of the kyecuring tool is in contact is 25 ⁇ 5 ⁇ , Select the discharge and bonding conditions and the shape of the drilling tool so that the height Dh of the raised part at the center of the bump is 50 m and the height Hh of that part is 50 m at 10 m. ing.
  • the bonding strength is 80 g or more in shear strength.
  • the shape of the pole bump on the substrate side (B) is such that the deformation of the pole is smaller than on the chip side and the shoulder height Hk is as high as about 40 ⁇ 10 m. I have.
  • pole bonding in this case, the bonding terminal surface of the board is sputter-cleaned immediately before bonding in order to improve the bondability.
  • the bonding strength is 50 g or more in shear strength.
  • the shape of both bumps after crimping is controlled by controlling the amount of crushing of the bumps by controlling the amount of displacement so that the bumps are metallically joined at the raised portion at the center of the bumps. ing.
  • the most constricted part of the joined bump pillars is formed at the joint between the bumps, and in terms of strength, The bonding interface is the lowest.
  • the height H between the chip and the substrate is about 70 ⁇ 10 m.
  • the resin 9 with high fluidity is removed. It is poured and cured, and finally, solder bumps 10 are formed on the external connection terminals to complete the package.
  • the following effects are obtained. 1) Since the A1 electrode pad of the chip and the internal connection terminal of the organic carrier substrate are connected by the flip-chip bonding method, the pads are arranged in an area even for multi-pin LSI chips.
  • the pad pitch can be reduced and bonding can be performed, and it can be mounted on a semiconductor package.
  • the chip and the organic carrier substrate are electrically connected at the shortest distance, a package with a high transmission speed can be configured, and a package that can fully exploit the performance of high-speed processing LSI chips can be realized. .
  • the connection is completed within the chip projection area by the face down, a plurality of chips can be mounted close to each other. Therefore, in a multi-chip package, the knock size can be significantly reduced. Also, since the heat resistance of the joints in the package is the same as that of the conventional Au wire bonding type package, it can be mounted on a wiring board with the same solder reflow opening as before.
  • FIG. 3 shows a cross-sectional structure of a semiconductor package according to another embodiment of the present invention.
  • the organic carrier substrate is patterned with polyimide tape 13 with openings, and the internal and external connection terminals 14 are used as internal and external connection terminals on the front and back surfaces of the same Cu land.
  • a tape substrate is used.
  • Ni plating is applied to the base and Au plating is applied to the outermost surface.
  • Au bumps 16 are formed on the internal connection terminals on the opening side, and are joined to Au bumps 15 formed on A 1 or Au electrodes 12 of the LSI chip 11. .
  • the method of joining Au bumps is as follows.
  • the Au bump surface on the substrate side is cleaned by an Ar sputter, and the substrate is carried into a bonding chamber in a dry atmosphere having a water vapor partial pressure of 100 Pa or less without being exposed to the air.
  • the chip on which the Au bumps are formed is heated in a vacuum chamber to remove adsorbed moisture, and then carried into the bonding chamber.
  • the two Au bumps are aligned in the joining chamber, the chip is mounted on the substrate with a face-down, and heated and pressed with a joining tool from the chip side, and several scrubs or ultrasonic waves of 5 to 10 m are performed. Join by applying vibration.
  • the chip and the tape substrate have the same dimensions, and the joining portion is entirely housed inside the chip surface on the projection surface.
  • the present embodiment is suitable for the case of 200 pins or less.
  • FIG. 4 shows a cross-sectional structure of another semiconductor package according to the present invention.
  • FIG. 5 is a plan view of the organic carrier substrate used in FIG.
  • the organic carrier substrate is a tape substrate composed of a polyimide tape 23 and a Cu foil pattern adhered to the tape and etched.
  • the polyimide tape has an opening at the boundary between the external connection terminal area and the internal connection terminal area 24 and the external connection terminal area 25.
  • the slit 29, which is the latter opening, is large enough that the distortion of the tape in the internal connection area is not transmitted to the external connection area.
  • the Cu foil pattern is composed of internal and external connection terminals 26 and 27 and a wiring portion 28 passing through a slit 29.
  • the Au bumps 30 formed on the Au-plated internal connection terminals 26 and the electrode terminals 22 of the chip 21 are metallically joined.
  • the bonding method is as follows. First, the surface of the internal connection terminals of the tape substrate is cleaned by sputtering with Ar ions, the chip is positioned and mounted in a dry atmosphere with a water vapor partial pressure of 100 Pa or less, and the overall temperature is reduced. Heating is performed at 200 ° C, and pressure is applied from the chip side and ultrasonic vibration is applied to perform pressure bonding. On the chip mounting side of the external connection terminal area, a reinforcing plate 31 having the same thermal expansion coefficient as the wiring board on which the package is mounted is adhered with an adhesive 32.
  • Highly fluid resin 33 is poured between the chip and the substrate and solidified.
  • an underlining material is used so that the resin does not leak from the slit portion 29, and the slit portion is also solidified with the resin. Therefore, the wiring passing through the slit is covered and protected by the resin.
  • an ultra-high number of electrode terminals having more than 150 pins are used, and the SI chip is securely connected to the terminals of the tape substrate with a material having a high melting point, a long fatigue life and a high environmental resistance. Because it can be rip-chip bonded, it is possible to assemble an ultra-high-pin-count, ultra-high-speed processing LSI chip into a plastic package with low cost and high reliability when mounted on a wiring board. Further, when the package according to the present embodiment is mounted on a wiring board, thermal distortion due to a difference in thermal expansion between the chip and the carrier board is cut off by the slit portion, and thermal expansion of the external connection terminal area is prevented. The rate is almost the same as the coefficient of thermal expansion of the wiring board. Therefore, no large thermal stress is generated in the solder bump connection part, and the temperature cycle life of the solder bump connection part becomes very long.
  • FIG. 6 shows a cross-sectional structure of an embodiment in which the present invention is applied to a multi-chip package in which a plurality of chips are closely arranged with a gap of 1 mm or less.
  • an internal connection terminal 44, an external connection terminal 45, and a wiring pattern are formed on each surface of the module substrate 43.
  • Internal connection terminals Au bumps are made by applying thick Ni plating 47 on the ground and forming Au plating 48 on it.
  • Au stud bumps 46 are formed on the A1 electrode pads 42 of the chip 41 by a wire bonding method.
  • the bonding of Au bumps is performed by cleaning the surface of the Au bumps on the substrate side by sputter cleaning, transporting it to a bonding chamber filled with an air-tight and dry atmosphere gas without exposing it to the air, Au bumps are heat-treated in vacuum to remove adsorbed moisture and organic matter, are aligned and faced, and are joined by applying heat, pressure and scrub vibration. A plurality of chips are joined to the module substrate, and a resin 49 is filled between the chip substrates. Solder bumps 50 with a liquidus temperature of 190 ° C. or higher are formed on the back surface of the module substrate for connection to the motherboard. As an external connection mechanism, a structure in which a lead terminal is used instead of a solder bump and the lead terminal is soldered to a mother board may be used.
  • connection between the module substrate and the chip is a metal joint between Au bumps having high strength, the temperature cycle reliability of the internal connection portion is high, and the connection portion having heat resistance is used. Therefore, there is an effect that there is no restriction on a heating temperature in soldering to a mother node.
  • FIG. 7 shows a joining procedure of the joining method according to the present invention.
  • Au bumps formed by the pole wire bonding method are characterized by high Au purity of the bump material, softness, and high cleanliness of the bump surface because bumps can be formed in the process immediately before flip chip bonding. For this reason, the surface cleaning treatment of both can be omitted, and the chip is placed on the carrier substrate under atmospheric pressure. Then, the surrounding atmosphere is evacuated to a vacuum of 100 Pa or less and heated, and moisture and organic substances adsorbed on the bump surface are separated and pressure-bonded. At this time, the bonding strength can be easily improved by performing scrubbing with an amplitude: several to several tens ⁇ m a plurality of times together with the pressurization, or by applying ultrasonic vibration.
  • the chip is positioned by setting the substrate and chip in a bonding apparatus in the atmosphere, and after positioning, a load of about several g or less per bump is applied to the chip with a pressing jig. By doing so, displacement between the chip and the substrate during pressurization can be prevented, and the bonded area exposed to the vacuum atmosphere can be increased as much as possible to promote the detachment of the adsorbed material.
  • the substrate with the chips is taken out into the atmosphere, liquid resin is allowed to penetrate between the chip substrates, bubbles are removed, and the resin is cured by heating. After that, apply flux to the Au-plated external connection terminals on the back of the carrier board, mount the solder poles, and reflow the solder by heating to form solder bumps.
  • FIG. 8 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG.
  • the upper chamber 54 and the lower chamber 51 for evacuation closely contact each other via the 0-ring 61.
  • a pressing jig / vacuum flange 55 for applying pressure to the chip 68 is hermetically integrated via a bellows 56.
  • a cylinder 62 fixed to a support arm 53 is disposed above the flange, and the piston 75 is attached to the flange to control the vertical movement of the flange.
  • the upper chamber can move up and down independently of the movement of the flange, and is controlled by a drive mechanism 63 attached to the support arm.
  • the relative movement distance between the upper chamber and the flange is designed to be 20 mm or more.
  • the structure is such that the upper chamber can be pulled up while a low load is applied to it, and the position confirmation force camera can be inserted into the chamber.
  • the heat stage 57 for supplying and setting the semiconductor chip 68 and the carrier substrate 70 in a state where the Au bump 69 and the Au pad 71 are in contact with each other has a heater 60 inside. Further, a stage drive mechanism 59 is provided for driving the stage left and right by a small amount.
  • the heat stage is supported by a pairing 58 that has the role of supporting movement and joining load.
  • the size of the space to be evacuated is designed to be the smallest size that can accommodate the chip and the substrate, and the evacuation pump 64 is designed so that the evacuation time to 10 to rr or less is 20 seconds or less. Is selected. N 2 gas 66 is used as the leak gas for returning the chamber to atmospheric pressure.
  • the joining mechanism is arranged outside the vacuum chamber so that only the periphery of the joining sample can be evacuated, so that it is necessary for the joining to be performed under atmospheric pressure before joining.
  • the time required to obtain a vacuum atmosphere is greatly reduced, and a single bonding process such as alignment of substrate and chip ⁇ evacuation ⁇ pressure bonding ⁇ atmospheric leak can be performed in less than one minute.
  • the joining method according to the present invention can be applied to mass production.
  • a scrub of several ⁇ can be applied from the substrate side during the pressure bonding process, the bonding strength can be increased with a low load, and the possibility of chip damage can be further reduced. There is also an effect.
  • FIG. 9 shows another joining procedure of the joining method according to the present invention.
  • the Au pad or Au bump formed by plating is expensive in terms of cost if it is formed thicker than several ims, and must be manufactured with a thickness of 1 ⁇ or less. is there.
  • the Au plating is thin, the Au deformation of the pad is so small that the surface contamination level has a large effect on the bonding. This Therefore, in the procedure shown in the figure, the Au pad surface on the substrate side is cleaned by sputter cleaning, and the Au bump surface on the chip side is only heated in vacuum to remove adsorbed moisture.
  • FIG. 10 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG.
  • the basic configuration of the equipment consists of a pretreatment chamber 81 for cleaning the pad surface of the substrate, a chip supply chamber 83 for supplying a semiconductor chip with vacuum heating and supplying it to the bonding chamber described later, and aligning the substrate and the chip.
  • a substrate unloading room 86 to take out a substrate with chips from the bonding room 86, airtight pretreatment room, bonding room, and chip supply room
  • a dry gas supply mechanism 85 for supplying dry gas to the substrate unloading chamber
  • a vacuum exhaust system 64 for evacuating each chamber to a vacuum
  • a substrate supply mechanism 87 for supplying substrates to the pretreatment chamber.
  • the chambers are connected by gate valves 88, 89, 90 to transfer substrates or chips.
  • the drying gas may be any gas such as air, nitrogen and argon, as long as the partial pressure of water vapor is 100 Pa or less, regardless of oxidizing or non-oxidizing.
  • FIG. 11 is an embodiment showing an apparatus configuration of the pretreatment chamber and the bonding chamber in FIG. 10. It is.
  • the pretreatment chamber 100 is provided with a mechanism for sputtering the carrier substrate 129 with Ar ions.
  • the cathode electrode 107 is electrically insulated from the device by an insulating member 108, and a cathode electrode 106 having the same potential as the ground is arranged on the upper portion.
  • the substrate is set on a force source electrode, the chamber is evacuated to a vacuum, then Ar gas is introduced, and a high frequency voltage superimposed with a DC component is applied between the electrodes from a high frequency power source 109. To generate a glow discharge between the electrodes.
  • the bonding chamber contains a substrate transfer mechanism 127, a camera 125, its drive system 126, an XY movable stage 124, a positioning mechanism consisting of a controller 123, and a pressurizing mechanism 118.
  • a joining mechanism consisting of a support arm 121, an ultrasonic vibration mechanism 1 19, a joining tool 120, and a controller 122, a chip supply (not shown) that transports the chip 13 1 to the joining tool A mechanism is provided.
  • the bonding chamber is evacuated once, and dried nitrogen gas is introduced to near atmospheric pressure to maintain a dry atmosphere at normal pressure.
  • the substrate 130 is mounted on a heat stage 128 having a built-in heating mechanism.
  • the tip 13 1 is chucked to the joining tool by vacuum suction.
  • the camera is inserted between the chip and the substrate, and the position of the Au bump on the chip and the Au pad on the substrate are checked while aligning with the XY movable stage.After moving the camera, the chip is lowered by the pressure mechanism. It moves and joins by applying pressure and ultrasonic waves.
  • the surface is physically etched with Ar ions.
  • Chip side This greatly improves the bondability with the Au bump, and provides a highly reliable, high-strength joint.
  • the atmosphere in the joining chamber is a dry, normal-pressure nitrogen gas atmosphere with a low water content, the joining performance is not impaired, and the chips can be chucked by the vacuum suction method. Since they can be used for a long life without causing adhesion, mass-produced processes and equipment can be realized, and highly reliable bonding between the chip and the carrier substrate can be achieved.
  • an ultra-high pin count or high-speed LSI chip can be housed in a compact, and the chip performance can be maximized.
  • a semiconductor package having a highly reliable connection portion can be provided by using a low-cost organic carrier substrate.
  • the present invention provides an Au bump / Au pad or an Au bump, a flip-chip bonding method of an Au bump capable of producing the semiconductor package by a process with high productivity, and a bonding apparatus for realizing the method. can do.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

On soude solidement une puce sur un substrat organique au moyen de protubérances nettoyées en Au dans une atmosphère limitée en humidité. Chaque protubérance en Au présente une contrainte limitée et possède un diamètre égal ou inférieur à 300 νm, une hauteur égale ou supérieure à 50 νm et un rapport entre hauteur et diamètre égal ou supérieur à 1/5.
PCT/JP1998/004337 1998-09-28 1998-09-28 Boitier de semiconducteur et procede correspondant de soudage de puce WO2000019514A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN98814031A CN1299518A (zh) 1998-09-28 1998-09-28 半导体封装及其倒装芯片接合法
KR1020007003151A KR20010030703A (ko) 1998-09-28 1998-09-28 반도체 패키지 및 그에 있어서의 플립 칩 접합 방법
PCT/JP1998/004337 WO2000019514A1 (fr) 1998-09-28 1998-09-28 Boitier de semiconducteur et procede correspondant de soudage de puce

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PCT/JP1998/004337 WO2000019514A1 (fr) 1998-09-28 1998-09-28 Boitier de semiconducteur et procede correspondant de soudage de puce

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WO2009009566A2 (fr) * 2007-07-09 2009-01-15 Texas Instruments Incorporated Procédé de fabrication d'un dispositif à semi-conducteurs
CN102237285A (zh) * 2010-04-20 2011-11-09 台湾积体电路制造股份有限公司 晶片接合机
US9560771B2 (en) 2012-11-27 2017-01-31 Omnivision Technologies, Inc. Ball grid array and land grid array having modified footprint
US9960143B2 (en) 2016-03-14 2018-05-01 Toshiba Memory Corporation Method for manufacturing electronic component and manufacturing apparatus of electronic component

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KR20030049284A (ko) * 2001-12-14 2003-06-25 삼성전기주식회사 플립칩 본딩용 패키지기판
US7164192B2 (en) * 2003-02-10 2007-01-16 Skyworks Solutions, Inc. Semiconductor die package with reduced inductance and reduced die attach flow out
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KR100691443B1 (ko) * 2005-11-16 2007-03-09 삼성전기주식회사 플립칩 패키지 및 그 제조방법
JP5066529B2 (ja) 2006-10-19 2012-11-07 パナソニック株式会社 半導体素子の実装構造体及び半導体素子の実装方法
US8387674B2 (en) 2007-11-30 2013-03-05 Taiwan Semiconductor Manufacturing Comany, Ltd. Chip on wafer bonder
US8084853B2 (en) * 2009-09-25 2011-12-27 Mediatek Inc. Semiconductor flip chip package utilizing wire bonding for net switching
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
JP5643036B2 (ja) * 2010-09-14 2014-12-17 株式会社ディスコ 光デバイスウエーハの加工方法
US20130119532A1 (en) * 2011-11-11 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Bumps for Chip Scale Packaging
US8975117B2 (en) * 2012-02-08 2015-03-10 Infineon Technologies Ag Semiconductor device using diffusion soldering
US10037941B2 (en) * 2014-12-12 2018-07-31 Qualcomm Incorporated Integrated device package comprising photo sensitive fill between a substrate and a die

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009009566A2 (fr) * 2007-07-09 2009-01-15 Texas Instruments Incorporated Procédé de fabrication d'un dispositif à semi-conducteurs
WO2009009566A3 (fr) * 2007-07-09 2009-03-26 Texas Instruments Inc Procédé de fabrication d'un dispositif à semi-conducteurs
CN102237285A (zh) * 2010-04-20 2011-11-09 台湾积体电路制造股份有限公司 晶片接合机
US9560771B2 (en) 2012-11-27 2017-01-31 Omnivision Technologies, Inc. Ball grid array and land grid array having modified footprint
US9960143B2 (en) 2016-03-14 2018-05-01 Toshiba Memory Corporation Method for manufacturing electronic component and manufacturing apparatus of electronic component

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KR20010030703A (ko) 2001-04-16
CN1299518A (zh) 2001-06-13

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