TWI657545B - 半導體封裝結構及其線路基板 - Google Patents

半導體封裝結構及其線路基板 Download PDF

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TWI657545B
TWI657545B TW107108194A TW107108194A TWI657545B TW I657545 B TWI657545 B TW I657545B TW 107108194 A TW107108194 A TW 107108194A TW 107108194 A TW107108194 A TW 107108194A TW I657545 B TWI657545 B TW I657545B
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TW201939682A (zh
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謝慶堂
Chin-Tang Hsieh
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頎邦科技股份有限公司
Chipbond Technology Corporation
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Priority to TW107108194A priority Critical patent/TWI657545B/zh
Priority to KR1020180053038A priority patent/KR20190107547A/ko
Priority to JP2018090485A priority patent/JP6615938B2/ja
Priority to CN201810438033.2A priority patent/CN110265381B/zh
Priority to US15/990,747 priority patent/US10504828B2/en
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Publication of TWI657545B publication Critical patent/TWI657545B/zh
Publication of TW201939682A publication Critical patent/TW201939682A/zh

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Abstract

一種半導體封裝結構包含一線路基板及一晶片，該線路基板具有複數個線路，各該線路之一接合區域具有一上寬部及一下寬部，使該接合區域形成有一上缺口及一下缺口，該上缺口及該下缺口分別朝向相鄰線路之該上寬部及該下寬部，該上寬部及該下寬部用以避免該些線路及該晶片凸塊之間發生偏移錯位而導接不良，此外於線路蝕刻過程中，相互交錯對應的該些寬部及該些缺口使該些線路之間具有足夠的蝕刻空間，以避免線路蝕刻不完全的情形發生。

Description

半導體封裝結構及其線路基板
本發明關於一種半導體封裝結構，特別是一種可避免晶片與線路基板之間發生導接不良的半導體封裝結構。
為了滿足消費電子產品的效能需求，半導體封裝結構日益朝向超精細間距(super fine pitch)發展，其中可藉由縮小線路寬度及線路間距提高線路數目以達到超精細間距，然而當以習知熱壓合技術接合線路基板的線路及晶片的凸塊時，線路及凸塊之間容易脫落或偏移錯位而導接不良。
本發明之一目的在於提供一種線路基板，其包含一載板、複數個第一線路及複數個第二線路，該載板具有一表面，該些第一線路及該些第二線路形成於該表面且沿著一橫軸方向間隔排列，各該第一線路具有依序連接之一第一上寬部、一第一窄部、一第一下寬部、一內延伸部及一第一線路段，該第一上寬部、該第一窄部、該第一下寬部及該內延伸部位於一第一接合區域用以接合一晶片，各該第二線路具有依序連接之一外延伸部、一第二上寬部、一第二窄部、一第二下寬部及一第二線路段，該外延伸部、該第二上寬部、該第二窄部及該第二下寬部位於一第二接合區域用以接合該晶片，其中於該橫軸方向，該第一上寬部及該第一下寬部之寬度大於該第一窄部及該內延伸部之寬度，使各該第一線路於該第一接合區域形成一第一上缺口及一第一下缺口，該第一上缺口朝向該第二上寬部，該第一下缺口朝向該第二下寬部，且該第二上寬部及該第二下寬部之寬度大於該外延伸部及該第二窄部之寬度，使各該第二線路於該第二接合區域形成一第二上缺口及一第二下缺口，該第二上缺口朝向該第一上寬部，該第二下缺口朝向該第一下寬部。
本發明之另一目的在於提供一種半導體封裝結構，其包含一晶片及一線路基板，該晶片具有複數個第一凸塊及複數個第二凸塊，該線路基板具有一載板、複數個第一線路及複數個第二線路，該載板具有一表面，該些第一線路及該些第二線路形成於該表面並沿著一橫軸方向間隔排列，各該第一線路具有依序連接之一第一上寬部、一第一窄部、一第一下寬部、一內延伸部及一第一線路段，該第一上寬部、該第一窄部、該第一下寬部及該內延伸部位於一第一接合區域並接合各該第一凸塊，各該第二線路具有依序連接之一外延伸部、一第二上寬部、一第二窄部、一第二下寬部及一第二線路段，該外延伸部、該第二上寬部、該第二窄部及該第二下寬部位於一第二接合區域並接合各該第二凸塊，其中於該橫軸方向，該第一上寬部及該第一下寬部之寬度大於該第一窄部及該內延伸部之寬度，使該第一線路於該第一接合區域形成一第一上缺口及一第一下缺口，該第一上缺口朝向該第二上寬部，該第一下缺口朝向該第二下寬部，且該第二上寬部及該第二下寬部之寬度大於該外延伸部及該第二窄部之寬度，使該第二線路於該第二接合區域形成一第二上缺口及一第二下缺口，該第二上缺口朝向該第一上寬部，該第二下缺口朝向該第一下寬部。
當該些線路與該晶片之該些凸塊接合時，該第一上寬部、該第一下寬部、該第二上寬部及該第二下寬部可避免該些線路及該些凸塊之間發生脫落或偏移錯位而導接不良，且為了使該些線路之間具有足夠的蝕刻空間，於該第一接合區域及該第二接合區域中設有相互交錯對應的寬部及缺口，以避免線路圖案化過程中發生蝕刻不完全的情形。
請參閱第1及3圖，本發明之一種半導體封裝結構A包含一線路基板100及一晶片200，該線路基板100具有複數個第一線路110、複數個第二線路120及一載板130，該載板130具有一表面131，其中沿著一橫軸方向，該些第一線路110及該些第二線路120間隔排列地形成於該表面131，該晶片200具有複數個第一凸塊210及複數個第二凸塊220，該些第一凸塊210及該些第二凸塊220沿著該橫軸方向間隔排列且分別與該些第一線路110及該些第二線路120接合，在本實施例中，該半導體封裝結構A另包含一封裝膠體300，該封裝膠體300填充於該線路基板100及該晶片200之間，較佳地，該封裝膠體300為底部填充膠(underfill)。
請參閱第2圖，各該第一線路110具有依序連接之一第一上寬部111、一第一窄部112、一第一下寬部113、一內延伸部114及一第一線路段115，且各該第一線路110之一端具有一第一接合區域B1，該第一上寬部111、該第一窄部112、該第一下寬部113及該內延伸部114位於該第一接合區域B1用以接合該晶片200之各該第一凸塊210。
請參閱第2圖，各該第二線路120具有依序連接之一外延伸部121、一第二上寬部122、一第二窄部123、一第二下寬部124及一第二線路段125，與各該第一線路110相同，各該第二線路120之一端具有一第二接合區域B2，且各該第一接合區域B1與各該第二接合區域B2沿著該橫軸方向間隔排列，該外延伸部121、該第二上寬部122、該第二窄部123及該第二下寬部124位於該第二接合區域B2用以接合該晶片200之各該第二凸塊220，較佳地，各該第一接合區域B1與各該第二接合區域B2實質上平齊。
請參閱第1及3圖，該載板130另具有一保護層132，該保護層132形成於該表面131並覆蓋該些第一線路段115及該些第二線路段125，但該保護層132不覆蓋該些第一接合區域B1及該些第二接合區域B2，使位於各該第一接合區域B1及各該第二接合區域B2之該些第一線路110及該些第二線路120顯露於該載板130，以接合該晶片200。
請參閱第2圖，於該橫軸方向，該第一上寬部111及該第一下寬部113之寬度實質上相同，該第一窄部112、該內延伸部114及該第一線路段115之寬度實質上相同，且該第一上寬部111及該第一下寬部113之寬度大於該第一窄部112、該內延伸部114及該第一線路段115之寬度，使各該第一線路110於該第一接合區域B1形成一第一上缺口116及一第一下缺口117，即該第一上寬部111及該第一下寬部113之邊緣凸出於該第一窄部112及該內延伸部114之邊緣，其中該第一上缺口116朝向該第二上寬部122，該第一下缺口117朝向該第二下寬部124，較佳地，該第一上寬部111及該第一下寬部113之邊緣沿著該橫軸方向凸出於該第一窄部112及該內延伸部114之邊緣0.5-3.5 μm，該第一上寬部111及該第一下寬部113用以承接各該第一凸塊210，避免覆晶接合時各該第一凸塊210及各該第一線路110之間發生脫落或偏移錯位的情形。
該第一上寬部111及該第一下寬部113至少一側凸出於該第一窄部112及該內延伸部114，較佳地，該第一窄部112及該內延伸部114之寬度介於5-8 μm之間，請參閱第2圖，在本實施例中，該第一上寬部111及該第一下寬部113兩側邊緣皆凸出於該第一窄部112及該內延伸部114，但本發明不以此為限制，該第一窄部112及該內延伸部114之寬度實質上為7 μm，該第一上寬部111及該第一下寬部113之寬度實質上為9 μm，因此該第一上寬部111及該第一下寬部113兩側分別凸出於該第一窄部112及該內延伸部114邊緣1 μm。
請參閱第2圖，該第二上寬部122及該第二下寬部124之寬度實質上相同，該外延伸部121、該第二窄部123及該第二線路段125之寬度實質上相同，且該第二上寬部122及該第二下寬部124之寬度大於該外延伸部121、該第二窄部123及該第二線路段125之寬度，使各該第二線路120於該第二接合區域B2形成一第二上缺口126及一第二下缺口127，即該第二上寬部122及該第二下寬部124之邊緣凸出於該外延伸部121及該第二窄部123之邊緣，其中該第二上缺口126朝向該第一上寬部111，該第二下缺口127朝向該第一下寬部113，較佳地，該第二上寬部122及該第二下寬部124之邊緣沿著該橫軸方向凸出於該外延伸部121及該第二窄部123之邊緣0.5-3.5 μm，該第二上寬部122及該第二下寬部124用以承接各該第二凸塊220，避免覆晶接合時各該第二凸塊220及各該第二線路120之間發生脫落或偏移錯位的情形。
該第二上寬部122及該第二下寬部124至少一側凸出於該外延伸部121及該第二窄部123，較佳地，該外延伸部121及該第二窄部123之寬度介於5-8 μm之間，請參閱第2圖，在本實施例中，該第二上寬部122及該第二下寬部124兩側邊緣皆凸出於該外延伸部121及該第二窄部123，但本發明不以此為限制，該外延伸部121及該第二窄部123之寬度實質上為7 μm，該第二上寬部122及該第二下寬部124之寬度實質上為9 μm，因此該第二上寬部122及該第二下寬部124兩側分別凸出於該外延伸部121及該第二窄部123邊緣1 μm。
請參閱第3圖，於該橫軸方向，該第一凸塊210、該第一上寬部111及該第一下寬部113之寬度實質上相同，且該第二凸塊220、該第二上寬部122及該第二下寬部124之寬度實質上相同，因此可避免該晶片200於接合過程中晃動而造成該線路基板100之該些第一線路110及該第二線路120受損。
請參閱第2圖，該第一窄部112與該第二上寬部122之間具有一第一間距P1，該第一間距P1為該第一窄部112中心與該第二上寬部122中心之最短距離，而該第二窄部123與該第一下寬部113之間具有一第二間距P2，該第二間距P2為該第二窄部123中心與該第一下寬部113中心之最短距離，其中該第一間距P1與該第二間距P2實質上相同，較佳地，該第一間距P1及該第二間距P2不大於20 μm，在本實施例中，該第一間距P1及該第二間距P2實質上為14 μm。
請參閱第3圖，較佳地，該第一窄部112及該內延伸部114之寬度小於其厚度，其中該第一窄部112及該內延伸部114之厚度為其頂面至該載板130之該表面131之最短距離，由於該第一窄部112及該內延伸部114呈細長狀，因此當各該第一線路110與各該第一凸塊210接合時，該第一窄部114及該內延伸部114會些微扭曲以避免該些第一線路110受接合力矩影響而脫離該載板130。相同地，該外延伸部121及該第二窄部123之寬度小於其厚度，使該外延伸部121及該第二窄部123呈細長狀，可於接合過程中些微扭曲，以避免該些第二線路120受接合力矩影響而脫離該載板130。
請參閱第3圖，較佳地，該第一上寬部111及該第一下寬部113之寬度不小於其厚度，其中該第一上寬部111及該第一下寬部113之厚度為其頂面至該載板130之該表面131之最短距離，該第一上寬部111及該第一下寬部113可防止該第一窄部112及該內延伸部114於接合過程中過度扭曲而導致該第一線路110斷裂，相同地，該第二上寬部122及該第二下寬部124之寬度不小於其厚度。
在本實施例中，該些第一線路110及該些第二線路120之厚度實質上為8 μm，該第一上寬部111、該第一下寬部113、該第二上寬部122及該第二下寬部124之寬度實質上為9 μm，而該第一窄部112、該內延伸部114、該外延伸部121及該第二窄部123之寬度實質上為7 μm。
當該晶片200覆晶接合於該線路基板100時，該第一上寬部111及該第一下寬部113能夠降低該些第一線路110及該些第一凸塊210之間發生偏移錯位而導接不良的情形，且該第二上寬部122及該第二下寬部124能夠降低該些第二線路120及該些第二凸塊220之間發生偏移錯位而導接不良的情形，除此之外，本發明亦可避免各該第一凸塊210與各該第二凸塊220因附著力不足而導致該晶片200脫離該線路基板100的情形發生。
此外，線路圖案化製程係以圖案化光阻為遮罩蝕刻金屬層，以形成該些第一線路110及該些第二線路120，由於該些第一線路110及該些第二線路120之該些寬部及該些缺口相互交錯對應，因此該些第一線路110及該些第二線路120之間具有足夠的蝕刻空間，可避免線路蝕刻不完全的情形發生。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100‧‧‧線路基板
110‧‧‧第一線路
111‧‧‧第一上寬部
112‧‧‧第一窄部
113‧‧‧第一下寬部
114‧‧‧內延伸部
115‧‧‧第一線路段
116‧‧‧第一上缺口
117‧‧‧第一下缺口
120‧‧‧第二線路
121‧‧‧外延伸部
122‧‧‧第二上寬部
123‧‧‧第二窄部
124‧‧‧第二下寬部
125‧‧‧第二線路段
126‧‧‧第二上缺口
127‧‧‧第二下缺口
130‧‧‧載板
131‧‧‧表面
132‧‧‧保護層
200‧‧‧晶片
210‧‧‧第一凸塊
220‧‧‧第二凸塊
300‧‧‧封裝膠體
A‧‧‧半導體封裝結構
B1‧‧‧第一接合區域
B2‧‧‧第二接合區域
P1‧‧‧第一間距
P2‧‧‧第二間距
第1圖：依據本發明之一實施例，一種線路基板之上視圖。 第2圖：依據本發明之一實施例，該線路基板之局部線路上視圖。 第3圖：依據本發明之一實施例，一種半導體封裝結構之側視圖。

Claims (17)

  1. 一種線路基板，其包含： 一載板，具有一表面； 複數個第一線路，形成於該表面，各該第一線路具有依序連接之一第一上寬部、一第一窄部、一第一下寬部、一內延伸部及一第一線路段，該第一上寬部、該第一窄部、該第一下寬部及該內延伸部位於一第一接合區域用以接合一晶片；以及 複數個第二線路，形成於該表面，該些第一線路及該些第二線路沿著一橫軸方向間隔排列，各該第二線路具有依序連接之一外延伸部、一第二上寬部、一第二窄部、一第二下寬部及一第二線路段，該外延伸部、該第二上寬部、該第二窄部及該第二下寬部位於一第二接合區域用以接合該晶片； 其中於該橫軸方向，該第一上寬部及該第一下寬部之寬度大於該第一窄部及該內延伸部之寬度，使各該第一線路於該第一接合區域形成一第一上缺口及一第一下缺口，該第一上缺口朝向該第二上寬部，該第一下缺口朝向該第二下寬部，且該第二上寬部及該第二下寬部之寬度大於該外延伸部及該第二窄部之寬度，使各該第二線路於該第二接合區域形成一第二上缺口及一第二下缺口，該第二上缺口朝向該第一上寬部，該第二下缺口朝向該第一下寬部。
  2. 如申請專利範圍第1項所述之線路基板，其中各該第一接合區域與各該第二接合區域沿著該橫軸方向間隔排列且實質上平齊。
  3. 如申請專利範圍第1項所述之線路基板，其中該第一窄部與該第二上寬部之間具有一第一間距，該第二窄部與該第一下寬部之間具有一第二間距，該第一間距與該第二間距實質上相同。
  4. 如申請專利範圍第3項所述之線路基板，其中該第一間距及該第二間距不大於20 μm。
  5. 如申請專利範圍第1項所述之線路基板，其中該第一上寬部及該第一下寬部之寬度實質上相同，該第一窄部及該內延伸部之寬度實質上相同。
  6. 如申請專利範圍第1項所述之線路基板，其中該第一上寬部之邊緣凸出於該第一窄部之邊緣0.5-3.5 μm。
  7. 如申請專利範圍第1項所述之線路基板，其中該第一上寬部之寬度不小於該第一上寬部之厚度。
  8. 如申請專利範圍第1項所述之線路基板，其中該第一窄部之寬度小於該第一窄部之厚度。
  9. 一種半導體封裝結構，其包含： 一晶片，具有複數個第一凸塊及複數個第二凸塊；以及 一線路基板，具有一載板、複數個第一線路及複數個第二線路，該載板具有一表面，該些第一線路及該些第二線路形成於該表面並沿著一橫軸方向間隔排列，各該第一線路具有依序連接之一第一上寬部、一第一窄部、一第一下寬部、一內延伸部及一第一線路段，該第一上寬部、該第一窄部、該第一下寬部及該內延伸部位於一第一接合區域並接合各該第一凸塊，各該第二線路具有依序連接之一外延伸部、一第二上寬部、一第二窄部、一第二下寬部及一第二線路段，該外延伸部、該第二上寬部、該第二窄部及該第二下寬部位於一第二接合區域並接合各該第二凸塊，其中於該橫軸方向，該第一上寬部及該第一下寬部之寬度大於該第一窄部及該內延伸部之寬度，使該第一線路於該第一接合區域形成一第一上缺口及一第一下缺口，該第一上缺口朝向該第二上寬部，該第一下缺口朝向該第二下寬部，且該第二上寬部及該第二下寬部之寬度大於該外延伸部及該第二窄部之寬度，使該第二線路於該第二接合區域形成一第二上缺口及一第二下缺口，該第二上缺口朝向該第一上寬部，該第二下缺口朝向該第一下寬部。
  10. 如申請專利範圍第9項所述之半導體封裝結構，其中各該第一接合區域與各該第二接合區域沿著該橫軸方向間隔排列且實質上平齊。
  11. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一窄部與該第二上寬部之間具有一第一間距，該第二窄部與該第一下寬部之間具有一第二間距，該第一間距與該第二間距實質上相同。
  12. 如申請專利範圍第11項所述之半導體封裝結構，其中該第一間距及該第二間距不大於20 μm。
  13. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一上寬部及該第一下寬部之寬度實質上相同，該第一窄部及該內延伸部之寬度實質上相同。
  14. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一上寬部之邊緣凸出於該第一窄部之邊緣0.5-3.5 μm。
  15. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一上寬部之寬度不小於該第一上寬部之厚度。
  16. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一窄部之寬度小於該第一窄部之厚度。
  17. 如申請專利範圍第9項所述之半導體封裝結構，其中該第一凸塊、該第一上寬部及該第一下寬部之寬度實質上相同。
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