CN110071082B - 具有环绕填充线的接合垫 - Google Patents

具有环绕填充线的接合垫 Download PDF

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Publication number
CN110071082B
CN110071082B CN201811570669.9A CN201811570669A CN110071082B CN 110071082 B CN110071082 B CN 110071082B CN 201811570669 A CN201811570669 A CN 201811570669A CN 110071082 B CN110071082 B CN 110071082B
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fill
bond pad
top surface
perimeter
under bump
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CN110071082A (zh
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史考特·波德尔
T·拉曼
K·杨-费希尔
D·斯通
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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Abstract

本发明涉及具有环绕填充线的接合垫，其提供一种接合垫结构及用于制作接合垫结构的方法。在介电层的顶端表面上形成接合垫及多条填充线。填充线是相邻于接合垫设置在介电层的顶端表面上，并且可通过填充排除区与接合垫分开。一或多个凸块下冶金(UBM)层可设置在接合垫上，并且可向外延展以与填充线重叠。

Description

具有环绕填充线的接合垫
技术领域
本发明大体上是关于半导体结构及半导体芯片的制作，并且尤指接合垫结构及用于制作接合垫结构的方法。
背景技术
芯片或晶粒包括通过前段(FEOL)处理所形成的集成电路、及通过后段(BEOL)处理所形成的互连结构的敷金属阶(metallization level)。接着，将芯片封装并嵌装在电路板上。接合垫通常是用于经由凸块在芯片的最后或顶端敷金属阶与封装材之间提供机械及电连接。
典型由铝所组成的接合垫可由在芯片对封装材接口处造成机械弱点的禁用空间所围绕。封装材内的高局部负载可透过接合垫上的焊块及凸块下冶金(UBM)传送至BEOL敷金属阶。这些传送力会提升芯片对封装材接口处凸块下失效的风险，尤其是在接合垫尺寸比例缩小的情况下。
需要改良型接合垫结构及制作接合垫结构的方法。
发明内容
在本发明的一具体实施例中，一种结构包括具有顶端表面的介电层、位在该介电层的该顶端表面上的接合垫、以及设置在该介电层的该顶端表面上与该接合垫相邻的多条填充线。
在本发明的一具体实施例中，一种结构包括具有顶端表面的介电层、位在该介电层的该顶端表面上的接合垫、以及位在该接合垫上方的钝化层。该钝化层包括顶端表面及开口，该开口具有自该顶端表面延展至该接合垫的侧壁。该结构包括位在该接合垫、该钝化层中该开口的该侧壁、及该钝化层的该顶端表面上的一或多个凸块下冶金(UBM)层。该接合垫具有周界，并且该一或多个UBM层具有水平设置在该接合垫的该周界外侧的周界。
在本发明的一具体实施例中，一种方法包括形成位在介电层的顶端表面上的接合垫，以及形成位在该介电层的该顶端表面上相邻于该接合垫设置的多条填充线。
附图说明
附图是合并于本说明书的一部分并构成该部分，绘示本发明的各项具体实施例，并且连同上述对本发明的一般性说明、及下文对具体实施例提供的详细说明，目的是为了阐释本发明的具体实施例。
图1根据本发明的具体实施例，为一种结构在处理方法的初始制作阶段时的俯视图。
图1A为该结构大体上沿着图1中的线条1A-1A取看的截面图。
图2至图5为该结构在图1A后的接续制作阶段时的截面图。
图6根据本发明的具体实施例为一种结构的俯视图。
主要附图标记说明
10,12,30 介电层
13 顶端表面
14 BEOL互连结构
16 接合垫
18,27 侧边
19,29,37 周界
20 绕接线
25 端部
26 填充线
28 填充排除区
31 平坦化表面
32 钝化层
33 顶端表面
34 开口
35 侧壁
36 UBM层
40 柱体
42,43 区块
44 不连续部位。
具体实施方式
请参阅图1、图1A，并且根据本发明的具体实施例，介电层10、12是设置在后段(BEOL)互连结构14的敷金属阶的顶端表面上。BEOL互连结构14的典型构造可包括二(2)至约十五(15)个敷金属阶。BEOL互连结构14的敷金属阶可通过镶嵌程序的微影及蚀刻程序特性来形成。介电层10、12可由介电材料所组成，诸如氮化硅(Si3N4)、二氧化硅(SiO2)、或氮掺杂碳化硅(例如，NBloK)，其是通过例如电浆增强型化学气相沉积(CVD)所沉积，并且作用为电绝缘体。BEOL互连结构14是承载在晶粒或芯片(图未示)上，其上已通过前段(FEOL)处理制作有一或多个主动电路的装置结构。
接合垫16、绕接线20、及多条填充线26是设置在介电层12的顶端表面13上。接合垫16、绕接线20、及填充线26可通过将沉积在介电层12的顶端表面13上的诸如铝(Al)的一层导体图型化的微影及蚀刻程序来形成。接合垫16可形成有通过多个边缘或侧边18于其周界19处围绕的给定多角形状，诸如八角形。绕接线20跨过介电层12的顶端表面13自接合垫16的一个侧边18向外延展。介电层10可包括与芯片上的主动电路耦接的导线(图未示)，并且绕接线20及一或多个介电层12中的贯孔(图未示)可将接合垫18与该导线连接。相比之下，填充线26为与信号网路或电力网络缺乏连接的电隔离特征。
在一替代具体实施例中，接合垫16及填充线26可接续由透过微影及蚀刻程序予以个别图型化的分离沉积导体层所形成。
可用平行对准将填充线26设置为格栅的线路，所述线路是沿着其各别长度于每个点处以相同隔距设置。填充线26可具有线路-空间间距，其中，填充线26具有宽度w，并且相邻填充线26之间的空间或间隙具有间隔g。在一具体实施例中，填充线26的宽度可大于相邻填充线26之间的间隔。在一具体实施例中，填充线26的宽度及间隔之间的比率可为2.5比1。在一具体实施例中，相邻填充线26之间的间隔可选定为狭窄到足以促进用介电材料在相邻填充线26之间进行空间的完整间隙填充，以便在填充线26上方形成平坦化表面。或者，相邻填充线26之间的间隔可超过最大间隔，允许用介电材料在相邻填充线26之间进行空间的完整间隙填充，并且可导致部分填充。
填充线26是相邻于接合垫16设置，并且通过位于接合垫16的所有侧边18将接合垫16围绕。填充线26及接合垫16的侧边18是通过填充禁区或排除区28予以分开，其为介电层12的顶端表面13上没有金属的区域，尤其是没有填充线26的金属。填充排除区28具有大体上在图1中以点虚线图示的外周界29、以及与接合垫16的周界19共同延展的内周界。填充线26是设置在填充排除区28的外周界29外侧，并且结合垫16是整个设置在填充排除区28的外周界29内侧。特别的是，基于填充排除区28的置放，填充线26可具有在其周界19处以距离s与接合垫16的一个侧边18分开的端部25或侧边27，使得填充排除区28没有填充线26。在该配置中，填充线26的侧边27可与绕接线20的侧边平行对准。填充排除区28可相对于接合垫16设置在x-y平面中，使得接合垫16受填充线26的端部25及侧边27圈围，并且周界29追踪端部25及侧边27。在接合垫16为八角形的一具体实施例中，接合垫16具有以介于两个平行侧边18之间的垂直距离给定的直径或最大尺寸d2。
请参阅图2，其中相似的附图标记是指图1A中及后续制作阶段时相似的特征，在接合垫16及填充线26上方将一或多个介电层30形成为钝化。一或多个介电层30填充介于诸填充线26之间的间隙、以及包覆接合垫16并填充禁区28。间隙填充取决于相邻填充线26之间的间隙的间隔。在一具体实施例中，一或多个介电层30可完全填充介于诸填充线26之间的间隙，并且在填充线26上面或上方提供平坦化表面31。在一替代具体实施例中，一或多个介电层30可部分地填充介于诸填充线26之间的间隙。一或多个介电层30可各由诸如氮化硅(Si3N4)、二氧化硅(SiO2)、氮氧化硅(SiONx)等通过例如电浆增强型化学气相沉积(CVD)或原子层沉积(ALD)所沉积的无机介电材料所组成。
请参阅图3，其中相似的附图标记是指图2中及后续制作阶段时相似的特征，在一或多个介电层30上方形成钝化层32。钝化层32可由诸如聚亚酰胺(PI)、聚苯并唑(PBO)、苯环丁烯(BCB)等有机介电材料所构成，其是任选地具有光敏性，并且为电绝缘体。钝化层32可通过在溶剂中将聚合物溶解以形成先驱物、利用旋涂程序使该先驱物散布、然后燥化涂料将溶剂从先驱物涂料移除并使聚合物亚酰胺化来制备。钝化层32可通过一或多个微影及蚀刻程序来图型化以形成开口34，开口34具有自钝化层32的顶端表面33延展至接合垫16的侧壁35。可在图型化期间在开口34的底座处移除一或多个介电层30，以使接合垫16的顶端表面显露及曝露。
请参阅图4，其中相似的附图标记是指图3中及后续制作阶段时相似的特征，一或多个凸块下冶金(UBM)层36是沉积在钝化层32的顶端表面33的一部分上、开口34的侧壁35、及接合垫16上方的开口34内侧，并且是通过一或多个微影及蚀刻程序来图型化。一或多个UBM层36可由通过物理气相沉积(PVD)或另一沉积技巧来沉积的各种导体所组成，诸如金属(诸如钽(Ta))、以及金属合金(诸如钛与钨的合金(TiW))、金属氮化物(诸如氮化钛(TiN)、氮化钽(TaN)、或氮化钨(WNx))、或这些导体的多层组合(例如，TaN/Ta的双层)。
一或多个UBM层36大于接合垫16，并且具有将接合垫16的周界19围绕及圈围的周界37。一或多个UBM层36的周界37可具有圆形形状，并且可圈围接合垫16，使得接合垫16的周界19是设置在外缘37内侧。一或多个UBM层36的周界37延展超出填充排除区28(第2、2A图)的周界29，并且与填充线26的区段重叠。该重叠可绕着一或多个UBM层36的整个周界37延展。特别的是，一或多个UBM层36可在周界37处具有比填充排除区28的周界29的尺寸d1更大的尺寸d3，并且这两者都大于接合垫16的周界19的尺寸d2。在传统接合垫结构中，一或多个UBM层小于接合垫，使得接合垫的外缘圈围一或多个UBM层的外缘。在布局的一具体实施例中，填充排除区28在其周界29处的尺寸d1可为63微米，接合垫16在其周界19处的最大尺寸d2可小于或等于46微米，并且一或多个UBM层36在其周界37处的尺寸d3可为75微米或95微米。
请参阅图5，其中相似的附图标记是指图4中及后续制作阶段时相似的特征，柱体40是在一或多个UBM层36上及接合垫16上的开口34内侧形成。柱体40可由透过例如电化学浸镀程序来沉积的导体所构成，诸如铜(Cu)或另一低电阻率金属或金属合金。或者，可在一或多个UBM层36上、以及开口34内侧及接合垫16上方形成焊块，以取代柱体40。焊块可由具有无铅(无Pb)组成的焊料所构成，其可包括锡(Sn)作为主要元素组分。
接合垫16、填充线26、及一或多个UBM层36的结构可采个别或组合方式提供各种效益。填充线26的添加以及介于一或多个UBM层36与填充线26之间的重叠与接合垫16的尺寸无关。不同尺寸接合垫的阵列上可应用填充线26的添加及介于一或多个UBM层36与填充线26之间的重叠。填充线26的添加以及介于一或多个UBM层36与填充线26之间的重叠不干扰布线，因为其是在布线完成之后才形成。填充线26的添加以及介于一或多个UBM层36与填充线26之间的重叠与贯孔24的置放无关。介于一或多个UBM层36与填充线26之间的重叠导致结合垫构造具有机械稳健性，并且可实现电容目标，因为允许填充禁区28而没有劣化芯片对封装材接口机械效能，并且因为隔离的填充线26尺寸够小，使得任何添加的电容都小。
请参阅图6，其中相似的附图标记是指图1中相似的特征，而且根据本发明的具体实施例，可改变填充线26以提供多个区块42、43，各区块包括设置成阵列的多条填充线26。区块42内侧及区块43内侧相关联的填充线26在x-y平面中具有平行配置。区块43中的填充线26相对于区块42中的填充线偏斜一角度。在一具体实施例中，区块43中的填充线26是在平面中顺着一个方向(例如，x方向)取向，并且区块42中的填充线26在平面中顺着正交方向(例如，y方向)取向，使得倾角为90°。然而，区块43中的填充线26可相对于区块42中的填充线26以不同倾角偏斜。一或多个区块42、43中的填充线26有一些可包括不连续部位44。以不同倾角为特征在区块42、43中设置填充线26可提供等向性或近似等向性的性质，诸如平行及正交于填充线26以加热及冷却循环膨胀及收缩。
本文中对“垂直”、“水平”等用语的参照属于举例，并非限制，乃用来建立参考架构。诸如“水平”与“侧向”等用语是指平面中与半导体基材的顶端表面平行的方向，与其实际三维空间方位无关。诸如“垂直”与“正交”等用语是指与“水平”及“侧向”方向垂直的方向。诸如“上面”及“下面”等用语指出组件或结构彼此的相对位置，及/或与半导体基材的顶端表面相对的位置，与相对高度截然不同。
“连接”或“耦接”至另一组件、或与该另一组件“连接”或“耦接”的特征可直接连接或耦接至其它组件，或者，转而可出现一或多个中介组件。如无中介组件，一特征可“直接连接”或“直接耦接”至另一组件。如有至少一个中介组件，一特征可“间接连接”或“间接耦接”至另一组件。
本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对所属领域技术人员将会显而易见，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让所属领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (17)

1.一种半导体结构，其包含：
第一介电层，具有顶端表面；
接合垫，位在该第一介电层的该顶端表面上；
多条填充线，设置在该第一介电层的该顶端表面上相邻于该接合垫；
钝化层，位在该接合垫及所述填充线上方，该钝化层包括顶端表面及开口，该开口具有自该顶端表面垂直延展至该接合垫的侧壁；以及
一或多个凸块下冶金层，位在该接合垫上、该钝化层中的该开口的该侧壁上、及该钝化层的该顶端表面上，
其中，该接合垫具有通过填充排除区与所述填充线分开的周界，及
其中，该填充线与该一或多个凸块下冶金层之间有重迭。
2.如权利要求1所述的半导体结构，其中，该一或多个凸块下冶金层具有周界，并且该接合垫的该周界水平设置在该一或多个凸块下冶金层的该周界内侧。
3.如权利要求1所述的半导体结构，其中，该填充排除区是水平设置在该一或多个凸块下冶金层的该周界与该接合垫的该周界之间。
4.如权利要求1所述的半导体结构，其中，所述填充线是通过间隙分开，并且还包含：
一或多个第二介电层，设置在所述间隙中，
其中，该一或多个第二介电层填充所述间隙，以在所述填充线上方提供平坦化表面。
5.如权利要求1所述的半导体结构，其中，该接合垫具有设置成八角形状的多个侧边，并且所述填充线具有与该接合垫的所述侧边的至少一者平行对准的侧边。
6.如权利要求1所述的半导体结构，其中，所述填充线及该接合垫相对于该第一介电层的该顶端表面具有相等高度，所述填充线具有间隔，并且所述填充线具有比该间隔更大的宽度。
7.如权利要求1所述的半导体结构，其中，所述填充线是组列在第一区块及第二区块中，并且位在该第一区块中的所述填充线相对于位在该第二区块中的所述填充线偏斜一角度。
8.一种半导体结构，其包含：
第一介电层，具有顶端表面；
接合垫，位在该第一介电层的该顶端表面上；
钝化层，位在该接合垫上方，该钝化层包括顶端表面及开口，该开口具有自该顶端表面延展至该接合垫的侧壁；以及
一或多个凸块下冶金层，位在该接合垫、该钝化层中该开口的该侧壁、及该钝化层的该顶端表面上，
其中，该接合垫具有通过填充排除区与填充线分开的周界，
其中，该填充线与该一或多个凸块下冶金层具有重迭,及
其中，该一或多个凸块下冶金层具有水平设置在该接合垫的该周界外侧的周界。
9.如权利要求8所述的半导体结构，还包含：
传导柱，设置在该一或多个凸块下冶金层上。
10.如权利要求8所述的半导体结构，其中，该接合垫的该周界包括设置成八角形状的多个侧边。
11.如权利要求8所述的半导体结构，其中，该接合垫呈八角形，具有第一侧缘及与该第一侧缘采对径方式隔开的第二侧缘，并且该第一侧缘与该第二侧缘分开小于或等于46微米。
12.一种制作半导体结构的方法，该方法包含：
形成位在第一介电层的顶端表面上的接合垫；
形成位在该第一介电层的该顶端表面上相邻于该接合垫设置的多条填充线；
形成位在该接合垫及所述填充线上方的钝化层，该钝化层包括顶端表面及开口，该开口具有自该顶端表面延展至该接合垫的侧壁；以及
形成位在该接合垫上、该钝化层中的该开口的该侧壁上、及该钝化层的该顶端表面上的一或多个凸块下冶金层，
其中，该接合垫具有通过填充排除区与所述填充线分开的周界,及
其中，该填充线与该一或多个凸块下冶金层之间有重迭。
13.如权利要求12所述的方法，还包含：
形成自该接合垫的外缘向外延展的绕接线。
14.如权利要求12所述的方法，其中，所述填充线是与该接合垫同时形成。
15.如权利要求12所述的方法，其中，该一或多个凸块下冶金层具有设置在该接合垫的该周界外侧的周界。
16.如权利要求15所述的方法，其中，该填充排除区与所述填充线分开，并且该填充排除区是设置在该一或多个凸块下冶金层的该周界与该接合垫的该周界之间。
17.如权利要求12所述的方法，其中，所述填充线是通过间隙分开，并且还包含：
沉积设置在所述间隙中的一或多个第二介电层，
其中，该一或多个第二介电层填充所述间隙，以在所述填充线上方提供平坦化表面。
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