KR100447968B1 - 웨이퍼 레벨 패키지의 제조방법 - Google Patents
웨이퍼 레벨 패키지의 제조방법 Download PDFInfo
- Publication number
- KR100447968B1 KR100447968B1 KR10-2001-0047459A KR20010047459A KR100447968B1 KR 100447968 B1 KR100447968 B1 KR 100447968B1 KR 20010047459 A KR20010047459 A KR 20010047459A KR 100447968 B1 KR100447968 B1 KR 100447968B1
- Authority
- KR
- South Korea
- Prior art keywords
- opening
- insulating layer
- forming
- metal wiring
- ball
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 21
- 239000004642 Polyimide Substances 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 8
- 239000007787 solid Substances 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 claims 2
- 238000004544 sputter deposition Methods 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 72
- 238000010586 diagram Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (26)
- 상부면에 다수의 칩패드가 형성된 기판을 제공하는 단계와,상기 기판 상에 상기 칩패드를 노출시키는 제 1개구부와 볼랜드 형성을 위한 제 2개구부를 갖는 제 1절연층을 형성하는 단계와,상기 제 1절연층 상에 상기 제 1개구부를 통해 상기 칩패드와 일체로 연결되며, 상기 제 2개구부를 덮는 볼랜드를 갖는 메탈배선을 형성하는 단계와,상기 메탈배선을 덮고 상기 볼랜드를 노출시키며, 이 후 안착될 도전성 볼과 동일한 폭을 가진 제 3개구부를 구비한 2절연층을 형성하는 단계와,상기 볼랜드 상에 양측이 상기 제 3개구부와 접촉되어 고정되도록 도전성 볼을 안착시키는 단계를 포함하고,상기 제 1개구부와 상기 제 2개구부는 상기 제 1절연층을 서로 다른 노광량으로 노광시키어 형성하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 1항에 있어서, 상기 제 1 및 제 2절연층은 액상 또는 고상의 폴리이미드를 사용하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 삭제
- 제 1항에 있어서, 상기 제 1개구부는 상기 제 1절연층에 포토리쏘그라피에 의한 식각공정을 진행시키어 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 1항에 있어서, 상기 제 2개구부는 상기 제 1절연층에 레이저 조사에 의한 식각공정을 진행시키어 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 6항에 있어서, 상기 조사되는 레이저 에너지는 0.1∼2Joule/cm2 인 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 1항에 있어서, 상기 제 2개구부는 상기 제 1절연층에 자외선 조사에 의한 식각공정을 진행시키어 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 8항에 있어서, 상기 조사되는 자외선 에너지는 100∼300mJ/cm2 범위인 것을 특징으로 하는 패키지의 제조방법.
- 제 1항에 있어서, 상기 제 2개구부는 상기 제 1절연층에 포토리쏘그라피에 의한 식각공정을 진행시키어 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 상부면에 다수의 칩패드가 형성된 기판을 제공하는 단계와,상기 기판 상에 상기 칩패드를 노출시키는 제 1개구부를 갖는 제 1절연층을 형성하는 단계와,상기 제 1절연층의 일정영역에 레이저 조사에 의한 식각공정을 진행하여 볼랜드 형성을 위한 제 2개구부를 형성하는 단계와,상기 제 1절연층 상에 상기 제 1개구부를 통해 상기 칩패드와 일체로 연결되며, 상기 제 2개구부를 덮어 볼랜드를 갖는 메탈배선을 형성하는 단계와,상기 메탈배선을 덮고 상기 볼랜드를 노출시키며, 이후 안착될 도전성 볼과 동일 폭을 가진 제 3개구부를 구비한 2절연층을 형성하는 단계와,상기 볼랜드 상에 양측이 상기 제 3개구부와 접촉되어 고정되도록 도전성 볼을 안착시키는 단계를 포함하고,상기 제 1개구부와 상기 제 2개구부 형성공정은 상기 제 1절연층을 서로 다른 노광량으로 노광시키어 진행하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 12항에 있어서, 상기 제 1개구부는 상기 제 1절연층에 포토리쏘그라피에 의한 식각공정을 진행시키어 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 12항에 있어서, 상기 제 1개구부는 상기 제 1절연층에 레이저 조사에 의한 식각공정을 진행하여 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 제 12항에 있어서, 상기 조사되는 레이저 에너지는 0.1∼2 Joule/cm2 인 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 12항에 있어서, 상기 제 3개구부는 상기 제 2개구부 폭보다 더 크게 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 제 12항에 있어서, 상기 제 1 및 제 2절연층은 액상 또는 고상의 폴리이미드를 사용하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 상부면에 다수의 칩패드가 형성된 기판을 제공하는 단계와,상기 기판 상에 상기 칩패드를 덮도록 제 1절연층을 형성하는 단계와,상기 제 1절연층에 1차 자외선 조사에 의한 식각공정을 진행하여 상기 칩패드를 노출시키는 제 1개구부를 형성하는 단계와,상기 제 1절연층의 일정 영역에 2차 자외선 조사에 의한 식각공정을 진행시키어 볼랜드 형성을 위한 제 2개구부를 형성하는 단계와,상기 제 1절연층 상에 상기 제 1개구부를 통해 상기 칩패드와 일체로 연결되며, 상기 제 2개구부를 덮어 볼랜드를 갖는 메탈배선을 형성하는 단계와,상기 메탈배선을 덮고 상기 볼랜드를 노출시키며, 도전성 볼과 동일 폭을 가진 제 3개구부를 갖는 2절연층을 형성하는 단계와,상기 볼랜드 상에 양측이 상기 제 3개구부와 접촉되어 고정되도록 도전성 볼을 안착시키는 단계를 포함하고,상기 제 1개구부와 상기 제 2개구부는 상기 제 1절연층을 서로 다른 제 1및 제 2자외선 공정에 의해 형성하며, 상기 제 1및 제 2자외선 조사공정은 각각 다른 에너지값으로 진행하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 제 20항에 있어서, 상기 1차 자외선 조사는 50∼3000mJ/cm2 의 에너지값으로 진행되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 20항에 있어서, 싱기 2차 자외선 조사는 10∼2000mJ/cm2의 에너지값으로 진행되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 제 20항에 있어서, 상기 제 3개구부는 상기 제 2개구부 폭보다 크게 형성되는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
- 삭제
- 제 20항에 있어서, 상기 제 1 및 제 2절연층은 액상 또는 고상의 폴리이미드를 사용하는 것을 특징으로 하는 웨이퍼 레벨 패키지의 제조방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0047459A KR100447968B1 (ko) | 2001-08-07 | 2001-08-07 | 웨이퍼 레벨 패키지의 제조방법 |
US10/024,892 US6699782B2 (en) | 2001-08-07 | 2001-12-18 | Method of fabricating a wafer level package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0047459A KR100447968B1 (ko) | 2001-08-07 | 2001-08-07 | 웨이퍼 레벨 패키지의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030013125A KR20030013125A (ko) | 2003-02-14 |
KR100447968B1 true KR100447968B1 (ko) | 2004-09-10 |
Family
ID=19712943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0047459A KR100447968B1 (ko) | 2001-08-07 | 2001-08-07 | 웨이퍼 레벨 패키지의 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6699782B2 (ko) |
KR (1) | KR100447968B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111211105A (zh) * | 2018-11-22 | 2020-05-29 | 华邦电子股份有限公司 | 重布线层结构及其制造方法 |
US11063010B2 (en) | 2019-02-01 | 2021-07-13 | Winbond Electronics Corp. | Redistribution layer (RDL) structure and method of manufacturing the same |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100561638B1 (ko) * | 2000-01-21 | 2006-03-15 | 한국전자통신연구원 | 재배열 금속배선기술을 적용한 패키징 제조방법 |
JP4097660B2 (ja) * | 2005-04-06 | 2008-06-11 | シャープ株式会社 | 半導体装置 |
KR100647483B1 (ko) * | 2005-08-19 | 2006-11-23 | 삼성전자주식회사 | 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법 |
JP5017872B2 (ja) | 2006-02-06 | 2012-09-05 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
KR101067133B1 (ko) * | 2009-08-17 | 2011-09-22 | 삼성전기주식회사 | 원통형 캐패시터를 구비한 웨이퍼 레벨 패키지 및 그 제조방법 |
TWI541964B (zh) * | 2010-11-23 | 2016-07-11 | 矽品精密工業股份有限公司 | 半導體基板之製法 |
US8900929B2 (en) | 2012-03-21 | 2014-12-02 | Stats Chippac, Ltd. | Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation |
US8824145B2 (en) * | 2012-06-08 | 2014-09-02 | Infineon Technologies Ag | Electric device package and method of making an electric device package |
CN104584208B (zh) * | 2012-12-21 | 2018-01-30 | 松下知识产权经营株式会社 | 电子部件封装以及其制造方法 |
CN104584210B (zh) | 2012-12-21 | 2017-09-26 | 松下知识产权经营株式会社 | 电子部件封装件及其制造方法 |
JP5624700B1 (ja) | 2012-12-21 | 2014-11-12 | パナソニック株式会社 | 電子部品パッケージおよびその製造方法 |
JP5624697B1 (ja) | 2012-12-21 | 2014-11-12 | パナソニック株式会社 | 電子部品パッケージおよびその製造方法 |
US9825209B2 (en) | 2012-12-21 | 2017-11-21 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
US9559044B2 (en) | 2013-06-25 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with solder regions aligned to recesses |
US10804153B2 (en) | 2014-06-16 | 2020-10-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method to minimize stress on stack via |
CN106684003B (zh) * | 2016-12-29 | 2019-03-29 | 清华大学 | 扇出型封装结构及其制作方法 |
CN106847713B (zh) * | 2016-12-29 | 2019-03-01 | 清华大学 | 卷对卷制作扇出型封装结构的方法和扇出型封装结构 |
US10256179B2 (en) * | 2017-02-06 | 2019-04-09 | Nanya Technology Corporation | Package structure and manufacturing method thereof |
SG11202004703RA (en) | 2017-12-30 | 2020-07-29 | Intel Corp | Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating |
EP3732714A4 (en) * | 2017-12-30 | 2021-08-18 | INTEL Corporation | STRUCTURES WITH TWO PASSES WITHOUT MISALIGNMENT USING A PHOTOGRAPHIC DIELECTRIC STRUCTURE FILM AND TRANSPARENT SUBSTRATE WITH ELECTRIC PLATING |
CN109727949B (zh) * | 2019-02-22 | 2024-04-16 | 江苏汇成光电有限公司 | 一种硅片封装结构及其制备方法 |
KR20210152721A (ko) | 2020-06-09 | 2021-12-16 | 삼성전자주식회사 | 반도체 패키지 |
US11728308B2 (en) * | 2021-04-26 | 2023-08-15 | Nxp B.V. | Semiconductor device under bump structure and method therefor |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08340002A (ja) * | 1995-04-10 | 1996-12-24 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
US5736456A (en) * | 1996-03-07 | 1998-04-07 | Micron Technology, Inc. | Method of forming conductive bumps on die for flip chip applications |
KR20010004529A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
KR20010029196A (ko) * | 1999-09-30 | 2001-04-06 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
KR20010031276A (ko) * | 1997-10-20 | 2001-04-16 | 추후보정 | 큰 연성을 가진 땜납 볼을 사용한 칩 스케일 패키지 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW322613B (en) | 1997-03-10 | 1997-12-11 | guang-long Lin | Continuous method of implementing solder bump on semiconductor wafer electrode |
JPH1140624A (ja) | 1997-07-22 | 1999-02-12 | Mitsubishi Electric Corp | 半導体装置のリペア方法 |
US6118180A (en) | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
US6107180A (en) | 1998-01-30 | 2000-08-22 | Motorola, Inc. | Method for forming interconnect bumps on a semiconductor die |
US6259148B1 (en) * | 1998-08-13 | 2001-07-10 | International Business Machines Corporation | Modular high frequency integrated circuit structure |
US7498196B2 (en) * | 2001-03-30 | 2009-03-03 | Megica Corporation | Structure and manufacturing method of chip scale package |
-
2001
- 2001-08-07 KR KR10-2001-0047459A patent/KR100447968B1/ko active IP Right Grant
- 2001-12-18 US US10/024,892 patent/US6699782B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08340002A (ja) * | 1995-04-10 | 1996-12-24 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
US5736456A (en) * | 1996-03-07 | 1998-04-07 | Micron Technology, Inc. | Method of forming conductive bumps on die for flip chip applications |
KR20010031276A (ko) * | 1997-10-20 | 2001-04-16 | 추후보정 | 큰 연성을 가진 땜납 볼을 사용한 칩 스케일 패키지 |
KR20010004529A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
KR20010029196A (ko) * | 1999-09-30 | 2001-04-06 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111211105A (zh) * | 2018-11-22 | 2020-05-29 | 华邦电子股份有限公司 | 重布线层结构及其制造方法 |
US11063010B2 (en) | 2019-02-01 | 2021-07-13 | Winbond Electronics Corp. | Redistribution layer (RDL) structure and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US6699782B2 (en) | 2004-03-02 |
US20030032276A1 (en) | 2003-02-13 |
KR20030013125A (ko) | 2003-02-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100447968B1 (ko) | 웨이퍼 레벨 패키지의 제조방법 | |
KR100418000B1 (ko) | 반도체 장치 및 그 제조방법 | |
JPH03179763A (ja) | アンチヒューズ構造とそれを形成する方法 | |
CN110085564B (zh) | 晶圆级晶粒尺寸封装结构及其制造方法 | |
JPH08213469A (ja) | 集積回路の製造方法及び集積回路の製造に用いられる中間製品及び永久的に改造可能な集積回路 | |
KR100675296B1 (ko) | 퓨즈 패턴을 갖는 반도체소자 및 그 제조방법들 | |
US7067929B2 (en) | Semiconductor wafer, semiconductor device, circuit board, electronic instrument, and method for manufacturing semiconductor device | |
KR100422292B1 (ko) | 금속상부레벨의퓨즈,집적회로제조방법및집적회로상의퓨즈트리밍방법 | |
JPH11354560A (ja) | 半導体装置の製造方法 | |
JPH08340002A (ja) | 半導体装置の製造方法 | |
JP2003347471A (ja) | 半導体装置及びその製造方法 | |
KR100754895B1 (ko) | 반도체 장치 및 그 형성 방법 | |
US6127721A (en) | Soft passivation layer in semiconductor fabrication | |
KR20040100770A (ko) | 반도체 패키지장치 및 그 제조 방법 | |
JP2004342862A (ja) | 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びにマルチチップモジュール | |
KR100358567B1 (ko) | 반도체소자의 제조방법 | |
JP3173488B2 (ja) | 半導体集積回路装置及びその製造方法 | |
JP4274715B2 (ja) | 半導体装置及びその製造方法 | |
KR100372649B1 (ko) | 반도체 소자의 금속 패드 형성방법 | |
KR100219412B1 (ko) | 이중패드 구조를 갖는 반도체 장치 및 그 제조방법 | |
KR100324602B1 (ko) | 일괄패키지공정이가능한반도체장치의제조방법 | |
KR101116350B1 (ko) | 반도체 소자 제조방법 | |
KR970003633A (ko) | 반도체 소자의 금속 층간 절연막 형성방법 | |
JPH07130787A (ja) | 半導体装置のダミーパッド構造 | |
KR100480590B1 (ko) | 프로빙을 위한 패드를 갖는 반도체소자 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
J201 | Request for trial against refusal decision | ||
AMND | Amendment | ||
B701 | Decision to grant | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120720 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20130723 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20140723 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20150721 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20160721 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20170724 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20180725 Year of fee payment: 15 |