JP5367235B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5367235B2 JP5367235B2 JP2007151620A JP2007151620A JP5367235B2 JP 5367235 B2 JP5367235 B2 JP 5367235B2 JP 2007151620 A JP2007151620 A JP 2007151620A JP 2007151620 A JP2007151620 A JP 2007151620A JP 5367235 B2 JP5367235 B2 JP 5367235B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000005530 etching Methods 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 29
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 98
- 230000000052 comparative effect Effects 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
12 トンネル酸化膜
13 トラップ層
14 トップ酸化膜
16 ONO膜
17 被エッチング層
18 ワードライン
20 マスク層
21、22 中間層
23、24 上部層
30 BARC膜
32 フォトレジスト層
25 カバー膜
26 サイドウォール層
34 第1層
36 第2層
38 珪化金属層
Claims (7)
- 半導体基板上にシリコンからなる被エッチング層を形成する工程と、
前記被エッチング層上に、酸化シリコン膜からなる中間層とシリコンからなる上部層とからなりパターンを有するマスク層を形成する工程と、
前記マスク層をマスクに前記被エッチング層をエッチングし、かつ前記上部層を除去する工程と、
エッチングされた前記被エッチング層の間に酸化シリコン膜からなる第1層及び窒化シリコン層からなる第2層を順に形成して2つの被エッチング層間の隙間を埋める工程と、
前記第1層及び前記第2層を形成した後、前記被エッチング層上の中間層を除去する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記被エッチング層の上部に珪化金属層を形成する工程を有することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記珪化金属層を形成する工程は、前記被エッチング層上に金属層を形成する工程と、熱処理することにより、前記金属層と前記被エッチング層の上部とから珪化金属層を形成する工程であることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記マスク層を形成する工程は、前記被エッチング層上に前記中間層及び前記上部層を積層する工程と、
前記中間層及び前記上部層をパターニングする工程と、
パターニングされた前記中間層及び前記上部層上に酸化シリコン膜からなるカバー層を形成する工程と、
前記カバー層を前記上部層が露出するように全面エッチングし、パターンニングされた前記中間層及び前記上部層の側面にサイドウォール層を形成する工程と、を有することを特徴とする請求項1から3のいずれか一項記載の半導体装置の製造方法。 - 前記中間層及び前記上部層をパターニングする工程は、前記上部層上に反射防止膜及びフォトレジスト膜を形成する工程と、前記反射防止膜及び前記フォトレジスト膜をパターニングする工程と、前記フォトレジスト膜をマスクに前記中間層及び前記上部層をエッチングする工程を有することを特徴とする請求項4記載の半導体装置の製造方法。
- 被エッチング層を形成する工程と、
前記被エッチング層上に、中間層と前記被エッチング層と同じ元素からなる上部層とからなりパターンを有するマスク層を形成する工程と、
前記マスク層をマスクに被エッチング層をエッチングし、かつ前記上部層を除去する工程と、
エッチングされた前記被エッチング層の間に、前記中間層と同じ材料からなる第1層、及び第2層を形成して2つの被エッチング層間の隙間を埋める工程と、
前記第1層及び前記第2層を形成した後、前記被エッチング層上の中間層を除去する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記被エッチング層はゲート層であることを特徴とする請求項1から6のいずれか一項記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007151620A JP5367235B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置の製造方法 |
US12/130,537 US7682974B2 (en) | 2007-06-07 | 2008-05-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007151620A JP5367235B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008305965A JP2008305965A (ja) | 2008-12-18 |
JP5367235B2 true JP5367235B2 (ja) | 2013-12-11 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007151620A Expired - Fee Related JP5367235B2 (ja) | 2007-06-07 | 2007-06-07 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (1) | US7682974B2 (ja) |
JP (1) | JP5367235B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6236918B2 (ja) * | 2012-06-26 | 2017-11-29 | 大日本印刷株式会社 | ナノインプリント用テンプレートの製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5126231A (en) * | 1990-02-26 | 1992-06-30 | Applied Materials, Inc. | Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch |
JPH05152296A (ja) * | 1991-07-15 | 1993-06-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002217414A (ja) * | 2001-01-22 | 2002-08-02 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4801296B2 (ja) * | 2001-09-07 | 2011-10-26 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
TWI276153B (en) * | 2001-11-12 | 2007-03-11 | Hynix Semiconductor Inc | Method for fabricating semiconductor device |
JP4139266B2 (ja) * | 2003-05-13 | 2008-08-27 | スパンション エルエルシー | 半導体メモリ用のメモリ素子を製造する方法 |
US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
JP2007067118A (ja) * | 2005-08-30 | 2007-03-15 | Toshiba Corp | 半導体装置及びその製造方法 |
-
2007
- 2007-06-07 JP JP2007151620A patent/JP5367235B2/ja not_active Expired - Fee Related
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2008
- 2008-05-30 US US12/130,537 patent/US7682974B2/en active Active
Also Published As
Publication number | Publication date |
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US20090004838A1 (en) | 2009-01-01 |
US7682974B2 (en) | 2010-03-23 |
JP2008305965A (ja) | 2008-12-18 |
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