JP5582879B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims description 117
- 239000002184 metal Substances 0.000 claims description 75
- 239000000758 substrate Substances 0.000 claims description 36
- 239000011229 interlayer Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 12
- 238000002161 passivation Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 8
- 238000005336 cracking Methods 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- 229920001721 polyimide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Description
図1に、本実施形態の半導体装置の断面図を示す。図に示すように、トランジスタ等の能動素子が形成された素子領域11を表面に有する基板10上に、例えばTEOS(Tetra EthOxy Silane)などからなる絶縁層12が形成されている。基板10は、例えばSiや、SOI(Silicon On Insulator)などからなる。絶縁層12上には、例えばSiOCなどからなる比誘電率が2.5以下であるlow−k膜131a、131b、131cと、例えばSiOなどからなるcap膜132a、132b、132cとが交互に形成された層間絶縁膜13が形成されている。層間絶縁膜13上には、パシベーション膜14が形成されている。
本実施形態の半導体装置において、層間絶縁膜に開口窓を設ける構造は第1の実施形態と同様であるが、メタルパッドの構造が異なっている。
Claims (5)
- 基板上に形成された絶縁層と、
前記絶縁層上に形成された複数の低誘電率膜を含む層間絶縁膜と、
前記層間絶縁膜中にそれぞれ形成される複数の配線層及びビアからなる多層配線と、
前記複数の配線層のうち最下層の配線層より前記基板側に形成されたメタルパッドと、
前記メタルパッドの一部の領域上の前記絶縁層及び層間絶縁膜が除去されて形成された開口部と、
前記メタルパッド上に、前記複数の層間絶縁膜を貫通し、前記開口部を取り囲むように設けられるパッドリングと、
を備えることを特徴とする半導体装置。 - 前記半導体基板は素子が形成されている素子領域を有し、前記素子領域上の前記多層配線は、前記素子領域以外の領域である非素子領域上の前記多層配線を介して前記メタルパッドと接続されることを特徴とする請求項1に記載の半導体装置。
- 前記メタルパッドの上面が、前記絶縁層の上面と同一平面であることを特徴とする請求項1又は請求項2に記載の半導体装置。
- 前記メタルパッドの上面がAlを含む層であることを特徴とする請求項1から請求項3のいずれか1項に記載の半導体装置。
- 基板上に素子領域を形成し、
前記基板上に絶縁層を形成し、
前記素子領域上の前記絶縁層に、前記基板に到達するコンタクトホールを形成するとともに、前記素子領域以外の領域上の前記絶縁層に開口部を形成し、
前記コンタクトホール内にコンタクトを埋め込み形成し、
前記開口部内にメタルパッドを埋め込み形成し、
前記絶縁層上に複数の低誘電率膜を含む層間絶縁膜と、複数の配線層及びビアを有する多層配線を形成するとともに、前記メタルパッド上に前記複数の層間絶縁膜を貫通するようにパッドリングを形成し、
前記パッドリングに取り囲まれた領域の前記層間絶縁膜を除去し、前記メタルパッドを露出させる、
ことを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2010132160A JP5582879B2 (ja) | 2010-06-09 | 2010-06-09 | 半導体装置及びその製造方法 |
US13/048,176 US8536710B2 (en) | 2010-06-09 | 2011-03-15 | Semiconductor device and manufacturing method thereof |
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JP2010132160A JP5582879B2 (ja) | 2010-06-09 | 2010-06-09 | 半導体装置及びその製造方法 |
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JP2011258762A JP2011258762A (ja) | 2011-12-22 |
JP5582879B2 true JP5582879B2 (ja) | 2014-09-03 |
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JP2010132160A Expired - Fee Related JP5582879B2 (ja) | 2010-06-09 | 2010-06-09 | 半導体装置及びその製造方法 |
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DE3280187D1 (de) * | 1982-03-31 | 1990-07-05 | Ibm Deutschland | Festkoerper-fernsehkamera. |
US5543586A (en) * | 1994-03-11 | 1996-08-06 | The Panda Project | Apparatus having inner layers supporting surface-mount components |
JP3906522B2 (ja) * | 1997-06-10 | 2007-04-18 | ソニー株式会社 | 半導体装置の製造方法 |
JP3121311B2 (ja) * | 1998-05-26 | 2000-12-25 | 日本電気株式会社 | 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法 |
JP2000012604A (ja) * | 1998-06-22 | 2000-01-14 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2974022B1 (ja) * | 1998-10-01 | 1999-11-08 | ヤマハ株式会社 | 半導体装置のボンディングパッド構造 |
JP2001267323A (ja) | 2000-03-21 | 2001-09-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6362531B1 (en) * | 2000-05-04 | 2002-03-26 | International Business Machines Corporation | Recessed bond pad |
TW484196B (en) * | 2001-06-05 | 2002-04-21 | United Microelectronics Corp | Bonding pad structure |
JP4801296B2 (ja) * | 2001-09-07 | 2011-10-26 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP3811473B2 (ja) * | 2003-02-25 | 2006-08-23 | 富士通株式会社 | 半導体装置 |
US6864578B2 (en) * | 2003-04-03 | 2005-03-08 | International Business Machines Corporation | Internally reinforced bond pads |
US7067902B2 (en) * | 2003-12-02 | 2006-06-27 | International Business Machines Corporation | Building metal pillars in a chip for structure support |
US7071575B2 (en) * | 2004-11-10 | 2006-07-04 | United Microelectronics Corp. | Semiconductor chip capable of implementing wire bonding over active circuits |
JP2006190839A (ja) * | 2005-01-06 | 2006-07-20 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
WO2007102214A1 (ja) * | 2006-03-08 | 2007-09-13 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP5111878B2 (ja) * | 2007-01-31 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20080246152A1 (en) * | 2007-04-04 | 2008-10-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bonding pad |
JP4609497B2 (ja) * | 2008-01-21 | 2011-01-12 | ソニー株式会社 | 固体撮像装置とその製造方法、及びカメラ |
JP2010093161A (ja) * | 2008-10-10 | 2010-04-22 | Panasonic Corp | 半導体装置 |
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