JP4588046B2 - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
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- JP4588046B2 JP4588046B2 JP2007146244A JP2007146244A JP4588046B2 JP 4588046 B2 JP4588046 B2 JP 4588046B2 JP 2007146244 A JP2007146244 A JP 2007146244A JP 2007146244 A JP2007146244 A JP 2007146244A JP 4588046 B2 JP4588046 B2 JP 4588046B2
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- connection
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- metal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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- H05K2203/12—Using specific substances
- H05K2203/122—Organic non-polymeric compounds, e.g. oil, wax, thiol
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
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Description
図2〜図4は、実施の形態に係る回路装置の製造方法を示す工程断面図である。
Claims (9)
- 回路素子を搭載する配線基板であって、
基板と、
前記基板の一方の面に設けられた第1の接続部および第1の配線部と、
前記第1の接続部および前記第1の配線部の接続端子部分に開口が設けられた保護膜と、
を備え、
前記第1の接続部の膜厚が前記第1の配線部の膜厚より薄く、さらに、前記第1の配線部の接続端子部分が、前記第1の接続部を構成する金属よりイオン化傾向が小さい金属で被覆されていることを特徴とする配線基板。 - 前記基板の他方の面に設けられた第2の接続部と、前記基板を貫通し前記第1の接続部と前記第2の接続部とを電気的に接続する導通部とをさらに備え、前記第2の接続部は、前記第1の接続部を構成する金属よりイオン化傾向が小さい金属で被覆されていることを特徴とする請求項1に記載の配線基板。
- 基板と、
前記基板の一方の面に設けられた第1の接続部および第1の配線部と、
前記第1の接続部および前記第1の配線部の接続端子部分に開口が設けられた保護膜とを含む配線基板を備えた回路装置であって、
前記第1の接続部の膜厚が前記第1の配線部の膜厚より薄く、さらに、前記第1の配線部の接続端子部分が、前記第1の接続部を構成する金属よりイオン化傾向が小さい金属で被覆されており、
前記第1の接続部にフリップチップ接続された第1の回路素子と、前記第1の回路素子上に搭載した第2の回路素子と、をさらに備え、
前記第1の配線部の接続端子部分を被覆した金属と前記第2の回路素子とがワイヤを介して接続されていることを特徴とする回路装置。 - 前記基板の他方の面に設けられた第2の接続部と、前記基板を貫通し前記第1の接続部と前記第2の接続部とを電気的に接続する導通部とをさらに備え、前記第2の接続部は、前記第1の接続部を構成する金属よりイオン化傾向が小さい金属で被覆されていることを特徴とする請求項3に記載の回路装置。
- 基板の一方の面に第1の接続部および第1の配線部を形成する第1の工程と、
前記第1の接続部および前記第1の配線部の接続端子部分に開口が設けられた保護膜を形成する第2の工程と、
前記第1の配線部の接続端子部分を、前記第1の接続部を構成する金属に比べてイオン化傾向が小さい金属で被覆する第3の工程と、
前記開口から露出した前記第1の接続部にOSP処理を施すことにより、前記第1の接続部の表面にプレフラックス膜を形成する第4の工程と、
を備えることを特徴とする配線基板の製造方法。 - 前記第4の工程の前に、前記基板の他方の面に前記第1の接続部と電気的に接続された第2の接続部を形成する工程と、前記第2の接続部を前記第1の接続部を構成する金属に比べてイオン化傾向が小さい金属で被覆する工程とを備えることを特徴とする請求項5に記載の配線基板の製造方法。
- 請求項5または6に記載の配線基板の製造方法によって形成された配線基板に対して、前記第1の接続部に第1の回路素子を実装し、前記第1の回路素子上に第2の回路素子を搭載する第5の工程と、
前記第1の配線部の接続端子部分を被覆した金属と前記第2の回路素子とをワイヤを介して接続する第6の工程と、
を備えることを特徴とする回路装置の製造方法。 - 基板の一方の面に第1の接続部を形成する工程と、
前記基板の他方の面に前記第1の接続部と電気的に接続された第2の接続部を形成する工程と、
前記第2の接続部を前記第1の接続部を構成する金属に比べてイオン化傾向が小さい金属で被覆する工程と、
前記第1の接続部にOSP処理を施すことにより、前記第1の接続部の表面にプレフラックス膜を形成する工程と、
を備えることを特徴とする配線基板の製造方法。 - 請求項8に記載の配線基板の製造方法によって形成された配線基板に対して、前記第1の接続部に第1の回路素子を実装する工程と、
を備えることを特徴とする回路装置の製造方法。
Priority Applications (3)
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JP2007146244A JP4588046B2 (ja) | 2007-05-31 | 2007-05-31 | 回路装置およびその製造方法 |
US12/129,860 US8007285B2 (en) | 2007-05-31 | 2008-05-30 | Circuit device and manufacturing method therefor |
US13/195,657 US20110277318A1 (en) | 2007-05-31 | 2011-08-01 | Circuit device and manufacturing method therefor |
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JP2007146244A JP4588046B2 (ja) | 2007-05-31 | 2007-05-31 | 回路装置およびその製造方法 |
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JP2010095098A Division JP5121875B2 (ja) | 2010-04-16 | 2010-04-16 | 回路装置 |
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JP5581005B2 (ja) * | 2008-12-26 | 2014-08-27 | 株式会社東芝 | 半導体装置の製造方法 |
KR101095130B1 (ko) * | 2009-12-01 | 2011-12-16 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
KR101122140B1 (ko) * | 2010-05-11 | 2012-03-16 | 엘지이노텍 주식회사 | 단일층 인쇄회로기판 및 그 제조방법 |
US8844125B2 (en) | 2011-01-14 | 2014-09-30 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask and related devices |
JP6075825B2 (ja) * | 2012-04-26 | 2017-02-08 | 新光電気工業株式会社 | パッド形成方法 |
KR101572686B1 (ko) * | 2013-09-25 | 2015-11-27 | 주식회사 심텍 | 초박형 인쇄회로기판과, 이를 포함하는 반도체 패키지 및 그 제조 방법 |
JP7134617B2 (ja) * | 2017-10-30 | 2022-09-12 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
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- 2007-05-31 JP JP2007146244A patent/JP4588046B2/ja not_active Expired - Fee Related
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US20080299789A1 (en) | 2008-12-04 |
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US8007285B2 (en) | 2011-08-30 |
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