WO2022196123A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2022196123A1 WO2022196123A1 PCT/JP2022/003111 JP2022003111W WO2022196123A1 WO 2022196123 A1 WO2022196123 A1 WO 2022196123A1 JP 2022003111 W JP2022003111 W JP 2022003111W WO 2022196123 A1 WO2022196123 A1 WO 2022196123A1
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- Prior art keywords
- layer
- conductive member
- semiconductor device
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- insulating layer
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Definitions
- the present disclosure relates to semiconductor devices.
- Patent Document 1 discloses a semiconductor package including a conductive member, a semiconductor device, a bonding layer and a sealing resin.
- the semiconductor device is a flip chip type LSI.
- a semiconductor device has an element body, a plurality of electrodes, and a surface protective film.
- the surface protective film is made of polyimide and covers the bases of the electrodes.
- An embodiment of the present disclosure provides a semiconductor device capable of reducing stress on the sides of straight portions of conductive members.
- a semiconductor device includes: a semiconductor substrate; a first conductive member formed on the semiconductor substrate and having a first straight portion extending along a main surface of the semiconductor substrate; and an organic insulating layer that covers the first conductive member, and the first straight portion is formed on one side and the other side of the direction intersecting the longitudinal direction of the first straight portion in plan view It includes a first side edge formed of alternating curved lines.
- the semiconductor device According to the semiconductor device according to the embodiment of the present disclosure, it is possible to reduce the stress on the side portion of the first linear portion of the first conductive member.
- FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure.
- 2 is an enlarged plan view of the semiconductor chip of FIG. 1.
- FIG. 3 is an enlarged view (first embodiment) of a portion surrounded by a two-dot chain line III in FIG.
- FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG.
- FIG. 5 is an enlarged view (second embodiment) of a portion surrounded by a two-dot chain line III in FIG.
- FIG. 6 is a cross-sectional view along line VI-VI shown in FIG.
- FIG. 7 is a flowchart showing part of the manufacturing process of the semiconductor chip of FIG. 1 in the order of steps.
- FIG. 8 is a diagram for explaining the stress relaxation effect of the semiconductor device.
- a semiconductor device (1) is formed on a semiconductor substrate (4, 15) and a main surface (11) of the semiconductor substrate (4, 15). a first conductive member (25) having a first straight portion (36) extending along the ); and an organic insulation formed on the semiconductor substrate (4, 15) and covering the first conductive member (25). and a layer (55), wherein the first straight portion (36) is a curve (47 ).
- the first side edge of the first straight portion is a straight line
- variations in ambient temperature will cause the first straight line to collapse due to the difference in coefficient of thermal expansion between the first conductive member and the organic insulating layer.
- High stress may occur on the first side of the part. If an external force is applied to the organic insulating layer due to this stress during expansion and contraction due to temperature changes, the organic insulating layer may be distorted and the mechanical properties of the organic insulating layer may be degraded. Therefore, in the semiconductor device according to this embodiment, since the first side edge portion is formed with a curved line, the stress generated in the first side portion of the first linear portion can be dispersed. Thereby, the stress on the first side portion of the first straight portion of the first conductive member can be reduced as a whole. As a result, it is possible to suppress the strain generated in the organic insulating layer when it expands and contracts due to temperature changes.
- the first straight portion (36) includes a base portion (40) to which a bonding member can be connected, and a base portion (40) to the first straight portion. (36) a first side (41) comprising projections (44, 48) projecting in a direction transverse to the longitudinal direction and recesses (45, 49) recessed relative to said projections (44, 48); and the first side edge (46), in a plan view, connects the projections (44, 48) and the recesses (45, 49) along the longitudinal direction of the first straight portion (36).
- the stress generated in the first side portion including the convex portion and the concave portion is dispersed, so that when the joint member is connected to the base portion of the first straight portion, further stress is applied to the first straight portion.
- the stress distribution structure is constructed by selectively forming a convex portion and a concave portion on the first side portion of the first linear portion instead of the first conductive member being entirely meandering to form an S shape. It is Therefore, since it is not necessary to widen the installation space for the first conductive member according to this embodiment, it is possible to suppress an increase in the size of the semiconductor device.
- the base portion (40) is formed in a strip shape having a first width (W 2 ), and the base portion (40) has a width (W 2 ) may be 10 times or more the projection amount (P 1 ) of the projections (44, 48) from the base (40).
- the convex portion by forming the convex portion with a protrusion amount of about 1/10 of the width of the existing first conductive member (for example, wiring, electrode, etc.), the stress distribution in the first conductive member is reduced. effect can be achieved. Conversely, the first width of the base portion can be maintained relatively wide even if the stress distribution structure is formed by the convex portion and the concave portion. As a result, it is possible to leave many options (shape, thickness, etc. of the joining member) of the joining member that can be joined to the base portion.
- the first conductive member (25) includes a tip portion (39) including part of the first straight portion (36) and a corner portion (38). a second straight portion (37) connected to said first straight portion (36) via a said first side edge (46) connecting said first straight portion (36) and said first straight portion (36); It may be selectively formed in the first straight portion (36) of the two straight portions (37).
- the stress can be effectively relieved in the first conductive member. can be dispersed.
- the tip (39) of the first conductive member (25) has a first arc (51 ), and the first side edge (46) of the first conductive member (25) is smaller than the first radius of curvature (R 1 ) in plan view. It may have a second side surface (54) formed by a second arc (53) having a second radius of curvature (R2).
- the first conductive member (25) includes a first base layer (26) and an end face (29) of the first base layer (26) in cross-sectional view. ) and a first coating layer (27) laminated to the first base layer (26) so as to protrude laterally beyond the first coating layer ( 27) may be selectively formed.
- the curvilinear first side edge is selectively formed on the first coating layer and may not be formed on the first base layer. Therefore, the number of processes for forming the first side edge portion can be reduced.
- the organic insulating layer (55) has a pad opening that exposes the base portion (40) of the first straight portion (36) as a pad (14). (56).
- a bonding member such as a bonding wire can be connected to the base portion of the first straight portion through the pad opening.
- a second conductive member ( 59) In the semiconductor device (1) according to the embodiment of the present disclosure, a second conductive member ( 59).
- the aforementioned stress dispersion structure suppresses deterioration of the mechanical properties of the organic insulating layer around the second conductive member. Therefore, connection reliability between the first conductive member (first straight portion) and the second conductive member can be improved.
- the second conductive member (59) includes a third straight portion (72) extending along the main surface (11) of the semiconductor substrate (4, 15).
- the third straight portion (72) is formed by a curve (80) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the third straight portion (72) in plan view. It may also include a second side edge (79).
- the stress generated in the second side portion of the third linear portion can be dispersed.
- the stress on the second side portion of the third linear portion of the second conductive member can be reduced as a whole.
- the second conductive member (59) includes a second base layer (60) and an end surface (63) of the second base layer (60) in a cross-sectional view. ) and a second coating layer (61) laminated on the second base layer (60) so as to protrude laterally beyond the second coating layer ( 61) may be selectively formed.
- the curved second side edge is selectively formed on the second coating layer, and may not be formed on the second base layer. Therefore, the number of processes for forming the second side edge portion can be reduced.
- a semiconductor device (1) is formed between the first conductive member (25) and the semiconductor substrate (4, 15), and includes at least first inorganic insulating layers (18, 57) ) and a second inorganic insulating layer (19, 58) laminated on the first inorganic insulating layer (18, 57).
- a semiconductor device (1) includes an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first conductive member (25). You can stay.
- the stress on the first side portion of the first straight portion of the first conductive member can be reduced as described above. can be provided.
- FIG. 1 is a schematic perspective view of a semiconductor device 1 according to one embodiment of the present disclosure.
- the semiconductor device 1 in this embodiment is a so-called SOP (Small Outline Package).
- a semiconductor device 1 includes a sealing resin 2 , a die pad 3 , a semiconductor chip 4 , a conductive bonding material 5 , a plurality of lead terminals 6 and a plurality of conducting wires 7 .
- the sealing resin 2 may contain epoxy resin, for example.
- the sealing resin 2 may be called a resin package.
- the sealing resin 2 is formed in a rectangular parallelepiped shape.
- the sealing resin 2 has a first main surface 8 on one side, a second main surface 9 on the other side, and four side surfaces 10A, 10B, 10C, and 10D connecting the first main surface 8 and the second main surface 12. including.
- the four sides 10A-10D specifically include a first side 10A, a second side 10B, a third side 10C and a fourth side 10D.
- the first side surface 10A and the second side surface 10B face each other.
- the third side surface 10C and the fourth side surface 10D face each other.
- the die pad 3 is arranged inside the sealing resin 2 . Die pad 3 may be exposed from second main surface 9 . Die pad 3 includes a rectangular parallelepiped metal plate. The die pad 3 may contain at least one of Fe, Au, Ag, Cu and Al. The die pad 3 may have an outer surface on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer and a Cu plating layer is formed.
- the plurality of lead terminals 6 includes a first lead terminal 6A, a second lead terminal 6B, a third lead terminal 6C, a fourth lead terminal 6D, a fifth lead terminal 6E, a sixth lead terminal 6F, a seventh lead terminal 6G and a Includes 8 lead terminals 6H.
- the number of lead terminals 6 is adjusted according to the function of the semiconductor chip 4 and is not limited to the number shown in FIG.
- the four lead terminals 6A to 6D are arranged on the first side surface 10A side of the sealing resin 2. As shown in FIG. The four lead terminals 6A-6D are spaced apart from the die pad 3. As shown in FIG. The four lead terminals 6A-6D are arranged at intervals in the direction in which the first side surface 10A extends. The four lead terminals 6A to 6D are led out of the sealing resin 2 across the first side surface 10A from within the sealing resin 2. As shown in FIG.
- the four lead terminals 6E to 6H are arranged on the second side surface 10B side of the sealing resin 2 .
- the four lead terminals 6E-6H are spaced apart from the die pad 3. As shown in FIG.
- the four lead terminals 6E to 6H are arranged at intervals in the extending direction of the second side surface 10B.
- the four lead terminals 6E to 6H are drawn out of the sealing resin 2 from within the sealing resin 2 across the second side surface 10B.
- the plurality of lead terminals 6 may contain at least one of Fe, Au, Ag, Cu and Al.
- the plurality of lead terminals 6 may have an outer surface on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer and a Cu plating layer is formed.
- the semiconductor chip 4 includes, for example, an LSI (Large Scale Integration) chip.
- a semiconductor chip 4 is arranged on the die pad 3 .
- the semiconductor chip 4 has a first main surface 11 on one side and a second main surface 12 on the other side.
- a first main surface 11 of the semiconductor chip 4 is formed with a plurality of element regions 13 in which elements constituting an LSI circuit are built.
- the multiple element regions 13 may include, for example, a diode region 13A, a transistor region 13B, a resistive element region 13C, and the like.
- a plurality of pads 14 are formed on the first main surface 11 of the semiconductor chip 4 .
- a plurality of pads 14 are arranged on the first main surface 11 of the semiconductor chip 4 on the sides of the four lead terminals 6A to 6D and the four lead terminals 6E to 6H.
- a plurality of pads 14 are electrically connected to functional elements 16 (circuit elements constituting an LSI), which will be described later.
- the conductive bonding material 5 is interposed between the semiconductor chip 4 and the die pad 3 to bond the semiconductor chip 4 to the die pad 3 .
- the conductive bonding material 5 contains solder or conductive paste.
- the solder may be lead-free solder.
- the solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi and SnSbNi.
- the metal paste may contain at least one of Au, Ag and Cu.
- the conductive bonding material 5 is preferably made of silver paste. It is particularly preferred that the silver paste comprises a sintered silver paste.
- the sintered silver paste may contain a paste in which nano-sized or micro-sized Ag particles are dispersed in an organic solvent.
- the plurality of conducting wires 7 are adjusted according to the functions of the semiconductor chip 4 and are not limited to the number shown in FIG.
- a plurality of conducting wires 7 electrically connect a plurality of lead terminals 6 and a plurality of pads 14 .
- the plurality of conducting wires 7 include aluminum wires as an example of bonding wires in this embodiment.
- the plurality of conducting wires 7 may be gold wires or copper wires instead of aluminum wires.
- the package form of the semiconductor device 1 may be a form other than the SOP.
- the semiconductor device 1 includes TO (Transistor Outline), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or It may have various package forms such as SOJ (Small Outline J-leaded Package) or similar.
- FIG. 2 is an enlarged plan view of the semiconductor chip 4 in FIG. 1, showing the periphery of the pads 14.
- FIG. FIG. 3 is an enlarged view (first embodiment) of a portion surrounded by a two-dot chain line III in FIG.
- FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG.
- FIG. 1 a first form of the semiconductor chip 4 will be described with reference to FIGS. 2 to 4.
- FIG. 2 a first form of the semiconductor chip 4 will be described with reference to FIGS. 2 to 4.
- semiconductor chip 4 includes a semiconductor substrate 15 .
- Semiconductor substrate 15 may be, for example, an epitaxial substrate including a base substrate containing Si and an epitaxial layer grown on the base substrate. Also, since the semiconductor chip 4 is formed in layers, it may be called a semiconductor layer.
- the first main surface 11 and the second main surface 12 of the semiconductor chip 4 may be the first main surface 11 and the second main surface 12 of the semiconductor substrate 15 .
- a plurality of functional elements 16 are formed on the first main surface 11 of the semiconductor substrate 15 .
- the plurality of functional elements 16 may include circuit elements such as diodes, transistors, resistor elements, etc. that constitute an LSI.
- the insulating layer laminated structure 17 is formed on the first main surface 11 of the semiconductor substrate 15 .
- the insulating layer laminated structure 17 includes a laminated structure of a plurality of inorganic insulating layers.
- the insulating layer laminated structure 17 includes a first insulating layer 18, a second insulating layer 19, a third insulating layer 20, and a fourth insulating layer 21, which are sequentially laminated from the first main surface 11 of the semiconductor substrate 15. and a fifth insulating layer 22 .
- Each of the insulating layers 18 to 22 of the insulating layer stack structure 17 contains an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN).
- a plurality of wirings 23 and a plurality of vias 24 connecting the wirings 23 located one above the other are formed in each of the insulating layers 18 to 22 .
- the wiring 23 is electrically connected to the functional element 16 through vias 24 .
- the insulating layer laminated structure 17 is configured as a multilayer wiring structure in which the wiring 23 electrically connected to the functional element 16 is provided over the plurality of insulating layers 18-22.
- the plurality of wirings 23 may contain known wiring materials such as Cu and Al, for example.
- Via 24 may comprise known via materials such as W, for example.
- a first conductive member 25 is formed on the insulating layer laminated structure 17 .
- the first conductive member 25 is the uppermost layer wiring forming the pads 14 of the semiconductor chip 4, and may be called a first wiring layer.
- the first conductive member 25 is formed of a plurality of conductive layers, and may be called a first conductive layer.
- the first conductive member 25 includes a first base layer 26 and a first covering layer 27 laminated on the first base layer 26 .
- the first base layer 26 contains Cu, for example, and may contain a Cu plating layer in this embodiment.
- the first base layer 26 is connected to vias 24, for example. Thereby, the first conductive member 25 is electrically connected to the functional element 16 through the via 24 and the wiring 23 .
- the first covering layer 27 covers the first base layer 26 .
- the first covering layer 27 includes a first covering portion 28 that contacts the upper surface of the first base layer 26 and covers the first base layer 26, and a first protrusion that protrudes laterally beyond the end surface 29 of the first base layer 26. 30 integrally.
- a first step 32 is formed between the end face 29 of the first base layer 26 and the end face 31 of the first coating layer 27, the first step 32 corresponding to the amount of protrusion of the first protrusion 30.
- the first protruding portion 30 may hang downward (closer to the first main surface 11 of the semiconductor substrate 15 ) than the first covering portion 28 .
- the upper surface 33 of the first covering layer 27 may be inclined downward at both side portions with respect to the portion above the first base layer 26 .
- the first covering layer 27 may be formed thinner than the first base layer 26 .
- the first base layer 26 may have a thickness of 2 ⁇ m or more and 3 ⁇ m or less, and the first covering layer 27 may have a thickness of 1 ⁇ m or more and 2 ⁇ m or less.
- the first coating layer 27 includes a plurality of coating layers in this embodiment.
- the first covering layer 27 may include, for example, a first layer 34 in contact with the first base layer 26 and a second layer 35 laminated on the first layer 34 .
- the first layer 34 contains Ni, for example, and may contain a Ni plating layer in this embodiment.
- the second layer 35 contains Pd, for example, and may contain a Pd plating layer in this embodiment.
- the first coating layer 27 may further include an Au plating layer on the outermost surface.
- the first layer 34 and the second layer 35 are laminated over both the first covering portion 28 and the first projecting portion 30 . Thereby, the boundary between the first layer 34 and the second layer 35 may be exposed on the end surface 31 of the first covering layer 27 .
- first conductive member 25 extends over a wide area on first main surface 11 of semiconductor substrate 15 .
- the first conductive member 25 includes a first straight portion 36 and a second straight portion 37 in this embodiment.
- the first straight portion 36 and the second straight portion 37 are each formed in a strip shape in a plan view, and are integrally connected via a corner portion 38 .
- the first straight portion 36 and the second straight portion 37 are defined as band-like because they are relatively wide relative to their length.
- the first straight portion 36 and the second straight portion 37 may be defined as linear or the like when their width is very small compared to their length.
- the first straight portion 36 includes a tip portion 39 that is the end portion of the first conductive member 25 .
- An end (not shown) opposite to the tip 39 of the first conductive member 25 may be connected to the via 24 described above.
- the first straight portion 36 and the second straight portion 37 may intersect each other at an obtuse angle at the corner portion 38 like the two first conductive members 25 on the left side in FIG.
- the first straight portion 36 and the second straight portion 37 may intersect each other at a right angle at the corner portion 38 like the two first conductive members 25 on the right side of FIG. That is, the angle of the corner portion 38 may be an obtuse angle, a right angle, or an acute angle.
- the longitudinal direction (extending direction) of the first linear portion 36 is defined as a first direction X1
- the direction orthogonal to the first direction X1 is defined as a second direction Y1.
- the first linear portion 36 includes a strip-shaped first base portion 40 extending in the first direction X1 and first side portions 41 integrally formed on both sides of the first base portion 40 in the second direction Y1.
- the first base portion 40 has a first linear portion 36, for example, like the inner region of the first boundary portion 42 indicated by the dashed line in FIG. 3 or the inner region of the first boundary portion 43 indicated by the dashed line. This is a strip-shaped region that can be extracted from the first linear portion 36 and is set for convenience while maintaining substantially the same outer shape as .
- the first base portion 40 only needs to have a width that allows connection of a joint member such as the conducting wire 7 described above.
- the first base portion 40 may have a first width W2 that is 80% or more, preferably 90% or more of the width W1 of the first linear portion 36 .
- the width W1 of the first linear portion 36 may be 12 ⁇ m or more and 25 ⁇ m or less, and the first width W2 of the first base portion 40 may be 10 ⁇ m or more and 20 ⁇ m or less.
- the width W1 of the first linear portion 36 may be the distance between the top of the first protrusion 44 on one side and the top of the first protrusion 44 on the other side in the second direction Y1.
- the first side portion 41 is the outer region of the first boundary portion 42 or the outer region of the first boundary portion 43, and has an uneven structure that does not affect the outer shape of the first straight portion 36. ing. More specifically, the first side portion 41 includes a first convex portion 44 that protrudes from the first base portion 40 in the second direction Y1 and a first concave portion 45 that is recessed from the first convex portion 44 . In this embodiment, the first linear portion 36 has a first side edge portion 46 formed by a curved line that alternately bends to one side (left side of the paper surface) and the other side (right side of the paper surface) in the second direction Y1.
- the first side edge portion 46 is an outline line extending in the first direction X1 of the first straight portion 36 in plan view, and forms a side surface of the first straight portion 36 . Therefore, the first side portion 41 of the first linear portion 36 is a region between the first base portion 40 and the first side edge portion 46 , and the first convex portion 44 and the first convex portion 44 that constitute the first side portion 41
- the 1 concave portion 45 is formed by a curved first side edge portion 46 that is continuously connected along the first direction X1.
- the protrusion amount P1 of the first convex portion 44 of the first side portion 41 may be any protrusion amount that does not significantly change the outer shape of the first linear portion 36 .
- the protrusion amount P1 is 1/10 or less of the first width W2 (that is, the first width W2 is 10 times the protrusion amount P1). above).
- the first width W2 of the first base portion 40 can be maintained relatively wide. As a result, it is possible to leave many choices (for example, shapes and thicknesses of wires and wirings) for bonding members that can be bonded to the first base portion 40 .
- the curvilinear first side edge 46 may be a sinusoidal curve 47 extending along the first direction X1.
- the first side portion 41 includes a plurality of first curved protrusions 48 and a plurality of first curved recesses 49 alternately formed along the first direction X1.
- the first width W2 of the first base portion 40 may be five times or more the amplitude A1 of the sinusoidal curve 47 from the first reference line 50 indicated by the two -dot chain line in FIG.
- first boundary portions 42 and 43 between the first side portion 41 and the first base portion 40 are, for example, lines formed by connecting the top portions of the plurality of first concave portions 45 along the first direction X1. (Dash-and-dot line in FIG. 3), or by forming a line parallel to the line (dashed line in FIG. 3) at a position slightly inside the tops of the plurality of first recesses 45, this It may be set by a line.
- the distal end portion 39 of the first conductive member 25 has a first side surface 52 formed by a first circular arc 51 having a first radius of curvature R1 in plan view.
- the first side edge portion 46 is a second side surface formed by a second circular arc 53 having a second radius of curvature R2 smaller than the first radius of curvature R1 in plan view. 54.
- the first side edge portion 46 includes the sinusoidal curve 47
- the curved surfaces of the first curved protrusion 48 and the first curved recess 49 may be formed by the second arc 53 .
- a pair of first side edges 46 including a sinusoidal curve 47 are formed along the first direction X1. That is, both side edges of the first linear portion 36 may be the first side edge portions 46 including the sinusoidal curve 47 .
- the pair of sinusoidal curves 47 may include one sinusoidal curve 47A and the other sinusoidal curve 47B. Comparing the sine curve 47A on one side and the sine curve 47B on the other side, the formation positions of the first curved convex portions 48 may be different in the first direction X1. For example, in the second direction Y1, the first curved projections 48 of one sinusoidal curve 47A may be offset with respect to the first curved projections 48 of the other sinusoidal curve 47B.
- the first curved protrusion 48 of one sinusoidal curve 47A faces the first curved recess 49 of the other sinusoidal curve 47B in the second direction Y1.
- the first curved convex portion 48 of the other sinusoidal curve 47B faces the first curved concave portion 49 of the one sinusoidal curve 47A.
- the first curved convex portion 48 is divided into the first side portion 41 including one sinusoidal curve 47A and the first side portion including the other sinusoidal curve 47B. 41 are alternately formed.
- the first straight portion 36 has a first side portion 41 including a first curved protrusion 48 and a first curved recess 49 .
- the first side portion 41 may be defined as having a zigzag shape in plan view.
- the shape of the top portion of the first convex portion 44 that protrudes outward from the zigzag shape may correspond to the shape of the curved surface of the first curved convex portion 48 .
- first convex portion 44 and the first concave portion 45 described above are selectively formed in the first covering layer 27 of the first base layer 26 and the first covering layer 27 that constitute the first conductive member 25. may Of course, it may be formed on both the first base layer 26 and the first covering layer 27 . Further, the first convex portion 44 and the first concave portion 45 may be selectively formed on the first linear portion 36 or selectively formed on the second linear portion 37 as shown in FIG. Alternatively, it may be formed on both the first linear portion 36 and the second linear portion 37 .
- a protective layer 55 is formed on insulating layer laminated structure 17 so as to cover first conductive member 25 .
- the protective layer 55 contains an organic insulating resin.
- the organic insulating resin may contain, for example, epoxy resin, phenolic resin, polyimide, or the like.
- the protective layer 55 may be a resin layer having a higher coefficient of thermal expansion than the first conductive member 25 .
- the first thermal expansion coefficient of Cu forming the base layer of the first conductive member 25 is 16 ⁇ 10 ⁇ 6 /° C. or more and 18 ⁇ 10 ⁇ 6 /° C. or less, whereas the resin forming the protective layer 55
- the second coefficient of thermal expansion (for example, epoxy resin) may be 45 ⁇ 10 ⁇ 6 /° C.
- a pad opening 56 is formed in the protective layer 55 to expose the first base portion 40 of the first linear portion 36 as the pad 14 . Through this pad 14 , the conductor 7 is connected to the first conductive member 25 .
- FIG. 5 is an enlarged view (second form) of the portion surrounded by the two-dot chain line III in FIG.
- FIG. 6 is a cross-sectional view along line VI-VI shown in FIG.
- the wiring 23 and the via 24 are not formed in the insulating layer laminated structure 17 directly under the first conductive member 25 in the thickness direction of the semiconductor substrate 15 . . That is, the first conductive member 25 may face the semiconductor substrate 15 only through the insulating layer of the insulating layer laminated structure 17 without the conductive member such as the wiring 23 and the via 24 .
- the insulating layer laminated structure 17 in the second embodiment includes a laminated structure of a plurality of inorganic insulating layers, including a first insulating layer 57 and a second insulating layer 58, for example. Each insulating layer of the insulating layer laminated structure 17 contains an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN).
- the first insulating layer 57 and the second insulating layer 58 are made of the same kind of insulating material, but may be insulating layers formed by different manufacturing methods.
- the first insulating layer 57 may be a thermal silicon oxide film
- the second insulating layer 58 may be a CVD (Chemical Vapor Deposition) silicon oxide film.
- the first insulating layer 57 may have a denser film quality than the second insulating layer 58 .
- the first conductive member 25 Since the wiring 23 and the via 24 are not formed directly under the first conductive member 25, the first conductive member 25 does not have to be electrically connected to the functional element 16 formed on the semiconductor substrate 15. Instead of this connection, the first conductive member 25 is electrically connected to the functional element 16 mounted on the semiconductor device 1 different from the semiconductor device 1, for example, via the conductive wire 7 connected to the pad 14. good too.
- a second conductive member 59 is formed on the first conductive member 25 .
- the second conductive member 59 is a second layer of wiring laminated on the first conductive member 25, and may be called a second wiring layer.
- the second conductive member 59 is formed of a plurality of conductive layers, and may be called a second conductive layer.
- the second conductive member 59 includes a second base layer 60 and a second covering layer 61 laminated on the second base layer 60 .
- the second base layer 60 contains Cu, for example, and may contain a Cu plating layer in this embodiment.
- the second base layer 60 is connected to the first covering layer 27 of the first conductive member 25 . Thereby, the second conductive member 59 is physically connected to the first conductive member 25 .
- the second covering layer 61 covers the second base layer 60 .
- the second covering layer 61 includes a second covering portion 62 that contacts the upper surface of the second base layer 60 and covers the second base layer 60 , and a second protrusion that protrudes laterally beyond the end surface 63 of the second base layer 60 . 64 integrally.
- a second step 66 is formed between the end face 63 of the second base layer 60 and the end face 65 of the second covering layer 61, the second step 66 corresponding to the amount of protrusion of the second protrusion 64.
- the second projecting portion 64 may face the first base layer 26 of the first conductive member 25 with a portion of the protective layer 55 interposed therebetween.
- the second protruding portion 64 may hang down from the second covering portion 62 (the side closer to the first main surface 11 of the semiconductor substrate 15). Therefore, the upper surface 67 of the second covering layer 61 may be inclined downward at both side portions with respect to the portion above the second base layer 60 .
- the second covering layer 61 may be formed thinner than the second base layer 60 .
- the second base layer 60 may have a thickness of 2 ⁇ m or more and 3 ⁇ m or less
- the second covering layer 61 may have a thickness of 1 ⁇ m or more and 2 ⁇ m or less.
- the second coating layer 61 includes a plurality of coating layers in this embodiment.
- the second covering layer 61 may include, for example, a first layer 68 in contact with the second base layer 60 and a second layer 69 laminated on the first layer 68 .
- the first layer 68 contains Ni, for example, and may contain a Ni plating layer in this embodiment.
- the second layer 69 contains Pd, for example, and may contain a Pd plated layer in this embodiment.
- the second coating layer 61 may further include an Au plating layer on the outermost surface.
- a first layer 68 and a second layer 69 are laminated over both the second covering portion 62 and the second projecting portion 64 . Thereby, the boundary between the first layer 68 and the second layer 69 may be exposed on the end surface 65 of the second covering layer 61 .
- the second conductive member 59 is formed in a portion above the first conductive member 25 in the protective layer 55 and extends so as to overlap the first conductive member 25 in plan view. ing.
- the second conductive member 59 has a connecting portion 70 connected to the distal end portion 39 of the first conductive member 25 .
- the connecting portion 70 of the second conductive member 59 is indicated by dashed hatching. For clarity, only one second conductive member 59 is hatched.
- the second conductive member 59 is bent upward at the connecting portion 70 and extends obliquely upward away from the first conductive member 25 .
- the straight line shown at the end of the connecting portion 70 is the bent portion 71 of the second conductive member 59 .
- the first conductive member 25 extends toward one side in the first direction X1 with the connection portion 70 between the first conductive member 25 and the second conductive member 59 as a boundary.
- the second conductive member 59 extends toward the other side of the first direction X1. Accordingly, the first conductive member 25 and the second conductive member 59 are arranged linearly along the first direction X1.
- the second conductive member 59 includes a third linear portion 72 in this embodiment.
- the third linear portion 72 is formed in a strip shape in plan view. 5, the third linear portion 72 is defined as being strip-shaped because it is shown to be relatively wide with respect to its length. On the other hand, the third linear portion 72 may be defined as linear or the like when its width is very small relative to its length.
- the third straight portion 72 includes a tip portion 73 that is the end portion of the second conductive member 59 .
- a tip portion 73 of the second conductive member 59 is a portion physically connected to the first conductive member 25 .
- the longitudinal direction (extending direction) of the third linear portion 72 is defined as a third direction X2, and the direction orthogonal to the third direction X2 is defined as a fourth direction Y2.
- the third direction X2 and the fourth direction Y2 coincide with the first direction X1 and the second direction Y1 respectively .
- the third linear portion 72 includes a strip-shaped second base portion 74 extending in the third direction X2 and second side portions 75 integrally formed on both sides of the second base portion 74 in the fourth direction Y2. include.
- the second base portion 74 is extracted from the third straight portion 72 while maintaining substantially the same outer shape as the third straight portion 72, such as the inner region of the second boundary portion 76 shown in dashed lines in FIG. This is a strip-shaped area that can be set for convenience.
- the second base portion 74 may have a second width W 4 that is 80% or more, preferably 90% or more of the width W 3 of the third linear portion 72 .
- the width W3 of the third linear portion 72 may be 8 ⁇ m or more and 20 ⁇ m or less, and the second width W4 of the second base portion 74 may be 7 ⁇ m or more and 16 ⁇ m or less.
- the width W3 of the third linear portion 72 may be the distance between the top of the second protrusion 77 on one side and the top of the second protrusion 77 on the other side in the fourth direction Y2.
- the width W3 of the third linear portion 72 may be smaller than the width W1 of the first linear portion 36 of the first conductive member 25 .
- the second side portion 75 is an outer region of the second boundary portion 76 and has an uneven structure that does not affect the external shape of the third linear portion 72 . More specifically, the second side portion 75 includes a second protrusion 77 protruding from the second base portion 74 in the fourth direction Y2 and a second recess 78 recessed from the second protrusion 77 .
- the third linear portion 72 has a second side edge portion 79 formed by a curved line that alternately bends to one side (left side of the paper surface) and the other side (right side of the paper surface) in the fourth direction Y2.
- the second side edge portion 79 is an outline line extending in the third direction X2 of the third straight portion 72 in plan view, and forms a side surface of the third straight portion 72 . Therefore, the second side portion 75 of the third linear portion 72 is a region between the second base portion 74 and the second side edge portion 79, and includes the second convex portion 77 and the second side portion 77 that constitute the second side portion 75.
- the two recessed portions 78 are formed by curved second side edge portions 79 that are continuously connected along the third direction X2.
- the protrusion amount P2 of the second convex portion 77 of the second side portion 75 may be any protrusion amount that does not significantly change the external shape of the third linear portion 72 .
- the protrusion amount P2 is 1/10 or less of the second width W4 (that is, the second width W4 is 10 times the protrusion amount P2).
- the curvilinear second side edge 79 may be a sinusoidal curve 80 extending along the third direction X2.
- the second side portion 75 includes a plurality of second curved protrusions 81 and a plurality of second curved recesses 82 alternately formed along the third direction X2.
- the second width W4 of the second base portion 74 may be five times or more the amplitude A2 of the sinusoidal curve 80 from the second reference line 83 indicated by the two-dot chain line in FIG.
- the distal end portion 73 of the second conductive member 59 has a third side surface 85 formed by a third circular arc 84 having a third radius of curvature R3 in plan view.
- the second side edge portion 79 is a fourth side surface formed by a fourth arc 86 having a fourth radius of curvature R4 smaller than the third radius of curvature R3 in plan view. 87.
- the curved surfaces of the second curved protrusion 81 and the second curved recess 82 may be formed by the fourth arc 86 .
- a pair of second side edges 79 including the sinusoidal curve 80 are formed along the third direction X2. That is, both side edges of the third linear portion 72 may be the second side edge portions 79 including the sinusoidal curve 80 .
- a pair of sinusoidal curves 80 may include one sinusoidal curve 80A and the other sinusoidal curve 80B. Comparing one sinusoidal curve 80A and the other sinusoidal curve 80B, the formation positions of the second curved convex portions 81 may be different in the third direction X2. For example, in the fourth direction Y2, the second curved protrusions 81 of one sinusoidal curve 80A may be displaced from the second curved protrusions 81 of the other sinusoidal curve 80B.
- the second curved protrusion 81 of one sinusoidal curve 80A faces the second curved recess 82 of the other sinusoidal curve 80B in the fourth direction Y2.
- the second curved convex portion 81 of the other sinusoidal curve 80B faces the second curved concave portion 82 of the one sinusoidal curve 80A.
- the second curved convex portion 81 is divided into a second side portion 75 including one sinusoidal curve 80A and a second side portion including the other sinusoidal curve 80B. 75 are alternately formed.
- the third linear portion 72 has a second side portion 75 including the second curved convex portion 81 and the second curved concave portion 82, as shown in FIG.
- the second side portion 75 may be defined as having a zigzag shape in plan view.
- the top shape of the second protrusion 77 that protrudes outward from the zigzag shape may correspond to the shape of the curved surface of the second curved protrusion 81 .
- the above-described second convex portion 77 and second concave portion 78 are selectively formed in the second covering layer 61 of the second base layer 60 and the second covering layer 61 that constitute the second conductive member 59 . may Of course, it may be formed on both the second base layer 60 and the second covering layer 61 .
- FIG. 7 is a flowchart showing part of the manufacturing process of the semiconductor chip 4 in order of steps.
- a semiconductor wafer is prepared (step S1).
- the semiconductor wafer serves as the base of the semiconductor substrate 15 .
- functional elements 16 are formed on the main surface of the semiconductor wafer (step S2).
- Functional element 16 may be formed by known methods such as, for example, impurity implantation into semiconductor substrate 15 and deposition of a resistive conductive material.
- an insulating layer laminated structure 17 is formed on the semiconductor substrate 15 (step S3).
- the insulating layer laminated structure 17 may be formed, for example, using a known technique for forming a multilayer wiring structure.
- a first conductive member 25 is formed on the insulating layer laminated structure 17 (step S4).
- the first conductive member 25 is formed, for example, by growing the materials of the first base layer 26 and the first covering layer 27 on the insulating layer laminated structure 17 by plating.
- the first conductive member 25 is patterned (step S5).
- the first side portion 41 including the first convex portion 44 and the first concave portion 45 is formed in the first linear portion 36 of the first conductive member 25 .
- a mask having a pattern of the first side edge 46 (sinusoidal curve 47) is placed on the laminated structure of the first base layer 26 and the first coating layer 27, and the first coating is formed through this mask.
- a first protrusion 44 and a first recess 45 are formed by selectively etching layer 27 and first base layer 26 . If the semiconductor chip 4 includes the second conductive member 59, the second conductive member 59 may be formed by repeating the steps S4 and S5 after the first conductive member 25 is patterned.
- a protective layer 55 is formed on the insulating layer laminated structure 17 so as to cover the first conductive member 25 (step S6).
- the protective layer 55 may be formed by setting a semiconductor wafer in a mold and filling the mold with a resin material. After that, the protective layer 55 is cured by heat treatment.
- the semiconductor wafer is cut to cut out a plurality of semiconductor chips 4 . Through the steps including the above, the aforementioned semiconductor chip 4 is obtained.
- FIG. 8 is a diagram for explaining the stress relaxation effect due to the introduction of the concave-convex structure. More specifically, FIG. 8 shows the results of stress simulations applied to samples 1 and 2.
- FIG. Sample 1 is a wire 89 with a side edge 88 formed by the sinusoidal curve 47 described above.
- Sample 2 is a wiring 91 having a straight side edge 90 .
- the areas hatched with dashed lines are areas where the stress is 0.1% to 10% when the stress in the other white areas is 100%.
- the stress applied to the side portions of the wiring 89 is dispersed and reduced as a whole compared to sample 2 not employing the uneven structure. Do you get it.
- the semiconductor chip 4 since the first side edge portion 46 is formed by the sinusoidal curve 47, the first side portion 41 of the first linear portion 36 has Stress can be distributed. Thereby, the stress of the first side portion 41 of the first linear portion 36 of the first conductive member 25 can be reduced as a whole. As a result, it is possible to suppress strain generated in the protective layer 55 when it expands or contracts due to changes in ambient temperature (for example, changes in temperature during curing of the protective layer 55).
- the first conductive member 25 does not meander as a whole and form an S shape, but the first convex portion 44 and the first concave portion 45 are selectively formed on the first side portion 41 of the first linear portion 36 .
- a stress distribution structure is constructed by forming. Therefore, since it is not necessary to widen the installation space for the first conductive member 25, it is possible to suppress an increase in the size of the semiconductor chip 4. FIG.
- the semiconductor chip 4 has a second conductive member 59 and the second side edge portion 79 of the second conductive member 59 is also formed by a sinusoidal curve 80, the second side portion 75 of the third linear portion 72 may The generated stress can be dispersed. Thereby, the stress of the second side portion 75 of the third straight portion 72 of the second conductive member 59 can be reduced as a whole. As a result, strain generated in the protective layer 55 during expansion and contraction due to temperature changes can be suppressed.
- the wiring layer of an LSI chip was taken as an example of the first conductive member 25 and the second conductive member 59, but the characteristic structure of the first conductive member 25 and the second conductive member 59 is For example, it can also be employed in the structure of wiring, electrodes, and coils of other semiconductor devices. More specifically, it can be applied to the surface wiring of a wafer level CSP (Wafer level Chip Size Package), the coil junction of an insulating transformer element, and the like.
- a wafer level CSP Wafer level Chip Size Package
- the first straight portion (36) includes a base portion (40) having a joining area to which a joining member can be connected, and a direction intersecting the longitudinal direction of the first straight portion (36) from the base portion (40).
- a semiconductor device (1) comprising a protruding protrusion (44,48) and a first side (41) comprising a recess (45,49) recessed relative to said protrusion (44,48).
- the first side of the first straight portion is a straight line
- the first straight portion High stress may occur on the first side of the .
- the organic insulating layer may be distorted and the mechanical properties of the organic insulating layer may be degraded. Therefore, in the semiconductor device according to this embodiment, since the first side portion of the first straight portion includes the convex portion and the concave portion, the stress generated in the first side portion of the first straight portion can be dispersed. . Thereby, the stress on the first side portion of the first straight portion of the first conductive layer can be reduced as a whole.
- the convex portions (44, 48) and the concave portions (45, 49) are a plurality of curved convex portions ( 48) and a plurality of curved recesses (49).
- the convex portion and the concave portion are the curved convex portion and the concave portion, respectively, it is possible to prevent stress from concentrating on specific portions of the convex portion and the concave portion.
- the first side portion (41) of the first straight portion (36) is formed by a pair of sinusoidal curves (47A, 47B) extending along the longitudinal direction of the first straight portion (36).
- the semiconductor device (1) according to 1-2.
- the stress can be dispersed on each of the pair of first side portions of the first linear portion.
- the curved convex portion (48) of one of the sinusoidal curves (47A) faces the curved concave portion (49) of the other sinusoidal curve (47B).
- the curved convex portion (48) of the other sinusoidal curve (47B) faces the curved concave portion (49) of the one sinusoidal curve (47A).
- the curved convex portions are alternately formed on the first side portion on one side and the first side portion on the other side along the longitudinal direction of the first straight portion.
- the stress relaxation portion in the first straight portion does not appear intermittently along the longitudinal direction of the first straight portion, but alternately continues to the first side portion on one side and the first side portion on the other side. appears as Therefore, it is possible to reduce the unevenness of the stress relaxation portion in the first linear portion.
- the base portion (40) is formed in a strip shape having a first width (W 2 ), and the first width (W 2 ) of the base portion (40) is the amplitude (A).
- the semiconductor device ( 1 ) according to any one of Appendices 1-2 to 1-4, which is 5 times or more that of 1).
- the curved convex portion and the curved concave portion with a sinusoidal curve having an amplitude of about 1 ⁇ 5 of the width of the existing first conductive layer (for example, wiring, electrode, etc.),
- the effect of stress distribution in one conductive layer can be achieved.
- the first width of the base portion can be maintained relatively wide even if the stress dispersion structure is formed by the curved convex portion and the curved concave portion.
- the first conductive layer (25) is connected to the first straight portion (36) via a tip portion (39) including part of the first straight portion (36) and a corner portion (38). and a second straight portion (37);
- the sinusoidal curve (47) is selectively formed in the first straight portion (36) of the first straight portion (36) and the second straight portion (37), Supplementary Note 1-2 to Supplementary Note
- the semiconductor device (1) according to any one of 1-5.
- the tip portion (39) of the first conductive layer (25) has a first side surface (52) formed by a first arc (51) having a first radius of curvature (R 1 ) in plan view, At least one of the curved convex portion (48) and the curved concave portion (49) of the sine curve (47) has a second radius of curvature ( R2 ) smaller than the first radius of curvature (R1) in plan view. 7.
- the first conductive layer (25) includes a first base layer (26) and the first base layer (25) so as to protrude laterally beyond an end surface (29) of the first base layer (26) in a cross-sectional view.
- the first side portion (41) including the protrusions (44, 48) and the recesses (45, 49) is selectively formed in the first coating layer (27), Appendixes 1-1 to The semiconductor device (1) according to any one of Appendices 1-7.
- the first side portion including the convex portion and the concave portion is selectively formed on the first coating layer, and may not be formed on the first base layer. Therefore, it is possible to reduce the number of processes for forming the convex portion and the concave portion.
- the organic insulating layer (55) has a pad opening (56) that exposes the base portion (40) of the first linear portion (36) as a pad (14), Appendix 1-1 to Appendix The semiconductor device (1) according to any one of 1-8.
- a bonding member such as a bonding wire can be connected to the base portion of the first straight portion through the pad opening.
- Appendix 1-10 Appendices 1-1 to 1-8, further including a second conductive layer (59) connected to the base portion (40) of the first straight portion (36) in the organic insulating layer (55)
- the semiconductor device (1) according to any one of Claims 1 to 3.
- the aforementioned stress distribution structure suppresses deterioration of the mechanical properties of the organic insulating layer around the second conductive layer. Therefore, connection reliability between the first conductive layer (first straight portion) and the second conductive layer can be improved.
- the second conductive layer (59) has a third linear portion (72) extending along the main surface (11) of the semiconductor chip (4, 15);
- the third straight portion (72) includes second protrusions (77, 81) protruding in a direction intersecting the longitudinal direction of the third straight portion (72) and the second protrusions (77,
- the second conductive layer (59), in a cross-sectional view, includes a second base layer (60) and the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60).
- the second side portion (75) including the second protrusions (77, 81) and the second recesses (78, 82) is selectively formed in the second coating layer (61).
- the semiconductor device (1) according to 1-11.
- the second side portion including the second convex portion and the second concave portion is selectively formed on the second covering layer, and may not be formed on the second base layer. Therefore, the number of processes for forming the second protrusion and the second recess can be reduced.
- Appendix 1-13 formed between the first conductive layer (25) and the semiconductor chip (4, 15), at least the first inorganic insulating layer (18, 57) and on the first inorganic insulating layer (18, 57)
- the semiconductor device (1) according to any one of Appendices 1-1 to 1-12, including an insulating layer laminated structure (17) including second inorganic insulating layers (19, 58) laminated on the semiconductor device (1).
- Any one of Appendices 1-1 to 1-13 including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first conductive layer (25).
- the semiconductor device (1) according to 1.
- the stress on the first side portion of the first straight portion of the first conductive layer can be reduced as described above.
- the first wiring layer (25) has a first side portion (41) including a zigzag shape (47) formed along the extending direction of the first wiring layer (25) in plan view.
- the first side of the first wiring layer may High stress may occur on the first side of the . If an external force is applied to the organic insulating layer due to this stress during expansion and contraction due to temperature changes, the organic insulating layer may be distorted and the mechanical properties of the organic insulating layer may be degraded. Therefore, in the semiconductor device according to this embodiment, since the first side portion of the first wiring layer includes a zigzag shape, the stress generated in the first side portion of the first wiring layer can be dispersed. As a result, the stress on the first side portion of the first wiring layer can be reduced as a whole.
- the first side portion (41) of the first wiring layer (25) is formed by a pair of zigzag shapes (47A, 47B) extending along the extending direction of the first wiring layer (25), A semiconductor device (1) according to Appendix 2-2.
- one of the zigzag-shaped (47A) protrusions (44, 48) is the other zigzag-shaped (47B) of recesses (45, 49).
- the other zigzag-shaped (47B) protrusions (44, 48) face one of the zigzag-shaped (47A) recesses (45, 49), described in Appendix 2-3
- the convex portions are alternately formed on the first side portion on one side and the first side portion on the other side.
- the stress relaxation portion in the first wiring layer does not appear intermittently along the longitudinal direction of the first wiring layer, but alternately continues to the first side portion on one side and the first side portion on the other side. appears as Therefore, it is possible to reduce the unevenness of the stress relaxation portions in the first wiring layer.
- the first wiring layer (25) includes a first straight portion (36) including a tip portion (39) and a second wiring layer (36) connected to the first straight portion (36) via a corner portion (38). a straight portion (37);
- the zigzag shape (47) is selectively formed in the first straight portion (36) of the first straight portion (36) and the second straight portion (37), Supplementary Note 2-2 to Supplementary Note
- the semiconductor device (1) according to any one of 2-4.
- the tip portion of the first wiring layer (25) is formed of a second arc (51) having a second radius of curvature ( R1 ) larger than the first radius of curvature (R2) in plan view. , the semiconductor device (1) according to appendix 2-5.
- the first wiring layer (25) includes a first base layer (26) and an end surface (29) of the first base layer (26) in a cross-sectional view so as to protrude laterally from the first base layer (26).
- the first side portion including the zigzag shape is selectively formed on the first coating layer, and may not be formed on the first base layer. Therefore, the number of processes for forming the zigzag shape can be reduced.
- Appendix 2-8 Any one of Appendices 2-1 to 2-7, wherein the organic insulating layer (55) has a pad opening (56) exposing the first wiring layer (25) as a pad (14). 1. A semiconductor device (1) according to the above paragraph.
- a bonding member such as a bonding wire can be connected to the first wiring layer through the pad opening.
- Appendix 2-9 According to any one of Appendixes 2-1 to 2-7, further including a second wiring layer (59) connected to the first wiring layer (25) in the organic insulating layer (55).
- the second wiring layer (59) has a second side portion (75) including a second zigzag shape (80) formed along the extending direction of the second wiring layer (59) in plan view.
- the semiconductor device (1) according to Appendix 2-9, wherein:
- the second wiring layer (59) includes a second base layer (60) and the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60) in a cross-sectional view. a second coating layer (61) laminated to (60); The semiconductor device (1) according to claim 2-10, wherein said second side (75) comprising said second zigzag shape (80) is selectively formed in said second covering layer (61).
- the second side portion including the second zigzag shape is selectively formed on the second coating layer, and may not be formed on the second base layer. Therefore, the number of processes for forming the second zigzag shape can be reduced.
- the semiconductor device (1) according to any one of Appendices 2-1 to 2-11, comprising an insulating layer laminated structure (17) including second inorganic insulating layers (19, 58) laminated on the semiconductor device (1).
- Appendix 2-13 Any one of Appendices 2-1 to 2-12, including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first wiring layer (25).
- the first straight portion (36) is formed by a curved line (47) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the first straight portion (36) in a plan view.
- a semiconductor device (1) comprising an edge (46).
- the resin layer expands more than the first conductive member when the ambient temperature fluctuates. High stress may occur on the first side of the straight portion.
- the resin layer may be distorted and the mechanical properties of the resin layer may be degraded. Therefore, in the semiconductor device according to this embodiment, since the first side edge portion is formed with a curved line, the stress generated in the first side portion of the first linear portion can be dispersed. Thereby, the stress on the first side portion of the first straight portion of the first conductive member can be reduced as a whole.
- the first straight portion (36) includes a base portion (40) to which a joining member can be connected, and a convex portion protruding from the base portion (40) in a direction crossing the longitudinal direction of the first straight portion (36). (44, 48) and a first side (41) comprising recesses (45, 49) recessed relative to said protrusions (44, 48); The first side edge (46) connects the projections (44, 48) and the recesses (45, 49) continuously along the longitudinal direction of the first straight portion (36) in plan view.
- the semiconductor device (1) according to Appendix 3-1, formed by curve (47).
- the stress generated in the first side portion including the convex portion and the concave portion is dispersed, so that when the joint member is connected to the base portion of the first straight portion, further stress is applied to the first straight portion.
- the stress distribution structure is constructed by selectively forming a convex portion and a concave portion on the first side portion of the first linear portion instead of the first conductive member being entirely meandering to form an S shape. It is Therefore, since it is not necessary to widen the installation space for the first conductive member according to this embodiment, it is possible to suppress an increase in the size of the semiconductor device.
- the base portion (40) is formed in a band shape having a first width (W 2 ), Note 3-, wherein the first width (W 2 ) of the base portion (40) is at least 10 times the projection amount (P 1 ) of the projections (44, 48) from the base portion (40) 3.
- the convex portion by forming the convex portion with a protrusion amount of about 1/10 of the width of the existing first conductive member (for example, wiring, electrode, etc.), the stress distribution in the first conductive member is reduced. effect can be achieved. Conversely, the first width of the base portion can be maintained relatively wide even if the stress distribution structure is formed by the convex portion and the concave portion. As a result, it is possible to leave many options (shape, thickness, etc. of the joining member) of the joining member that can be joined to the base portion.
- the first conductive member (25) is connected to the first straight portion (36) via a tip portion (39) including part of the first straight portion (36) and a corner portion (38).
- the tip (39) of the first conductive member (25) has a first side surface (52) formed by a first arc (51) having a first radius of curvature (R 1 ) in plan view
- the first side edge (46) of the first conductive member (25) has a second arc (53) having a second radius of curvature (R2) smaller than the first radius of curvature (R1) in plan view. ).
- the first conductive member (25) includes a first base layer (26) and the first base layer (26) so as to protrude laterally beyond an end face (29) of the first base layer (26) in a cross-sectional view. a first coating layer (27) laminated to (26);
- the semiconductor device (1) according to any one of Appendixes 3-1 to 3-5, wherein the first side edge (46) is selectively formed on the first covering layer (27). .
- the curvilinear first side edge is selectively formed on the first covering layer and may not be formed on the first base layer. Therefore, the number of processes for forming the first side edge portion can be reduced.
- Appendix 3-7 The semiconductor according to appendix 3-2, wherein the resin layer (55) has a pad opening (56) exposing the base portion (40) of the first straight portion (36) as a pad (14).
- Device (1) The semiconductor according to appendix 3-2, wherein the resin layer (55) has a pad opening (56) exposing the base portion (40) of the first straight portion (36) as a pad (14).
- a bonding member such as a bonding wire can be connected to the base portion of the first straight portion through the pad opening.
- the second conductive member (59) has a third straight portion (72) extending along the main surface (11) of the semiconductor substrate (4, 15),
- the third straight portion (72) has a second side formed by a curve (80) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the third straight portion (72) in plan view.
- the second conductive member (59) includes a second base layer (60) and the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60) in a cross-sectional view. a second coating layer (61) laminated to (60); The semiconductor device (1) according to Appendix 3-8 or Appendix 3-9, wherein the second side edge (79) is selectively formed on the second covering layer (61).
- the curved second side edge is selectively formed on the second covering layer, and may not be formed on the second base layer. Therefore, the number of processes for forming the second side edge portion can be reduced.
- Appendix 3-11 formed between the first conductive member (25) and the semiconductor substrate (4, 15), at least the first inorganic insulating layer (18, 57) and on the first inorganic insulating layer (18, 57)
- the semiconductor device (1) according to any one of Appendices 3-1 to 3-10, comprising an insulating layer laminate structure (17) including second inorganic insulating layers (19, 58) laminated on the substrate.
- Any one of appendices 3-1 to 3-11 including an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first conductive member (25).
- the semiconductor device (1) according to 1.
- the stress on the first side portion of the first straight portion of the first conductive member can be reduced as described above, so that a semiconductor device including an integrated circuit with high insulation reliability of the resin layer can be provided. can do.
- Reference Signs List 1 semiconductor device 2: sealing resin 3: die pad 4: semiconductor chip 5: conductive bonding material 6: lead terminal 7: conducting wire 8: first main surface 9: second main surface 10A: first side surface 10B: second side surface 10C: third side surface 10D: fourth side surface 11: first main surface 12: second main surface 13: element region 13A: diode region 13B: transistor region 13C: resistance element region 14: pad 15: semiconductor substrate 16: functional element 17 : Insulating layer laminated structure 18 : First insulating layer 19 : Second insulating layer 20 : Third insulating layer 21 : Fourth insulating layer 22 : Fifth insulating layer 23 : Wiring 24 : Via 25 : First conductive member 26 : First base layer 27 : First covering layer 28 : First covering portion 29 : End surface 30 : First projecting portion 31 : End surface 32 : First step 33 : Upper surface 34 : First layer 35 : Second layer 36 : First Straight portion 37 : Second straight portion 38 : Corner portion 39 : Tip
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Abstract
Description
まず、本開示の実施形態を列記して説明する。
<本開示の実施形態の詳細な説明>
次に、本開示の実施形態を、添付図面を参照して詳細に説明する。なお、以下の詳細な説明において、序数が付された名称の構成要素が複数存在するが、当該序数と、特許請求の範囲に記載の構成要素の序数とは、必ずしも一致するものではない。
[付記1-1]
半導体チップ(4,15)と、
前記半導体チップ(4,15)上に形成され、前記半導体チップ(4,15)の主面(11)に沿って延びる第1直線部(36)を有する第1導電層(25)と、
前記半導体チップ(4,15)上に形成され、前記第1導電層(25)を被覆する有機系絶縁層(55)とを含み、
前記第1直線部(36)は、接合部材が接続され得る接合領域を有するベース部(40)と、前記ベース部(40)から前記第1直線部(36)の長手方向に交差する方向に突出する凸部(44,48)および前記凸部(44,48)に対して窪んだ凹部(45,49)を含む第1側部(41)とを含む、半導体装置(1)。
[付記1-2]
前記凸部(44,48)および前記凹部(45,49)は、前記第1直線部(36)の長手方向に沿って延びる正弦曲線(47)によって交互に形成された複数の湾曲凸部(48)および複数の湾曲凹部(49)を含む、付記1-1に記載の半導体装置(1)。
[付記1-3]
前記第1直線部(36)の前記第1側部(41)は、前記第1直線部(36)の長手方向に沿って延びる一対の正弦曲線(47A,47B)によって形成されている、付記1-2に記載の半導体装置(1)。
[付記1-4]
前記第1直線部(36)の長手方向に交差する方向において、一方の前記正弦曲線(47A)の前記湾曲凸部(48)が他方の前記正弦曲線(47B)の湾曲凹部(49)に対向しており、他方の前記正弦曲線(47B)の前記湾曲凸部(48)が一方の前記正弦曲線(47A)の湾曲凹部(49)に対向している、付記1-3に記載の半導体装置(1)。
[付記1-5]
前記ベース部(40)は、第1幅(W2)を有する帯状に形成されており
前記ベース部(40)の前記第1幅(W2)は、前記正弦曲線(47)の振幅(A1)の5倍以上である、付記1-2~付記1-4のいずれか一項に記載の半導体装置(1)。
[付記1-6]
前記第1導電層(25)は、前記第1直線部(36)の一部を含む先端部(39)と、コーナ部(38)を介して前記第1直線部(36)に対して接続された第2直線部(37)とを含み、
前記正弦曲線(47)は、前記第1直線部(36)および前記第2直線部(37)のうち前記第1直線部(36)に選択的に形成されている、付記1-2~付記1-5のいずれか一項に記載の半導体装置(1)。
[付記1-7]
前記第1導電層(25)の前記先端部(39)は、平面視において第1曲率半径(R1)を有する第1円弧(51)で形成された第1側面(52)を有し、
前記正弦曲線(47)の前記湾曲凸部(48)および前記湾曲凹部(49)の少なくとも一方は、平面視において前記第1曲率半径(R1)よりも小さい第2曲率半径(R2)を有する第2円弧(53)で形成された第2側面(54)を有している、付記1-6に記載の半導体装置(1)。
[付記1-8]
前記第1導電層(25)は、断面視において、第1ベース層(26)と、前記第1ベース層(26)の端面(29)よりも側方に突出するように前記第1ベース層(26)に積層された第1被覆層(27)とを含み、
前記凸部(44,48)および前記凹部(45,49)を含む前記第1側部(41)は、前記第1被覆層(27)に選択的に形成されている、付記1-1~付記1-7のいずれか一項に記載の半導体装置(1)。
[付記1-9]
前記有機系絶縁層(55)は、前記第1直線部(36)の前記ベース部(40)をパッド(14)として露出させるパッド開口(56)を有している、付記1-1~付記1-8のいずれか一項に記載の半導体装置(1)。
[付記1-10]
前記有機系絶縁層(55)内において、前記第1直線部(36)の前記ベース部(40)に接続された第2導電層(59)をさらに含む、付記1-1~付記1-8のいずれか一項に記載の半導体装置(1)。
[付記1-11]
前記第2導電層(59)は、前記半導体チップ(4,15)の主面(11)に沿って延びる第3直線部(72)を有し、
前記第3直線部(72)は、平面視において、前記第3直線部(72)の長手方向に交差する方向に突出する第2凸部(77,81)および前記第2凸部(77,81)に対して窪んだ第2凹部(78,82)を含む第2側部(75)を含む、付記1-10に記載の半導体装置(1)。
[付記1-12]
前記第2導電層(59)は、断面視において、第2ベース層(60)と、前記第2ベース層(60)の端面(63)よりも側方に突出するように前記第2ベース層(60)に積層された第2被覆層(61)とを含み、
前記第2凸部(77,81)および前記第2凹部(78,82)を含む前記第2側部(75)は、前記第2被覆層(61)に選択的に形成されている、付記1-11に記載の半導体装置(1)。
[付記1-13]
前記第1導電層(25)と前記半導体チップ(4,15)との間に形成され、少なくとも第1無機系絶縁層(18,57)および前記第1無機系絶縁層(18,57)上に積層された第2無機系絶縁層(19,58)を含む絶縁層積層構造(17)を含む、付記1-1~付記1-12のいずれか一項に記載の半導体装置(1)。
[付記1-14]
前記半導体チップ(4,15)に形成され、前記第1導電層(25)に電気的に接続された集積回路素子(16)を含む、付記1-1~付記1-13のいずれか一項に記載の半導体装置(1)。
[付記2-1]
半導体チップ(4,15)と、
前記半導体チップ(4,15)上に形成され、前記半導体チップ(4,15)の主面(11)に沿って延びる第1配線層(25)と、
前記半導体チップ(4,15)上に形成され、前記第1配線層(25)を被覆する有機系絶縁層(55)とを含み、
前記第1配線層(25)は、平面視において前記第1配線層(25)の延出方向に沿って形成されたジグザグ形状(47)を含む第1側部(41)を有している、半導体装置(1)。
[付記2-2]
前記ジグザグ形状(47)の頂部は、平面視において第1曲率半径を(R2)有する第1円弧(53)で形成されている、付記2-1に記載の半導体装置(1)。
[付記2-3]
前記第1配線層(25)の前記第1側部(41)は、前記第1配線層(25)の延出方向に沿って延びる一対のジグザグ形状(47A,47B)によって形成されている、付記2-2に記載の半導体装置(1)。
[付記2-4]
前記第1配線層(25)の延出方向に交差する方向において、一方の前記ジグザグ形状(47A)の凸部(44,48)が他方の前記ジグザグ形状(47B)の凹部(45,49)に対向しており、他方の前記ジグザグ形状(47B)の凸部(44,48)が一方の前記ジグザグ形状(47A)の凹部(45,49)に対向している、付記2-3に記載の半導体装置(1)。
[付記2-5]
前記第1配線層(25)は、先端部(39)を含む第1直線部(36)と、コーナ部(38)を介して前記第1直線部(36)に対して接続された第2直線部(37)とを含み、
前記ジグザグ形状(47)は、前記第1直線部(36)および前記第2直線部(37)のうち前記第1直線部(36)に選択的に形成されている、付記2-2~付記2-4のいずれか一項に記載の半導体装置(1)。
[付記2-6]
前記第1配線層(25)の前記先端部は、平面視において前記第1曲率半径(R2)よりも大きい第2曲率半径(R1)を有する第2円弧(51)で形成されている、付記2-5に記載の半導体装置(1)。
[付記2-7]
前記第1配線層(25)は、断面視において、第1ベース層(26)と、前記第1ベース層(26)の端面(29)よりも側方に突出するように前記第1ベース層(26)に積層された第1被覆層(27)とを含み、
前記ジグザグ形状(47)を含む前記第1側部(41)は、前記第1被覆層(27)に選択的に形成されている、付記2-1~付記2-6のいずれか一項に記載の半導体装置(1)。
[付記2-8]
前記有機系絶縁層(55)は、前記第1配線層(25)をパッド(14)として露出させるパッド開口(56)を有している、付記2-1~付記2-7のいずれか一項に記載の半導体装置(1)。
[付記2-9]
前記有機系絶縁層(55)内において、前記第1配線層(25)に接続された第2配線層(59)をさらに含む、付記2-1~付記2-7のいずれか一項に記載の半導体装置(1)。
[付記2-10]
前記第2配線層(59)は、平面視において前記第2配線層(59)の延出方向に沿って形成された第2ジグザグ形状(80)を含む第2側部(75)を有している、付記2-9に記載の半導体装置(1)。
[付記2-11]
前記第2配線層(59)は、断面視において、第2ベース層(60)と、前記第2ベース層(60)の端面(63)よりも側方に突出するように前記第2ベース層(60)に積層された第2被覆層(61)とを含み、
前記第2ジグザグ形状(80)を含む前記第2側部(75)は、前記第2被覆層(61)に選択的に形成されている、付記2-10に記載の半導体装置(1)。
[付記2-12]
前記第1配線層(25)と前記半導体チップ(4,15)との間に形成され、少なくとも第1無機系絶縁層(18,57)および前記第1無機系絶縁層(18,57)上に積層された第2無機系絶縁層(19,58)を含む絶縁層積層構造(17)を含む、付記2-1~付記2-11のいずれか一項に記載の半導体装置(1)。
[付記2-13]
前記半導体チップ(4,15)に形成され、前記第1配線層(25)に電気的に接続された集積回路素子(16)を含む、付記2-1~付記2-12のいずれか一項に記載の半導体装置(1)。
[付記3-1]
半導体基板(4,15)と、
前記半導体基板(4,15)上に形成され、前記半導体基板(4,15)の主面(11)に沿って延びる第1直線部(36)を有し、第1熱膨張係数を有する第1導電部材(25)と、
前記半導体基板(4,15)上に形成され、前記第1導電部材(25)を被覆し、前記第1熱膨張係数よりも高い第2熱膨張係数を有する樹脂層(55)とを含み、
前記第1直線部(36)は、平面視において、前記第1直線部(36)の長手方向に交差する方向の一方側および他方側に交互に曲がる曲線(47)で形成された第1側縁部(46)を含む、半導体装置(1)。
[付記3-2]
前記第1直線部(36)は、接合部材が接続され得るベース部(40)と、前記ベース部(40)から前記第1直線部(36)の長手方向に交差する方向に突出する凸部(44,48)および前記凸部(44,48)に対して窪んだ凹部(45,49)を含む第1側部(41)とを含み、
前記第1側縁部(46)は、平面視において、前記凸部(44,48)および前記凹部(45,49)を前記第1直線部(36)の長手方向に沿って連続して繋ぐ曲線(47)によって形成されている、付記3-1に記載の半導体装置(1)。
[付記3-3]
前記ベース部(40)は、第1幅(W2)を有する帯状に形成されており、
前記ベース部(40)の前記第1幅(W2)は、前記ベース部(40)からの前記凸部(44,48)の突出量(P1)の10倍以上である、付記3-2に記載の半導体装置(1)。
[付記3-4]
前記第1導電部材(25)は、前記第1直線部(36)の一部を含む先端部(39)と、コーナ部(38)を介して前記第1直線部(36)に対して接続された第2直線部(37)とを含み、
前記第1側縁部(46)は、前記第1直線部(36)および前記第2直線部(37)のうち前記第1直線部(36)に選択的に形成されている、付記3-1~付記3-3のいずれか一項に記載の半導体装置(1)。
[付記3-5]
前記第1導電部材(25)の前記先端部(39)は、平面視において第1曲率半径(R1)を有する第1円弧(51)で形成された第1側面(52)を有し、
前記第1導電部材(25)の前記第1側縁部(46)は、平面視において前記第1曲率半径(R1)よりも小さい第2曲率半径(R2)を有する第2円弧(53)で形成された第2側面(54)を有している、付記3-4に記載の半導体装置。
[付記3-6]
前記第1導電部材(25)は、断面視において、第1ベース層(26)と、前記第1ベース層(26)の端面(29)よりも側方に突出するように前記第1ベース層(26)に積層された第1被覆層(27)とを含み、
前記第1側縁部(46)は、前記第1被覆層(27)に選択的に形成されている、付記3-1~付記3-5のいずれか一項に記載の半導体装置(1)。
[付記3-7]
前記樹脂層(55)は、前記第1直線部(36)の前記ベース部(40)をパッド(14)として露出させるパッド開口(56)を有している、付記3-2に記載の半導体装置(1)。
[付記3-8]
前記樹脂層(55)内において、前記第1直線部(36)の前記ベース部(40)に接続された第2導電部材(59)をさらに含む、付記3-2に記載の半導体装置(1)。
[付記3-9]
前記第2導電部材(59)は、前記半導体基板(4,15)の主面(11)に沿って延びる第3直線部(72)を有し、
前記第3直線部(72)は、平面視において、前記第3直線部(72)の長手方向に交差する方向の一方側および他方側に交互に曲がる曲線(80)で形成された第2側縁部(79)を含む、付記3-8に記載の半導体装置(1)。
[付記3-10]
前記第2導電部材(59)は、断面視において、第2ベース層(60)と、前記第2ベース層(60)の端面(63)よりも側方に突出するように前記第2ベース層(60)に積層された第2被覆層(61)とを含み、
前記第2側縁部(79)は、前記第2被覆層(61)に選択的に形成されている、付記3-8または付記3-9に記載の半導体装置(1)。
[付記3-11]
前記第1導電部材(25)と前記半導体基板(4,15)との間に形成され、少なくとも第1無機系絶縁層(18,57)および前記第1無機系絶縁層(18,57)上に積層された第2無機系絶縁層(19,58)を含む絶縁層積層構造(17)を含む、付記3-1~付記3-10のいずれか一項に記載の半導体装置(1)。
[付記3-12]
前記半導体基板(4,15)に形成され、前記第1導電部材(25)に電気的に接続された集積回路素子(16)を含む、付記3-1~付記3-11のいずれか一項に記載の半導体装置(1)。
2 :封止樹脂
3 :ダイパッド
4 :半導体チップ
5 :導電接合材
6 :リード端子
7 :導線
8 :第1主面
9 :第2主面
10A :第1側面
10B :第2側面
10C :第3側面
10D :第4側面
11 :第1主面
12 :第2主面
13 :素子領域
13A :ダイオード領域
13B :トランジスタ領域
13C :抵抗素子領域
14 :パッド
15 :半導体基板
16 :機能素子
17 :絶縁層積層構造
18 :第1絶縁層
19 :第2絶縁層
20 :第3絶縁層
21 :第4絶縁層
22 :第5絶縁層
23 :配線
24 :ビア
25 :第1導電部材
26 :第1ベース層
27 :第1被覆層
28 :第1被覆部
29 :端面
30 :第1突出部
31 :端面
32 :第1段差
33 :上面
34 :第1層
35 :第2層
36 :第1直線部
37 :第2直線部
38 :コーナ部
39 :先端部
40 :第1ベース部
41 :第1側部
42 :第1境界部
43 :第1境界部
44 :第1凸部
45 :第1凹部
46 :第1側縁部
47 :正弦曲線
47A :正弦曲線
47B :正弦曲線
48 :第1湾曲凸部
49 :第1湾曲凹部
50 :第1基準線
51 :第1円弧
52 :第1側面
53 :第2円弧
54 :第2側面
55 :保護層
56 :パッド開口
57 :第1絶縁層
58 :第2絶縁層
59 :第2導電部材
60 :第2ベース層
61 :第2被覆層
62 :第2被覆部
63 :端面
64 :第2突出部
65 :端面
66 :第2段差
67 :上面
68 :第1層
69 :第2層
70 :接続部
71 :屈曲部
72 :第3直線部
73 :先端部
74 :第2ベース部
75 :第2側部
76 :第2境界部
77 :第2凸部
78 :第2凹部
79 :第2側縁部
80 :正弦曲線
80A :正弦曲線
80B :正弦曲線
81 :第2湾曲凸部
82 :第2湾曲凹部
83 :第2基準線
84 :第3円弧
85 :第3側面
86 :第4円弧
87 :第4側面
88 :側縁部
89 :配線
90 :側縁部
91 :配線
A1 :振幅
A2 :振幅
P1 :突出量
P2 :突出量
R1 :第1曲率半径
R2 :第2曲率半径
R3 :第3曲率半径
R4 :第4曲率半径
W1 :幅
W2 :第1幅
W3 :幅
W4 :第2幅
X1 :第1方向
X2 :第3方向
Y1 :第2方向
Y2 :第4方向
Claims (12)
- 半導体基板と、
前記半導体基板上に形成され、前記半導体基板の主面に沿って延びる第1直線部を有する第1導電部材と、
前記半導体基板上に形成され、前記第1導電部材を被覆する有機系絶縁層とを含み、
前記第1直線部は、平面視において、前記第1直線部の長手方向に交差する方向の一方側および他方側に交互に曲がる曲線で形成された第1側縁部を含む、半導体装置。 - 前記第1直線部は、接合部材が接続され得るベース部と、前記ベース部から前記第1直線部の長手方向に交差する方向に突出する凸部および前記凸部に対して窪んだ凹部を含む第1側部とを含み、
前記第1側縁部は、平面視において、前記凸部および前記凹部を前記第1直線部の長手方向に沿って連続して繋ぐ曲線によって形成されている、請求項1に記載の半導体装置。 - 前記ベース部は、第1幅を有する帯状に形成されており、
前記ベース部の前記第1幅は、前記ベース部からの前記凸部の突出量の10倍以上である、請求項2に記載の半導体装置。 - 前記第1導電部材は、前記第1直線部の一部を含む先端部と、コーナ部を介して前記第1直線部に対して接続された第2直線部とを含み、
前記第1側縁部は、前記第1直線部および前記第2直線部のうち前記第1直線部に選択的に形成されている、請求項1~3のいずれか一項に記載の半導体装置。 - 前記第1導電部材の前記先端部は、平面視において第1曲率半径を有する第1円弧で形成された第1側面を有し、
前記第1導電部材の前記第1側縁部は、平面視において前記第1曲率半径よりも小さい第2曲率半径を有する第2円弧で形成された第2側面を有している、請求項4に記載の半導体装置。 - 前記第1導電部材は、断面視において、第1ベース層と、前記第1ベース層の端面よりも側方に突出するように前記第1ベース層に積層された第1被覆層とを含み、
前記第1側縁部は、前記第1被覆層に選択的に形成されている、請求項1~5のいずれか一項に記載の半導体装置。 - 前記有機系絶縁層は、前記第1直線部の前記ベース部をパッドとして露出させるパッド開口を有している、請求項2に記載の半導体装置。
- 前記有機系絶縁層内において、前記第1直線部の前記ベース部に接続された第2導電部材をさらに含む、請求項2に記載の半導体装置。
- 前記第2導電部材は、前記半導体基板の主面に沿って延びる第3直線部を有し、
前記第3直線部は、平面視において、前記第3直線部の長手方向に交差する方向の一方側および他方側に交互に曲がる曲線で形成された第2側縁部を含む、請求項8に記載の半導体装置。 - 前記第2導電部材は、断面視において、第2ベース層と、前記第2ベース層の端面よりも側方に突出するように前記第2ベース層に積層された第2被覆層とを含み、
前記第2側縁部は、前記第2被覆層に選択的に形成されている、請求項8または9に記載の半導体装置。 - 前記第1導電部材と前記半導体基板との間に形成され、少なくとも第1無機系絶縁層および前記第1無機系絶縁層上に積層された第2無機系絶縁層を含む絶縁層積層構造を含む、請求項1~10のいずれか一項に記載の半導体装置。
- 前記半導体基板に形成され、前記第1導電部材に電気的に接続された集積回路素子を含む、請求項1~11のいずれか一項に記載の半導体装置。
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JPH05315323A (ja) * | 1992-05-13 | 1993-11-26 | Hitachi Cable Ltd | 半導体基板の配線パターン及びその形成方法 |
JP2004134594A (ja) * | 2002-10-10 | 2004-04-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2016009745A (ja) * | 2014-06-24 | 2016-01-18 | 富士通株式会社 | 電子部品、電子部品の製造方法及び電子装置 |
JP2019083250A (ja) * | 2017-10-30 | 2019-05-30 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
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JPH05315323A (ja) * | 1992-05-13 | 1993-11-26 | Hitachi Cable Ltd | 半導体基板の配線パターン及びその形成方法 |
JP2004134594A (ja) * | 2002-10-10 | 2004-04-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2016009745A (ja) * | 2014-06-24 | 2016-01-18 | 富士通株式会社 | 電子部品、電子部品の製造方法及び電子装置 |
JP2019083250A (ja) * | 2017-10-30 | 2019-05-30 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
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