JP2010283053A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2010283053A
JP2010283053A JP2009133940A JP2009133940A JP2010283053A JP 2010283053 A JP2010283053 A JP 2010283053A JP 2009133940 A JP2009133940 A JP 2009133940A JP 2009133940 A JP2009133940 A JP 2009133940A JP 2010283053 A JP2010283053 A JP 2010283053A
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Prior art keywords
semiconductor device
wires
electrode
electrode terminal
conductive adhesive
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JP2009133940A
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English (en)
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Kenichi Ishii
研一 石井
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2009133940A priority Critical patent/JP2010283053A/ja
Priority to US12/662,332 priority patent/US20100308457A1/en
Publication of JP2010283053A publication Critical patent/JP2010283053A/ja
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Abstract

【課題】第１の電極端子と第２の電極端子間の配線におけるオン抵抗を低減する、半導体装置及び半導体装置の製造方法を提供する。
【解決手段】半導体装置１００は、第１の電極端子と、第２の電極端子と、前記第１及び第２の電極端子を接続する少なくとも２本のワイヤー１４とを有する。少なくとも２本のワイヤー１４は、ワイヤー１４が延びる方向に沿って導電性接着剤１５を用いて互いに電気的に接続されている。第１の電極端子は、例えば外部引き出し電極２０の端子である。また、第２の電極端子は、例えばＭＯＳＦＥＴのソース電極２２の端子である。
【選択図】図１

Description

本発明は、半導体装置及びその製造方法に関する。
近年、低消費電力社会の実現のために、半導体装置の低消費電力化や高効率化に関する技術が注目を集めている。特に、パワーエレクトロニクス分野で使用されるパワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等では、消費電力を低減する技術の一つとしてオン抵抗を低くする手法がある。
一般に、パワーＭＯＳＦＥＴをはじめとする半導体装置のパワー素子の接続には、線径が１００μｍから５００μｍであるアルミニウム(Ａｌ)ワイヤーが使用されている。図６は背景技術にかかる半導体装置内部の実装例を示す平面図である。図６に示すように、半導体装置はリードフレーム４１と、半導体チップ４２と、ワイヤー４３及び４４と、封止樹脂４５と、ソース電極４６と、外部引き出し電極４７と、を有する。そして、図６に示す半導体装置では、複数本のワイヤー４３を用いてソース電極４６と外部引き出し電極４７とを接続することで、配線におけるオン抵抗を低減している。よって、ソース電極４６と外部引き出し電極４７との間に大電流が流れた場合でも、発熱や電力ロスを抑えることができる。
また、図７は背景技術にかかる半導体装置内部の別の実装例を示す平面図である。図７に示すように、半導体装置はリードフレーム５１と、半導体チップ５２と、薄板５３と、ワイヤー５４と、封止樹脂５５と、接合部５６と、ソース電極５７と、外部引き出し電極５８とを有する。そして、ワイヤーに代わり薄板５３を用いて、半導体チップ５２のソース電極５７と外部引き出し電極５８を接続することで、配線におけるオン抵抗を数ｍΩまで低減している。よって、ソース電極５７と外部引き出し電極５８との間に大電流が流れた場合の発熱や電力ロスを抑えることができる。
配線におけるオン抵抗の低減は、適用された機器の冷却や低消費電力化に貢献するものである。なお、本特性は素子そのものの性能や、素子と外部回路とのインターフェースの役割を持つパッケージに大きく影響される。
特許文献１には、外部との電気的接続を行う電極端子と半導体チップを電気的に接続する配線の少なくとも一部に、網状金属細線を用いる、電力半導体モジュールに関する技術が開示されている。網状金属細線は金属細線と比較して表面積が大きく放熱効率が高いため、半導体チップを効率的に冷やすことができる。
特許文献２には、両端を電極に接続している複数のワイヤーの中間部を、共通のリードに接続するワイヤーボンディング構造に関する技術が開示されている。
特開２００１−０３６００１号公報 特開２００７−３１７７１８号公報
しかしながら、図６に示したように複数のワイヤー４３を用いる場合、ワイヤー４３同士の間隔を狭めるのにも限界があるため、使用できるワイヤー４３の本数は限られる。また、ワイヤー４３の線径を大きくした場合、大きなＵＳ（Ultra Sonic）パワーや圧力等を用いて半導体チップ４２とワイヤー４３をボンディングしなければならないため、半導体チップ４２の破壊リスクが高くなり、品質の安定維持が困難となる。
また、図７に示したように薄板５３を用いる場合、半導体チップ５２の両面を熱膨張係数の異なる材料で広範囲に接合することとなる。よって、接合部５６に熱応力が過度にかかることとなり、半導体チップ５２の破壊リスクが高くなる。
特許文献１に開示された技術では、半導体チップと網状金属細線のボンディングにおいて、半導体チップと金属細線のボンディングに比べて大きなパワーが必要であり、半導体チップの破壊リスクが高くなる。また、網状金属細線を別途用意する必要があることから、コストが増加するという問題がある。
特許文献２に開示された技術は、配線におけるオン抵抗の低減を図るものではない。また、複数のボンディングワイヤーを共通リードに押しつけるように変形して接着することから、共通リードのエリア面積が増大するとともにボンディングワイヤーの変形工程が必要となり、コストが増加するという問題がある。
本発明にかかる半導体装置は、第１の電極端子と、第２の電極端子と、前記第１及び第２の電極端子を接続する少なくとも２本のワイヤーとを有し、前記少なくとも２本のワイヤーは、当該少なくとも２本のワイヤーが延びる方向に沿って、導電性接着剤を用いて互いに電気的に接続されている。
本発明によれば、少なくとも２本のワイヤーを、少なくとも２本のワイヤーが延びる方向に沿って導電性接着剤を用いて互いに電気的に接続することで、第１の電極端子と第２の電極端子間の配線におけるオン抵抗を低減することができる。
本発明によれば、配線におけるオン抵抗を低減することにより、半導体装置の低消費電力化や高効率化を実現することができる。
発明の実施の形態１にかかる半導体装置を示す図である。（ａ）は半導体装置の平面図であり、（ｂ）は（ａ）の半導体装置のＡ−Ａにおける断面図である。 発明の実施の形態１にかかる半導体装置の製造工程を示すフローチャートである。 発明の実施の形態２にかかる半導体装置を示す図である。（ａ）は半導体装置の平面図であり、（ｂ）は（ａ）の半導体装置のＢ−Ｂにおける断面図である。 発明の実施の形態３にかかる半導体装置の平面図である。 発明の実施の形態４にかかるパワーモジュールの平面図である。 背景技術にかかる半導体装置内部の実装例を示す平面図である。 背景技術にかかる半導体装置内部の別の実装例を示す平面図である。
実施の形態１．
最初に、実施の形態１にかかる半導体装置１００の構成を図１を用いて説明する。図１（ａ）は半導体装置１００を上面から見たときの平面図であり、図１（ｂ）は半導体装置１００のＡ−Ａにおける断面図である。当該半導体装置１００を構成する各要素及び半導体装置１００の製造方法については後に詳細に説明する。
実施の形態１にかかる半導体装置１００は、リードフレーム１１と、半導体チップ１２と、ワイヤー１３及び１４と、導電性接着剤１５と、封止樹脂１６を有する。
リードフレーム１１はアイランド１７を有し、アイランド１７は半導体チップ１２のドレイン電極２３に接合している。また、リードフレーム１１は外部引き出し電極２０を有している。ここで、リードフレーム１１は、半導体パッケージの内部配線として使われる薄板状の金属であり、外部の配線との橋渡しの役目を果たしている。
半導体チップ１２は、ゲート電極２１及びソース電極２２を有している。半導体チップ１２は、典型的にはＭＯＳＦＥＴであるが、バイポーラトランジスタやダイオード、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、炭化珪素（シリコンカーバイド：ＳｉＣ）デバイス、窒化ガリウム（ガリウムナイトライド：ＧａＮ）デバイス、通常のＩＣ（Integrated Circuit）とすることもできる。
ワイヤー１３は、ゲート電極２１と外部引き出し電極２０間を電気的に接続している。なお、ゲート電極２１には大電流を流す必要がないため、１本のワイヤー１３による構成としている。
ワイヤー１４は、典型的には線径が１００μｍ未満の細線である。図１（ａ）に示すように、ソース電極２２と各ワイヤー１４はそれぞれ接続部１８において電気的に接続されている。また、外部引き出し電極２０と各ワイヤー１４はそれぞれ接続部１９において電気的に接続されている。このようにして、ワイヤー１４は、ソース電極２２と外部引き出し電極２０を電気的に接続している。ここで、ソース電極２２と外部引き出し電極２０を接続する複数のワイヤー１４は、少なくとも２本備えていればよく、ワイヤー１４の本数が増えるほどソース電極２２と外部引き出し電極２０の間の抵抗は低減する。
また、図１（ａ）に示すように、ソース電極２２の接続部１８、及び外部引き出し電極２０の接続部１９はそれぞれ、２段の千鳥配置としてもよいし、各接続部１８、１９の間隔を狭くすることができるのであれば、１段としてもよい。また、図１（ａ）に示すように、複数のワイヤー１４は互いに略平行となるように配置されている。
導電性接着剤１５は、少なくとも２本のワイヤー１４に対し、少なくとも２本のワイヤー１４が延びる方向に沿って塗布され、ワイヤー１４同士を互いに電気的に接続する。これにより、ソース電極２２と外部引き出し電極２０間の配線におけるオン抵抗を低減することができる。また、導電性接着剤１５に代わり金属製ペーストを用いても良く、導電性接着剤１５や金属製ペーストは少なくとも２本のワイヤー１４に絡みつく適度な粘度やチクソ性を有するのが望ましい。また、導電性接着剤１５に代わり、金属製シートや半田を用いることもできる。
封止樹脂１６は、半導体チップ１２等を光や熱、湿度等から保護するために塗布され、半導体装置１００をパッケージする。
次に、半導体装置１００の製造方法を、図２のフローチャートを用いて説明する。
初めに、リードフレーム１１を準備する（ステップＳ１）。次に、リードフレーム１１にマウント剤を塗布し（ステップＳ２）、リードフレーム１１のアイランド１７に半導体チップ１２のドレイン電極２３が接合するように、半導体チップ１２をマウントする（ステップＳ３）。
次に、ワイヤー１３の両端を外部引き出し電極２０とゲート電極２１にボンディングする。また、複数のワイヤー１４の両端を、外部引き出し電極２０とソース電極２２にボンディングする（ステップＳ４）。
次に、導電性接着剤１５を複数のワイヤー１４が延びる方向に沿って塗布し、複数のワイヤー１４同士を互いに電気的に接続する（ステップＳ５）。なお、導電性接着剤１５に代わり金属製シートを用いる場合には、金属製シートをワイヤー１４に載せて加熱すること等により金属製シートとワイヤー１４を接着し、複数のワイヤー１４同士を電気的に接続する。
次に、塗布した導電性接着剤１５に硬化剤等を加え、キュアを行う（ステップＳ６）。
次に、半導体装置１００に封止樹脂１６を塗布し、封止を行う（ステップＳ７）。次に、塗布した封止樹脂１６に硬化剤等を加え、キュアを行う（ステップＳ８）。
次に、半導体装置１００の外部リードを成型する（ステップＳ９）。
最後に、半導体装置１００に外装めっきを行い（ステップＳ１０）、完成した半導体装置１００の選別を行う（ステップＳ１１）。
以上で説明したように、本実施の形態にかかる半導体装置では、複数のワイヤーを導電性接着剤を用いて互いに電気的に接続しているので、半導体チップの電極と外部引き出し電極とを接続する配線におけるオン抵抗を低減することができる。
また、上述の半導体装置によれば、ワイヤー１４に細線を用いているので適度なＵＳパワーでソース電極２２とワイヤー１４を接合することができる。よって、半導体チップ１２に過度の負荷を与えること無く、配線におけるオン抵抗の低減を図ることができる。
また、ワイヤー１４は柔軟性を損なわないため応力に強く、また、材料間の熱膨張係数差による信頼性低下も防止することができる。さらに、ワイヤー１４の変形工程が必要ないことから、低コスト化を図ることができる。
実施の形態２．
実施の形態２にかかる半導体装置２００の構成を図３を用いて説明する。図３（ａ）は半導体装置２００を上面から見たときの平面図であり、図３（ｂ）は半導体装置２００のＢ−Ｂにおける断面図である。本実施の形態にかかる半導体装置２００の構成はワイヤー１４の配置以外、実施の形態１にかかる半導体装置１００の構成と同様であるので、重複する部分については説明を省略する。
実施の形態２にかかる半導体装置２００では、複数のワイヤー１４は互いに略平行に配置されている。また、図３（ａ）に示すように、ソース電極２２とワイヤー１４の接続部１８、及び外部引き出し電極２０とワイヤー１４の接続部１９はそれぞれ、ｍ（ｍは２以上の整数）、ｎ（ｎは２以上の整数）列に配置されている。各接続部１８、１９をこのような配置とすることで、複数のワイヤー１４の間隔が狭くなり、導電性接着剤１５の接着性を向上することができる。図３に示した半導体装置２００は、ワイヤー１４同士が、３段で互いに略平行となるように配置されている例である。
導電性接着剤１５は、少なくとも２本のワイヤー１４に対し、少なくとも２本のワイヤー１４が延びる方向に沿って塗布され、ワイヤー１４同士を互いに電気的に接続する。これにより、ソース電極２２と外部引き出し電極２０間の配線におけるオン抵抗を低減することができる。導電性接着剤１５に代わり金属製ペーストを用いても良く、導電性接着剤１５や金属製ペーストは少なくとも２本のワイヤー１４に絡みつく適度な粘度やチクソ性を有するのが望ましい。また、導電性接着剤１５に代わり、金属製シートや半田を用いることができる。
以上で説明したように、本実施の形態にかかる半導体装置では、複数のワイヤーを導電性接着剤を用いて互いに電気的に接続しているので、半導体チップの電極と外部引き出し電極とを接続する配線におけるオン抵抗を低減することができる。
特に、本実施の形態にかかる半導体装置では、ワイヤー同士の間隔を狭くすることができるので、塗布する導電性接着剤１５の適用範囲を広げることができる。
実施の形態３．
実施の形態３にかかる半導体装置３００の構成を図４を用いて説明する。本実施の形態にかかる半導体装置３００の構成は、ワイヤー１４の配置以外は、実施の形態１にかかる半導体装置１００の構成と同様であり、重複する部分については説明を省略する。
実施の形態３にかかる半導体装置３００では、複数のワイヤー１４の一部の間隔を特に狭くするため、複数のワイヤー１４が互いに交差するように、またはねじれの位置となるように配線する。このとき、互いに交差するワイヤー１４は、互いに接しているものとする。また、ねじれの位置に配置されたワイヤー１４は、互いに接していないものとする。図４に示した半導体装置３００は、ワイヤー１４の各２本が交差するよう配線した例である。
導電性接着剤１５は、少なくとも２本のワイヤー１４に対し、少なくとも２本のワイヤー１４が延びる方向に沿って塗布され、ワイヤー１４同士を互いに電気的に接続する。これにより、ソース電極２２と外部引き出し電極２０間の配線におけるオン抵抗を低減することができる。導電性接着剤１５に代わり金属製ペーストを用いても良く、導電性接着剤１５や金属製ペーストは少なくとも２本のワイヤー１４に絡みつく適度な粘度やチクソ性を有するのが望ましい。また、導電性接着剤１５に代わり、金属製シートや半田を用いることができる。
以上で説明したように、本実施の形態にかかる半導体装置では、複数のワイヤーを導電性接着剤を用いて互いに電気的に接続しているので、半導体チップの電極と外部引き出し電極とを接続する配線におけるオン抵抗を低減することができる。
特に、本実施の形態にかかる半導体装置では、ワイヤー同士の間隔を狭くすることができるので、塗布する導電性接着剤１５の適用範囲を広げることができる。
実施の形態４．
実施の形態４にかかるパワーモジュール４００の構成を図５を用いて説明する。
実施の形態４にかかるパワーモジュール４００は、主にＩＧＢＴ等のパワー素子に適用されているものであり、ベース３１と、セラミック基板２４と、半導体チップ２５と、ワイヤー２６と、導電性接着剤２７と、外部引き出し電極２８を有する。
ベース３１は、典型的には冷却板であり、素材として銅やアルミニウムを用いる。
セラミック基板２４は、接着材３２によりベース３１に接着されている。また、セラミック基板２４は電気回路を有しており、セラミック基板２４上に複数の半導体チップ２５がマウントされている。なお、セラミック基板２４は、他の絶縁基板とすることができる。
半導体チップ２５は、ゲート電極２９及びソース電極３０を有している。
ワイヤー２６は、電気回路の電極端子３３とゲート電極２９間や、電気回路の電極端子３３とソース電極３０間や、電気回路の電極端子３３と外部引き出し電極２８間を、電気的に接続している。
導電性接着剤２７は、互いに略平行となるように配線されている少なくとも２本以上のワイヤー２６に対して、ワイヤー２６が延びる方向に沿って塗布され、ワイヤー２６同士を電気的に接続する。これにより、外部引き出し電極２８と電気回路の電極端子３３間や、電気回路の電極端子３３とソース電極３０間の配線におけるオン抵抗を低減することができる。導電性接着剤２７に代わり金属製ペーストを用いても良く、導電性接着剤２７や金属製ペーストは少なくとも２本のワイヤー２６に絡みつく適度な粘度やチクソ性を有するのが望ましい。また、導電性接着剤２７に代わり、金属製シートや半田を用いることができる。
外部引き出し電極２８は、ワイヤー２６により電気回路の電極端子と電気的に接続している。また、外部引き出し電極２８は、パワーモジュール４００より外部に存在する電極（図示せず）と電気的に接続している。
以上で説明したように、本実施の形態にかかるパワーモジュールでは、複数のワイヤーを導電性接着剤を用いて互いに電気的に接続しているので、外部引き出し電極と電気回路の電極端子や、電気回路の電極端子とソース電極とを接続する配線におけるオン抵抗を低減することができる。
なお、本発明は上記実施の形態に限られたものではなく、本発明の趣旨を逸脱しない範囲で適宜変更することが可能である。
１１、４１、５１ リードフレーム
１２、２５、４２、５２ 半導体チップ
１３、１４、２６、４３、４４、５４ ワイヤー
１５、２７ 導電性接着剤
１６、４５、５５ 封止樹脂
１７ アイランド
１８、１９ 接続部
２０、２８、４７、５８ 外部引き出し電極
２１、２９ ゲート電極
２２、３０、４６、５７ ソース電極
２３ ドレイン電極
２４ セラミック基板
３１ ベース
３２ 接着剤
３３ 電気回路の電極端子
５３ 薄板
５６ 接合部
１００、２００、３００ 半導体装置
４００ パワーモジュール

Claims (14)

  1. 第１の電極端子と、
    第２の電極端子と、
    前記第１及び第２の電極端子を接続する少なくとも２本のワイヤーと、を有し、
    前記少なくとも２本のワイヤーは、当該少なくとも２本のワイヤーが延びる方向に沿って、導電性接着剤を用いて互いに電気的に接続されている、
    半導体装置。
  2. 前記導電性接着剤は粘度及びチクソ性を有する、
    請求項１に記載の半導体装置。
  3. 前記導電性接着剤は金属製ペーストである、
    請求項１又は請求項２に記載の半導体装置。
  4. 前記導電性接着剤は金属製シートである、
    請求項１に記載の半導体装置。
  5. 前記導電性接着剤は半田である、
    請求項１に記載の半導体装置。
  6. 前記少なくとも２本のワイヤーが略平行に配線されている、
    請求項１から請求項５までのいずれかに記載の半導体装置。
  7. 前記少なくとも２本のワイヤーが交差するように配線されている、
    請求項１から請求項５までのいずれかに記載の半導体装置。
  8. 前記少なくとも２本のワイヤーがねじれの位置関係にあるように配線されている、
    請求項１から請求項５までのいずれかに記載の半導体装置。
  9. 前記第１の電極端子は外部引き出し電極の端子であり、前記第２の電極端子はソース電極の端子である、
    請求項１から請求項８までのいずれかに記載の半導体装置。
  10. 前記第１の電極端子は外部引き出し電極の端子であり、前記第２の電極端子は電気回路の電極端子である、
    請求項１から請求項８までのいずれかに記載の半導体装置。
  11. 前記第１の電極端子はソース電極の端子であり、前記第２の電極端子は電気回路の電極端子である、
    請求項１から請求項８までのいずれかに記載の半導体装置。
  12. 前記第１の電極端子は、ＭＯＳＦＥＴ、バイポーラトランジスタ、ダイオード、ＩＢＧＴ、ＳｉＣ及びＧａＮを用いて形成されたＭＯＳＦＥＴ、のいずれかの電極端子である、
    請求項１から請求項８までのいずれかに記載の半導体装置。
  13. 第１の電極端子と、第２の電極端子とを、少なくとも２本のワイヤーを用いて接続し、
    前記少なくとも２本のワイヤーを、当該少なくとも２本のワイヤーが延びる方向に沿って、導電性接着剤を用いて互いに電気的に接続する、
    半導体装置の製造方法。
  14. 前記導電性接着剤をさらに硬化させる
    請求項１３の半導体装置の製造方法。
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