CN104851843A - 电力用半导体装置 - Google Patents

电力用半导体装置 Download PDF

Info

Publication number
CN104851843A
CN104851843A CN201510085084.8A CN201510085084A CN104851843A CN 104851843 A CN104851843 A CN 104851843A CN 201510085084 A CN201510085084 A CN 201510085084A CN 104851843 A CN104851843 A CN 104851843A
Authority
CN
China
Prior art keywords
power semiconductor
copper
circuit pattern
pad plate
insulation board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510085084.8A
Other languages
English (en)
Inventor
山口义弘
柳本辰则
石桥秀俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN104851843A publication Critical patent/CN104851843A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/049Wire bonding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

本发明提供一种能够提高电气接合可靠性的电力用半导体装置。安装电力用半导体元件(8)的电路基板具有绝缘板(5A)、接合图案(4A)、电路图案(6A)以及焊盘板(1C)。绝缘板(5A)由氮化铝陶瓷制作,具有第1面以及第2面(S1、S2)。接合图案(4A)接合在绝缘板(5A)的第1面(S1)上,由铝或铝合金制作。电路图案(6A)接合在绝缘板(5A)的第2面(S2)上,由铝或铝合金制作。焊盘板(1C)与电路图案(6A)接合,仅局部地覆盖电路图案(6A),由铜或铜合金制作。

Description

电力用半导体装置
技术领域
本发明涉及一种电力用半导体装置,特别地,涉及一种具有安装有电力用半导体元件的电路基板的电力用半导体装置。
背景技术
设置在电力模块内的、例如IGBT(Insulated Gate BipolarTransistor)以及二极管等电力用半导体元件,在使用中产生大量的热量。因此,安装电力用半导体元件的电路基板需要承受因热循环下的温度变化而引起的应力。另外,为了从电力用半导体元件中有效地去除热量,对于作为电路基板的母材的陶瓷,要求较高的导热性。作为代表性的陶瓷材料存在氮化铝以及氮化硅。
氮化铝陶瓷具有较高的导热性,但作为材料的机械强度不一定较高。因此,需要用于缓和上述应力的构造。
氮化硅陶瓷具有较高的机械强度,所以适于承受上述应力。氮化硅陶瓷的导热性与氮化铝陶瓷相比较差,但近年在不断地进行改善。
作为与电路基板相关的现有技术,例如,存在以下2种技术。
根据日本特开2003-78086号公报(专利文献1),在作为绝缘层的陶瓷板的表面上,顺序地层叠形成有铝或铝合金的层、以及铜或铜合金的层。作为与铜或铜合金相比较软的材料的铝或铝合金的层,缓和向陶瓷板施加的热应力。
根据日本特开2008-147307号公报(专利文献2),在氮化硅陶瓷板上设置有铜或铜合金的电路基板。
专利文献1:日本特开2003-78086号公报
专利文献2:日本特开2008-147307号公报
根据上述现有技术,向电力用半导体装置的制造中的电路基板上安装部件,是通过将该部件与铜或铜合金接合而进行。但是,根据上述部件的种类,有时不适于与铜或铜合金接合,其结果,电气接合可靠性变得不充分。特别是,在使用与焊料接合相比更适于在高温下使用的超声波接合等直接接合的情况下,如上所述的不适合性容易成为问题。例如,在铝导线通过超声波接合与铜图案接合的情况下,容易因铝和铜的接合界面的氧化膜导致电气接合可靠性变得不充分。该问题在电力用半导体元件的使用温度较高的情况下,需要更加关注。近年,作为电力用半导体元件的材料,碳化硅(SiC)或氮化镓(GaN)等与硅(Si)相比适于高温动作的材料的应用不断地发展,为了不损失其优点,需要特别改善上述电气接合可靠性。
发明内容
本发明就是为了解决上述课题而提出的,其目的在于提供一种能够提高电气接合可靠性的电力用半导体装置。
本发明的一个技术方案的电力用半导体装置,具有电力用半导体元件、以及安装有电力用半导体元件的电路基板。电路基板具有绝缘板、接合图案、电路图案以及焊盘板。绝缘板由氮化铝陶瓷制作,具有第1面和与第1面相反的第2面。接合图案接合在绝缘板的第1面上,由铝以及铝合金中的某一种制作。电路图案接合在绝缘板的第2面上,由铝以及铝合金中的某一种制作。焊盘板与电路图案接合,仅局部地覆盖电路图案,由铜以及铜合金中的某一种制作。
本发明的其他技术方案的电力用半导体装置,具有电力用半导体元件、以及安装有电力用半导体元件的电路基板。电路基板具有绝缘板、接合图案、电路图案以及焊盘板。绝缘板由氮化硅陶瓷制作,具有第1面和与第1面相反的第2面。接合图案接合在绝缘板的第1面上,由铜以及铜合金中的某一种制作。电路图案接合在绝缘板的第2面上,由铜以及铜合金中的某一种制作。焊盘板与电路图案接合,仅局部地覆盖电路图案,由铝以及铝合金中的某一种制作。
发明的效果
根据本发明,能够提高电力用半导体装置的电气接合可靠性。
附图说明
图1是概略地表示作为本发明的实施方式1中的电力用半导体装置的电力模块的结构的图,是沿图2的Ⅰ-Ⅰ线的剖面图。
图2是沿图1的Ⅱ-Ⅱ线的概略剖面图。
图3是表示对比例的电力模块的结构的图,是沿图4的Ⅲ-Ⅲ线的剖面图。
图4是沿图3的Ⅳ-Ⅳ线的剖面图。
图5是概略地表示作为本发明的实施方式2中的电力用半导体装置的电力模块的结构的图,是沿图6的Ⅴ-Ⅴ线的剖面图。
图6是沿图5的Ⅵ-Ⅵ线的概略剖面图。
标号的说明
1A、1C焊盘板,2金属基座板,3焊料层,4A、4C接合图案,5A、5S绝缘板,6A、6C电路图案,7接合材料,8电力用半导体元件,8a开关半导体元件,8b整流半导体元件,9栅极Al导线(导线),10主Al导线(导线),11阳极Cu电极(电极),12阴极Cu电极(电极),13控制Cu电极(电极),14壳体,15填充部,16栅极电阻,91、92电力模块(电力用半导体装置),S1下表面(第1面),S2上表面(第2面)。
具体实施方式
下面,基于附图对本发明的实施方式进行说明。在附图中对同一或相同的部分标注同一参照标号,不重复进行其说明。
实施方式1.
参照图1以及图2,电力模块91(电力用半导体装置)具有电路基板以及安装在该电路基板上的电力用半导体元件8。
具体地说,电力用半导体元件8具有如IGBT(Insulated GateBipolar Transistor)那样的开关半导体元件8a以及如电力用二极管那样的整流半导体元件8b。电路基板具有绝缘板5A、接合图案4A、电路图案6A以及焊盘板1C。
绝缘板5A由氮化铝陶瓷制作。绝缘板5A具有下表面S1(第1面)和上表面S2(与第1面相反的第2面)。
接合图案4A接合在绝缘板5A的下表面S1上。接合图案4A由铝或铝合金制作。电路图案6A接合在绝缘板5A的上表面S2上。电路图案6A由铝或铝合金制作。接合图案4A以及电路图案6A与绝缘板5A的接合,能够通过铝直接接合(DBA:Direct BondedAluminum)或活性金属钎焊(AMB:Active Metal Brazing)进行。
焊盘板1C由铜或铜合金制作。焊盘板1C与电路图案6A接合。该接合能够通过在真空中对绝缘板5A以及焊盘板1C高温加压而实现的固相扩散接合进行。焊盘板1C仅局部地覆盖电路图案6A。焊盘板1C与后述的电极不同,不向壳体14外凸出,而是收容在壳体14内。优选焊盘板1C具有平坦的板状形状。
在焊盘板1C上接合有电力用半导体元件8,在本实施方式中,在1个焊盘板1C上接合有多个电力用半导体元件8。优选电力用半导体元件8各自的接合是通过使用含有银的接合材料7的接合而进行的。
此外,在预先准备的电路基板上进行电力用半导体元件8的安装。即,在用于电路基板制造的接合工序完成后,安装电力用半导体元件8。因此可以认为,上述的通过高温加压实现的固相扩散接合等接合工序的条件不会对电力用半导体元件8及其可能附带的导线等产生影响,能够以较大的自由度进行选择。另外,在该接合中彼此接合的部件通常是容易接合的板状部件。另外,各自的接合面积比较大。因此,该接合虽然是铝或铝合金与铜或铜合金之间的异种接合,但还是比较容易确保接合可靠性。
电力模块91具有直接接合在焊盘板1C上的、由铜或铜合金中的某一种制作的电极。优选这些电极通过超声波接合而接合在焊盘板1C上。具体地说,电力模块91具有阳极Cu电极11、阴极Cu电极12以及控制Cu电极13。这些电极是从壳体14的内部延伸至外部的电极,即外部电极。
电力模块91具有栅极Al导线9以及主Al导线10,它们作为由铝以及铝合金制作的导线。栅极Al导线9以及主Al导线10各自的一端与电力用半导体元件8接合。另外,栅极Al导线9以及主Al导线10各自的另一端与电路图案6A直接接合,优选通过固相扩散接合进行接合,例如通过超声波接合进行接合。
电力模块91也可以具有与电路图案6A连接的、栅极电阻16等无源部件。栅极电阻16例如可以通过焊料层3进行接合。
电力模块91具有金属基座板2、壳体14以及填充部15。此外,为了使图容易观察,图中省略了填充部15的形状。金属基座板2通过与接合图案4A接合而安装在电路基板上。该接合例如也可以通过焊料层3而进行。壳体14在金属基座板2上对安装有电力用半导体元件8的电路基板进行收容。壳体14的安装能够使用螺钉或硅橡胶进行。填充部15由填充在壳体14内的绝缘体构成,在电路基板上,对电力用半导体元件8进行封装。填充部15的材料例如是硅胶。
参照图3及图4,对比例的电力模块99分别取代上述的接合图案4A、绝缘板5A和电路图案6A,而具有接合图案4C、绝缘板5S和电路图案6C。接合图案4C以及电路图案6C由铜或铜合金制作。绝缘板5S由氮化硅陶瓷制作。
在本对比例中,与电路图案6C电连接的部件,即电力用半导体元件8、栅极Al导线9、主Al导线10、阳极Cu电极11、阴极Cu电极12以及控制Cu电极13,分别与由铜或铜合金构成的电路图案6C连接。即,作为与电路图案6C的电连接,仅使用与铜或铜合金的连接。例如,由铝或铝合金制作的导线通过超声波接合与由铜或铜合金制作的电路图案6C接合。即,导线的连接作为不同种类的材料间的接合而进行,即,作为Al/Cu接合而进行。在其接合界面容易形成氧化膜,其结果,电气接合可靠性容易变得不充分。
对此,根据本实施方式(图1以及图2),电路图案6A由铝或铝合金制作,且焊盘板1C由铜或铜合金制作。由此,作为与电路图案6A的电连接,能够选择与由铝或铝合金制作的电路图案6A接合、以及与由铜或铜合金制作的焊盘板1C接合。由此,能够根据与电路基板电连接的部件的种类,选择可靠性更高的接合方法。因此,能够提高电气接合可靠性。其结果,使电力模块91的耐久性提高。即,电力模块91能够在更长期间内使用。
如上所述,能够选择与铝或铝合金的接合、以及与铜或铜合金的接合这一点,在直接接合中特别重要,例如在超声波接合中是很有益的。
阳极Cu电极11、阴极Cu电极12以及控制Cu电极13直接接合在由铜或铜合金制作的焊盘板1C上。如上所述,通过将电极的连接作为同种材料间的接合而进行,从而提高电气接合可靠性。
由铝或铝合金制作的栅极Al导线9以及主Al导线10,与由铝或铝合金制作的电路图案6A直接接合。由此,能够将导线的连接作为同种材料间的接合而进行。因此,提高电气接合可靠性。另外,与使用金等高价的材料的情况相比,通过使用铝或铝合金,能够降低材料成本。
用于将电力用半导体元件8与焊盘板1C接合的接合材料7含有银。由此,提高导热性,所以能够更有效地去除来自电力用半导体元件8的热量。因此,进一步提高电力模块91对于热循环的耐久性。
另外,由于对于由铜或铜合金制作的焊盘板1C使用含有银的接合材料7,所以能够容易地进行接合。此外,难以将含有银的接合材料7直接对由铝或铝合金制作的电路图案6A使用而进行接合,即使在电路图案6A上实施镀铬,该难度也不会明显改变。
通过作为绝缘板5A的材料而使用导热率较高的氮化铝陶瓷,从而提高散热效率。因此,能够将设置在电力模块91中的金属基座板2或外部散热器(未图示)等散热系统缩小。
实施方式2.
参照图5以及图6,本实施方式的电力模块92(电力用半导体装置)具有电路基板以及安装在该电路基板上的电力用半导体元件8。电路基板具有绝缘板5S、接合图案4C、电路图案6C以及焊盘板1A。
绝缘板5S由氮化硅陶瓷制作。绝缘板5S具有下表面S1(第1面)和上表面S2(与第1面相反的第2面)
接合图案4C接合在绝缘板5S的下表面S1上。接合图案4C由铜或铜合金制作。电路图案6C接合在绝缘板5S的上表面S2上。电路图案6C由铜或铜合金制作。接合图案4C以及电路图案6C与绝缘板5S的接合,能够通过铜直接接合(DBC:Direct Bonded Copper)或AMB进行。
焊盘板1A与电路图案6C接合。该接合能够通过在真空中对电路图案6C以及焊盘板1A高温加压而实现的固相扩散接合进行。焊盘板1A仅局部地覆盖电路图案6C。焊盘板1A由铝或铝合金制作。
电力模块92具有直接接合在电路图案6C上的、由铜或铜合金中的某一种制作的电极。优选这些电极通过超声波接合而接合在电路图案6C上。具体地说,电力模块92具有阳极Cu电极11、阴极Cu电极12以及控制Cu电极13。这些电极是从壳体14的内部延伸至外部的电极,即外部电极。
电力模块92具有栅极Al导线9以及主Al导线10,它们作为由铝或铝合金制作的导线。栅极Al导线9以及主Al导线10各自的一端与电力用半导体元件8接合。另外,栅极Al导线9以及主Al导线10各自的另一端与焊盘板1A直接接合,优选通过固相扩散接合进行接合,例如通过超声波接合进行接合。
此外,对于除了上述以外的结构,由于与上述的实施方式1的结构大致相同,因此对于相同或对应的要素,标注相同的标号,不重复进行其说明。
根据本实施方式,电路图案6C由铜或铜合金制作,且焊盘板1A由铝或铝合金制作。由此,作为与电路图案6C的电连接,能够选择与由铜或铜合金制作的电路图案6C接合、以及与由铝或铝合金制作的焊盘板1A接合。由此,与实施方式1相同地,能够根据与电路基板电连接的材料的种类,选择可靠性更高的接合方法。因此,能够提高电气接合可靠性。其结果,提高电力模块92的耐久性。即,电力模块92能够在更长期间内使用。
如上所述,能够选择与铝或铝合金接合、以及与铜或铜合金接合这一点,在直接接合中特别重要,例如在超声波接合中是很有益的。
由铝或铝合金制作的导线,与由铝或铝合金制作的焊盘板1A直接接合。由此,能够将导线的连接作为同种材料间的接合而进行。因此,提高电气接合可靠性。此外,在本实施方式中,在栅极Al导线9的接合中也使用焊盘板1A,但不一定需要对全部导线都使用焊盘板。例如,也可以对作为电力模块92的主电流路径的主Al导线10,设置焊盘板1A,另一方面,对作为控制信号路径的栅极Al导线9,省略焊盘板1A。
通过由氮化硅陶瓷制作绝缘板5S,从而能够以更小的厚度确保所需的机械强度。因此,能够使电力模块92缩小。
在上述各实施方式中,作为电力用半导体元件8的半导体材料,例如,可以使用Si,也可以使用如SiC或GaN那样的宽带隙半导体。宽带隙半导体适于在高温下使用,在利用该优点时,确保如上所述的电力用半导体元件8的电气接合可靠性是特别重要的。
此外,本发明在其发明的范围内,能够自由地组合各实施方式,或适当地对各实施方式进行变形、省略。

Claims (6)

1.一种电力用半导体装置,其具有:
电力用半导体元件;以及
电路基板,其安装有所述电力用半导体元件,
所述电路基板包含:
绝缘板,其由氮化铝陶瓷制作,具有第1面和与所述第1面相反的第2面;
接合图案,其接合在所述绝缘板的所述第1面上,由铝以及铝合金中的某一种制作;
电路图案,其接合在所述绝缘板的所述第2面上,由铝以及铝合金中的某一种制作;以及
焊盘板,其与所述电路图案接合,仅局部地覆盖所述电路图案,由铜以及铜合金中的某一种制作。
2.根据权利要求1所述的电力用半导体装置,
还具有电极,该电极直接接合在所述焊盘板上,由铜以及铜合金中的某一种制作。
3.根据权利要求1或2所述的电力用半导体装置,
所述电力用半导体元件使用含有银的接合材料与所述焊盘板接合。
4.根据权利要求1或2所述的电力用半导体装置,
还具有导线,该导线与所述电路图案直接接合,由铝以及铝合金中的某一种制作。
5.一种电力用半导体装置,其具有:
电力用半导体元件;以及
电路基板,其安装有所述电力用半导体元件,
所述电路基板包含:
绝缘板,其由氮化硅陶瓷制作,具有第1面和与所述第1面相反的第2面;
接合图案,其接合在所述绝缘板的所述第1面上,由铜以及铜合金中的某一种制作;
电路图案,其接合在所述绝缘板的所述第2面上,由铜以及铜合金中的某一种制作;以及
焊盘板,其与所述电路图案接合,仅局部地覆盖所述电路图案,由铝以及铝合金中的某一种制作。
6.根据权利要求5所述的电力用半导体装置,
还具有导线,该导线与所述焊盘板直接接合,由铝以及铝合金中的某一种制作。
CN201510085084.8A 2014-02-17 2015-02-16 电力用半导体装置 Pending CN104851843A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014027200A JP6192561B2 (ja) 2014-02-17 2014-02-17 電力用半導体装置
JP2014-027200 2014-02-17

Publications (1)

Publication Number Publication Date
CN104851843A true CN104851843A (zh) 2015-08-19

Family

ID=53759122

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510085084.8A Pending CN104851843A (zh) 2014-02-17 2015-02-16 电力用半导体装置

Country Status (4)

Country Link
US (1) US20150237718A1 (zh)
JP (1) JP6192561B2 (zh)
CN (1) CN104851843A (zh)
DE (1) DE102015201182A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110313220A (zh) * 2016-12-09 2019-10-08 恩德莱斯和豪瑟尔欧洲两合公司 电子模块

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109564918B (zh) * 2016-08-10 2023-09-29 三菱电机株式会社 半导体装置
JP2019054069A (ja) * 2017-09-14 2019-04-04 株式会社東芝 半導体装置
DE102018212272A1 (de) * 2018-07-24 2020-01-30 Robert Bosch Gmbh Keramischer Schaltungsträger und Elektronikeinheit
JP7279324B2 (ja) * 2018-09-14 2023-05-23 富士電機株式会社 半導体モジュール

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1828881A (zh) * 2005-02-28 2006-09-06 株式会社日立制作所 电子装置
CN101401197A (zh) * 2006-03-08 2009-04-01 株式会社东芝 电子元器件模块
CN101587870A (zh) * 2008-05-23 2009-11-25 富士电机电子技术株式会社 半导体器件
CN102054830A (zh) * 2009-09-30 2011-05-11 英飞凌科技股份有限公司 功率半导体模块和驱动功率半导体模块的方法
US20120134115A1 (en) * 2009-07-02 2012-05-31 Curamik Electronics Gmbh Electronic device
US20130009298A1 (en) * 2011-07-04 2013-01-10 Mitsubishi Electric Corporation Semiconductor module
CN103247545A (zh) * 2012-02-08 2013-08-14 英飞凌科技股份有限公司 半导体装置及其方法
JP2013214561A (ja) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板、冷却器付パワーモジュール用基板及びパワーモジュール

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691125B2 (ja) * 1985-11-20 1994-11-14 古河電気工業株式会社 半導体装置
JPS63296250A (ja) * 1987-05-27 1988-12-02 Mitsubishi Electric Corp 半導体装置
JPH0831546B2 (ja) * 1987-07-22 1996-03-27 電気化学工業株式会社 ハイパワ−用回路基板及びその混成集積回路
DE69233801D1 (de) * 1991-07-24 2011-02-17 Denki Kagaku Kogyo Kk Verfahren zur Herstellung eines Schaltungssubstrates mit einem montierten Halbleiterelement
JP2884872B2 (ja) * 1991-12-17 1999-04-19 三菱マテリアル株式会社 半導体装置の実装構造
JPH07231015A (ja) * 1994-02-17 1995-08-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2003078086A (ja) * 2001-09-04 2003-03-14 Kubota Corp 半導体素子モジュール基板の積層構造
JP2006114641A (ja) * 2004-10-14 2006-04-27 Mitsubishi Electric Corp 半導体装置
JP2008147307A (ja) 2006-12-07 2008-06-26 Hitachi Metals Ltd 回路基板およびこれを用いた半導体モジュール
JP2010199251A (ja) * 2009-02-25 2010-09-09 Hitachi Ltd 半導体装置の製造方法
US8603862B2 (en) * 2010-05-14 2013-12-10 International Business Machines Corporation Precise-aligned lock-and-key bonding structures
JP5373713B2 (ja) * 2010-07-23 2013-12-18 三菱電機株式会社 半導体装置
US8957508B2 (en) * 2011-05-13 2015-02-17 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing the same
JP5403129B2 (ja) * 2012-03-30 2014-01-29 三菱マテリアル株式会社 パワーモジュール用基板、ヒートシンク付パワーモジュール用基板、パワーモジュール、及びパワーモジュール用基板の製造方法
US9087833B2 (en) * 2012-11-30 2015-07-21 Samsung Electronics Co., Ltd. Power semiconductor devices
JP6230238B2 (ja) * 2013-02-06 2017-11-15 三菱電機株式会社 半導体装置及びその製造方法
JP2014187264A (ja) * 2013-03-25 2014-10-02 Toshiba Corp 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1828881A (zh) * 2005-02-28 2006-09-06 株式会社日立制作所 电子装置
CN101401197A (zh) * 2006-03-08 2009-04-01 株式会社东芝 电子元器件模块
CN101587870A (zh) * 2008-05-23 2009-11-25 富士电机电子技术株式会社 半导体器件
US20120134115A1 (en) * 2009-07-02 2012-05-31 Curamik Electronics Gmbh Electronic device
CN102054830A (zh) * 2009-09-30 2011-05-11 英飞凌科技股份有限公司 功率半导体模块和驱动功率半导体模块的方法
US20130009298A1 (en) * 2011-07-04 2013-01-10 Mitsubishi Electric Corporation Semiconductor module
CN103247545A (zh) * 2012-02-08 2013-08-14 英飞凌科技股份有限公司 半导体装置及其方法
JP2013214561A (ja) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板、冷却器付パワーモジュール用基板及びパワーモジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110313220A (zh) * 2016-12-09 2019-10-08 恩德莱斯和豪瑟尔欧洲两合公司 电子模块

Also Published As

Publication number Publication date
DE102015201182A1 (de) 2015-08-20
JP6192561B2 (ja) 2017-09-06
US20150237718A1 (en) 2015-08-20
JP2015153922A (ja) 2015-08-24

Similar Documents

Publication Publication Date Title
CN109216313B (zh) 具有包括钎焊的导电层的芯片载体的模制封装
US9171773B2 (en) Semiconductor device
US7149088B2 (en) Half-bridge power module with insert molded heatsinks
JP4569473B2 (ja) 樹脂封止型パワー半導体モジュール
US20130270688A1 (en) Power module
US20150116945A1 (en) Semiconductor device and method for manufacturing same
US10763244B2 (en) Power module having power device connected between heat sink and drive unit
CN104851843A (zh) 电力用半导体装置
JP5895220B2 (ja) 半導体装置の製造方法
JP2009536458A (ja) 半導体モジュール及びその製造方法
US20100308457A1 (en) Semiconductor apparatus and manufacturing method of the same
JP2016018866A (ja) パワーモジュール
KR20040007234A (ko) 전력 반도체장치
CN105051898A (zh) 半导体装置
JP2015126168A (ja) パワーモジュール
JP2010538483A (ja) 基板プレート、殊にdcbセラミック基板プレートを用いる電子的な構成素子の製造方法および接触接続方法
JP2017034152A (ja) 電力用半導体装置
WO2020136810A1 (ja) 半導体装置、半導体装置の製造方法及び電力変換装置
JP4096741B2 (ja) 半導体装置
EP3958305A1 (en) Power semiconductor module arrangement and method for producing the same
EP3410481A1 (en) Power semiconductor chip module
JP2015023226A (ja) ワイドギャップ半導体装置
JP2007150342A (ja) 半導体装置およびその製造方法
JP2011526422A (ja) 高温で使用するためのプレーナ型電力電子構成素子およびその製造方法
JP4961314B2 (ja) パワー半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned

Effective date of abandoning: 20180713

AD01 Patent right deemed abandoned