CN102054830A - 功率半导体模块和驱动功率半导体模块的方法 - Google Patents

功率半导体模块和驱动功率半导体模块的方法 Download PDF

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CN102054830A
CN102054830A CN2010105021881A CN201010502188A CN102054830A CN 102054830 A CN102054830 A CN 102054830A CN 2010105021881 A CN2010105021881 A CN 2010105021881A CN 201010502188 A CN201010502188 A CN 201010502188A CN 102054830 A CN102054830 A CN 102054830A
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power semiconductor
semiconductor chip
layer
ceramic substrate
metallization
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CN102054830B (zh
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R·拜尔勒
T·斯托尔策
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Abstract

本发明涉及功率半导体模块和驱动功率半导体模块的方法。功率半导体模块包括壳体、至少一个陶瓷衬底、布置在壳体中的第一功率半导体芯片以及第二功率半导体芯片，第一功率半导体芯片是整流器电路的组成部分并且具有带有上部和下部芯片金属化部的第一半导体本体，第二功率半导体芯片是逆变器电路的组成部分并且具有带有上部和下部芯片金属化部的第二半导体本体。与第一功率半导体芯片的上部和/或下部芯片金属化部分别紧邻有第一连接装置。与第二功率半导体芯片的上部和/或下部芯片金属化部分别紧邻有第二连接装置。在方法中，第一功率半导体芯片在阻挡层温度小于150℃的情况下运行，第二功率半导体芯片在阻挡层温度大于150℃的情况下运行。

Description

功率半导体模块和驱动功率半导体模块的方法 
技术领域
本发明涉及功率半导体模块。这样的模块通常包含两个或者更多个功率半导体芯片，例如包含二极管、晶闸管、IGBT、MOSFET、JFET等等。在功率半导体模块之内可以包含不同的这种功率半导体芯片。 
背景技术
目前可用的功率半导体芯片包括范围广泛的不同芯片工艺。在过去，现代的快速切换的功率半导体芯片的进一步发展已导致越来越高的允许的阻挡层温度以及由此导致越来越高的工作温度。由此需要将利用其将功率半导体芯片与功率半导体模块的其它部件相连接的传统连接技术通过改进的经受更高温度的连接技术来代替。当在切换运行时采用相关的功率半导体芯片并且由此遭受强的温度变化负载时，这种情况越来越多地适用。然而，这种改进的连接技术通常要求特定的、昂贵的芯片金属化部，例如具有铜或者贵金属的芯片金属化部。此外，也需要对模块的与这种特定的芯片金属化部(例如其上安装有功率半导体芯片的陶瓷衬底的金属化部)相连的部件或者对功率半导体芯片利用其相连的接合线提出提高的要求，这通常提高成本。 
在现代的功率半导体芯片的芯片金属化部方面的最新发展产生铜金属化部，而传统的功率半导体芯片的芯片金属化主要由铝制成。相对于铝，铜具有导电性高大约50％的优点。此外，铜特别良好地适于制造耐高温的扩散焊接连接(Diffusionloetverbindung)。然而，铜一方面是昂贵的，另一方面易于被氧化。但是，为了制造扩散焊接连接，需要至少一个裸的铜表面，即铜必须在扩散焊接之前例如被清除氧化层，或者裸的铜表面还必须在扩散焊接之前的时期(例如当相关的部件要安置较长的时间时)中被保护免受氧化。然而，所有这些措施是费事的且昂贵的。 
除了扩散焊接连接之外，低温压力烧结连接也具有高的耐热性和高的温度变化耐受性。在这种情况下，包含银粉和溶剂的糊(Paste) 被引入到彼此要连接的配合件(Fuegepartner)之间。接着，配合件在高压下在预先给定的温度的情况下相对彼此挤压预先给定的时间。由此，形成了耐高温的且抗温度变化(temperaturwechselstabil)的连接。除了该制造工艺本身是费事的且昂贵的之外，配合件的彼此要连接的表面必须被涂有贵金属(例如银或者金)，这同样提高了成本。 
另一基本上公知的连接技术是线接合。在这种情况下，接合线例如被接合到可自由到达的上部芯片金属化部上。对此通常采用的接合线主要由铝制成。然而，在高温差的情况下的负载变化运行时，铝的机械特性以及随之而来的接合连接的强度随着时间的推移而恶化。由此，在较长的运行之后也可发生接合线从芯片金属化部脱落(“liftoff”)。与此不同地，铜在负载变化运行时具有显著更好的特性，因此日益增加地采用基于铜的接合线。然而，高价值的、抗温度变化的线接合连接要求芯片金属化部的硬度和接合线的硬度不能相差过大。因此，从技术角度来看有利的是，在现代的功率半导体芯片中采用由铜构成的上部芯片金属化部，当然这是昂贵的。 
在制造目前的功率半导体模块时，出于制造技术的原因而采用了统一的电或机械连接技术，这意味着：功率半导体模块的所有功率半导体芯片的彼此相对应的接线端子以同样的连接技术被集成到模块结构中。对此的原因在于：出于方法经济的原因，对于在制造功率半导体模块时的所有可比较的子步骤采用了同样的连接技术。 
例如，模块的所有功率半导体芯片的下侧金属化部可以借助传统的熔融焊接连接(Schmelzlotverbindung)例如被焊接到被金属化的陶瓷衬底上，而上侧金属化部分别借助铝接合线连接被电连接。然而，如果现代的快速切换的功率半导体芯片利用这些连接技术被内装(verbauen)在功率半导体模块中，则存在高的概率，使得功率半导体模块故障的原因在于传统的连接技术，因为现代的功率半导体芯片与传统的功率半导体芯片相比大多在更大的温度偏移(Temperaturhub)的情况下运行。 
替换于传统的连接技术，自然可以以模块统一的方式在模块的彼此相对应的部位上采用耐高温的连接技术(也就是即扩散焊接、低温压力烧结、粘合、铜线接合)。但是这意味着：半导体芯片的不遭受高温或强的温度变化负载的金属化部只为了采用现代的连接技术而必 须具有带有铜和/或带有贵金属的金属化部。由此，通过提高的制造成本来换取利用现代连接技术制造的功率半导体模块的更高的可靠性。 
发明内容
本发明的任务在于提供一种功率半导体模块，其中具有基于铝的芯片金属化部的功率半导体芯片和具有基于铜的芯片金属化部的功率半导体芯片可以被混合采用并且仍然可以成本低廉地被制造。另一任务在于，提供一种用于驱动这种功率半导体模块的方法。这些任务通过根据权利要求1所述的功率半导体模块以及通过根据权利要求26所述的用于驱动功率半导体模块的方法来解决。本发明的扩展方案和改进方案是从属权利要求的主题。 
本发明基于如下认知： 
a)在高温时和在高的温度变化负载的情况下在切换运行时采用的快速切换的功率半导体芯片的使用寿命高度地与所采用的利用其内装功率半导体芯片的连接技术/多个连接技术的质量有关，因此在快速切换的功率半导体芯片中，基于铜的芯片金属化部是有利的。 
b)在极少切换的功率半导体芯片(与快速切换的功率半导体芯片相比，所述极少切换的功率半导体芯片在低温或小的温度变化负载的情况下例如在整流器运行时被采用)中，使用寿命基本上受芯片内部的结构制约并且不受所选的连接技术/多个连接技术显著影响，因此在缓慢切换的功率半导体芯片的情况下，基于铝的芯片金属化部就足够了。 
在包括整流器电路和逆变器电路的变频器中采用的功率半导体模块具有壳体、至少一个陶瓷衬底以及第一功率半导体芯片和第二功率半导体芯片。第一功率半导体芯片是整流器电路的组成部分，并且具有带有上部芯片金属化部和下部芯片金属化部的第一半导体本体。第二功率半导体芯片是逆变器电路的组成部分并且包括带有上部芯片金属化部和带有下部芯片金属化部的第二半导体本体。第一功率半导体芯片和第二功率半导体芯片被布置在壳体中。 
与第一功率半导体芯片的上部芯片金属化部和/或下部芯片金属化部分别紧邻有如下连接装置之一：熔融焊接层、铝比例为铝的重量百分比为至少99或者至少99.9的基于铝的接合线。与第二功率半导 体芯片的上部芯片金属化部和/或下部芯片金属化部分别紧邻如下连接装置之一：扩散焊接层、含银的烧结层、粘合层、铜比例为重量百分比为至少99或者至少99.9或者具有铜的基于铜的接合线。 
在用于驱动功率半导体模块的方法中，第一功率半导体芯片在最大阻挡层温度小于150℃的情况下运行，而第二功率半导体芯片在最大阻挡层温度大于150℃的情况下运行。 
在本说明书中，在传统的连接技术和耐高温的连接技术之间进行区分。倘若这些技术的单个技术不是无需解释的，则在下文对其更为详细地阐述。 
在本发明的意义上，熔融焊接或者利用基于铝的接合线进行接合被视为传统的连接技术。 
在熔融焊接时，现有的软焊料(例如基于锡的焊料)被引入到两个彼此要连接的配合件之间，被熔化并且被冷却，使得形成将配合件彼此连接的简单的熔融焊接层。不同于扩散焊接层，熔融焊接层必要时具有低比例(也就是重量百分比小于大约20)的金属间相。在本申请的意义下，对象(例如接合线、金属化部或者金属片)在其具有铝的重量百分比为至少99或者至少99.9的比例时被称为“基于铝的”。 
扩散焊接、低温压力烧结或者粘合被视为在本发明的意义下用于制造耐高温的连接的连接技术，或者利用基于铜的接合线进行接合也被视为在本发明的意义下用于制造耐高温的连接的连接技术。在本申请的意义下，对象(例如接合线、金属化部或者金属片)在其具有铜的重量百分比为至少99或者至少99.9的比例时被称为“基于铜的”。在粘合的情况下，可以使用电绝缘的或者导电的粘合剂。 
扩散焊接基于：在焊接期间，彼此要连接的配合件的材料扩散到液态焊料中并且与焊料组成部分一起构造金属间相，所述金属间相具有高于所使用的焊料的熔点的熔点。比例为金属间相的重量百分比为至少70的焊接层被视为在本发明的意义下的扩散焊接层。这种金属间相例如可以包含金属间的铜-锡相(例如Cu3Sn或者Cu3Sn5)。为了制造其，两个彼此要连接的配合件必须在其彼此要连接的表面上能够提供铜，也就是在每个配合件中(在焊接过程之前)最上面的层在设置的接合部位的区域中具有铜或者由铜制成。包含锡的焊料可以被用作焊料。可选地，焊料可以在焊接过程之前也掺入由一个或多个金属间 相构成的粒子。为了获得稳定的扩散焊接层，有利的是，金属间相(不同于在传统的熔融焊接连接的情况下)至少逐区段地连贯地在彼此要连接的焊接配对的表面之间延伸。 
在低温压力烧结的情况下，制造压力烧结层，其方式是具有银粉和溶剂的糊被引入到要连接的配合件之间并且在压力(例如30MPa)下在范围从大约150℃到250℃的温度的情况下将配合件相对于彼此挤压。为了构造以这种方式制造的含银的烧结连接层，有利的是，配合件在其要相互连接的表面上完全地或者至少主要由贵金属(例如银或者金)制成。这种含银的烧结连接层具有重量百分比为至少99或者至少99.9的银比例。含银的烧结连接层在此可以具有孔总体积比例为例如烧结连接层的大约50体积百分比的高孔隙率。 
附图说明
以下借助实施例参照所附的附图示例性地阐述了本发明。其中： 
图1示出了通过无底板的功率半导体模块的垂直截面，该无底板的功率半导体模块具有两个功率半导体芯片，这两个功率半导体芯片被布置在不同的陶瓷衬底上并且其中一个具有基于铝的芯片金属化部而另一个具有基于铜的芯片金属化部； 
图2示出了通过功率半导体模块的垂直截面，该功率半导体模块具有两个功率半导体芯片，这两个功率半导体芯片被布置在不同的安装在功率半导体模块的底板上的陶瓷衬底上并且其中一个具有基于铝的芯片金属化部而另一个具有基于铜的芯片金属化部； 
图3示出了通过功率半导体模块的垂直截面，该功率半导体模块具有整流器电路和逆变器电路，其中整流器电路的功率半导体芯片在空间上被分组为第一组而逆变器电路的功率半导体芯片在空间上被分组为第二组，并且各个组被布置在底板的已热解耦的段上； 
图4A示出了如在根据图1至3的功率半导体模块中可被采用的传统的功率半导体芯片的放大的图示，其中上部和下部金属化部分别具有多个部分层； 
图4B示出了如在根据图1至3的功率半导体模块中可被采用的传统的功率半导体芯片的放大的图示，其中上部金属化部具有基于铝的部分层，该基于铝的部分层直接接触基于铝的接合线； 
图5A示出了如在根据图1至3的功率半导体模块中可被采用的现代的功率半导体芯片的放大的图示，其中上部和下部金属化部分别具有多个部分层； 
图5B示出了如在根据图1至3的功率半导体模块中可被采用的现代的功率半导体芯片的放大的图示，其中上部金属化部具有基于铜的部分层，该基于铜的部分层直接接触基于铜的接合线； 
图6示出了功率半导体模块的一体式构造的底板的俯视图，该底板具有两个与接片连接的段； 
图7示出了功率半导体模块的具有两个彼此相间隔的段的底板的俯视图； 
图8示出了陶瓷衬底的俯视图，其中在所有情况下整流器电路的所有功率半导体芯片在空间上分组为第一组而逆变器电路的所有功率半导体芯片在空间上分组为第二组； 
图9示出了具有功率半导体模块的电路图，该功率半导体模块包含用于整流器电路的功率半导体芯片和用于逆变器电路的功率半导体芯片；以及 
图10示出了去掉了壳体的功率半导体模块的透视图。 
所示的附图除非另外提及都不是合乎比例的。在以下具体实施方式部分中所使用的与方向相关的术语(例如如“上”、“下”、“左”、“右”、“前”、“后”、“侧面”、“在...上”、“在...下”等之类的概念)涉及相应的附图。这些术语仅被用于使对附图的理解容易。基本上，所示的元件在空间上可以任意地布置，只要从本说明书中没有其它内容得出。此外，除非明确地另外提及，在不同的附图中，相同的附图标记表示具有相同的或者彼此相对应的功能的相同的或者彼此相对应的元件。 
具体实施方式
图1示出了通过功率半导体模块100的垂直截面。该模块具有带有壳体框65的壳体60以及可选的接片62，该接片62被布置在两个被金属化的陶瓷衬底3和4之间。陶瓷衬底3、4分别具有陶瓷小板30或40，这些陶瓷小板30或40在其上侧上配备有上部金属化部31或41。上部金属化部31或41可以可选地被结构化。此外，陶瓷衬底3、 4在其下侧分别具有可选的、未结构化的下部金属化部32或42。陶瓷衬底3、4基本上可以(彼此无关地和彼此任意组合地)被构造为DCB衬底(DCB＝直接铜接合(direct copper bonding))、被构造为DAB衬底(DAB＝直接铝接合(direct aluminium bonding))或者被构造为AMB衬底(AMB＝活性金属钎焊(active metal brazing))。上部金属化部31或41可以(同样彼此无关地和彼此任意组合地)完全或者至少主要由铜或者铝制成。为了避免衬底3、4的由温度引起的弯曲，陶瓷衬底3或4的下部金属化部32或42和上部金属化部31或41以衬底统一的方式由同样的材料制成。在需要时，陶瓷衬底3及4的上部金属化部31、41可以被结构化成印制导线和/或导体面，以便能够实现内装在功率半导体模块中的电子部件(例如功率半导体芯片)的布线。 
陶瓷衬底3和4在其侧向边缘的区域中被固定在壳体60上，然而这在图1中并未示出。在两个相邻的衬底3、4之间布置的壳体接片62同样用于固定与其相邻的陶瓷衬底3和4。如果功率半导体模块100仅仅具有恰好一个陶瓷衬底，则壳体接片62可以取消。 
在功率半导体模块100的陶瓷衬底3、4的每个上可以根据功率半导体模块的相应的电路要求来布置一个或多个功率半导体芯片1或2。用附图标记“1”表征整流器电路的功率半导体芯片，用附图标记“2”表征逆变器电路的功率半导体芯片。 
基本上，功率半导体模块100可以具有恰好一个或者也可以具有多个分别装备有至少一个功率半导体芯片1、2的陶瓷衬底3、4。 
在陶瓷衬底3的上部金属化部31上布置有传统的功率半导体芯片1，在该功率半导体芯片1的上侧上涂敷上部芯片金属化部11而在该功率半导体芯片1的下侧上涂敷下部芯片金属化部12。上部芯片金属化部11和下部芯片金属化部12分别具有至少一个基于铝的部分层，所述至少一个基于铝的部分层的厚度例如可以为大于1μm或者大于2μm。 
在功率半导体芯片1的半导体本体和这种基于铝的部分层之间可选地还可以设置例如金属的势垒层，该势垒层最大可能地防止铝从该部分层扩散到半导体本体中。在其背离功率半导体本体的那侧上，基于铝的部分层此外还可以配备有可选的其它的金属层，例如以便改善 可焊性或者保护基于铝的部分层的否则裸露的表面免受外部机械和/或化学影响。这种其它的金属层例如可以由如下材料之一制成：Ag、NiPd、NiAu、NiPdAu。可选地，这些材料可以包含合金添加剂。 
半导体芯片1借助传统的连接层15(即借助熔融焊接层)与陶瓷衬底3的上部金属化部31相连接。在被构造为熔融焊接层的连接层15的情况下，下部芯片金属化部12和上部衬底金属化部31的朝向彼此的表面可以在焊接过程之前至少在要用焊料润湿的部位上配备有涂层，该涂层改善了可焊性，即降低了焊接时的热需要量和/或提高了表面的可润湿性。这种涂层例如可以由镍、金或者银制成或者由具有这些金属中的至少一种的合金制成。 
为了在上侧接触功率半导体芯片1设置有基于铝的接合线71，该基于铝的接合线71被接合到功率半导体芯片1的上部芯片金属化部11上。接合线71可以将上部芯片金属化部11与功率半导体模块100的任意其它部件相连。图1中所示的至在陶瓷衬底3的上部衬底金属化部31中构造的印制导线的连接因而应被理解为仅仅是示例性的。 
布置在陶瓷衬底4上的功率半导体芯片2是快速切换的功率半导体芯片，该快速切换的功率半导体芯片包括基于硅或者基于碳化硅的半导体本体20，该半导体本体20在其上侧上配备有上部芯片金属化部21而在其下侧上配备有下部芯片金属化部22。上部芯片金属化部21和下部芯片金属化部22分别具有至少一个基于铜的部分层，该基于铜的部分层的厚度例如可以为大于1μm或者大于2μm。 
在功率半导体芯片2的半导体本体和这种基于铜的部分层之间可选地还可以设置有例如金属的势垒层，该势垒层最大可能地防止了铜从该部分层扩散到半导体本体中。此外，基于铜的部分层在其背离功率半导体本体的那侧上还可以配备有可选的其它金属层，例如以便保护基于铜的部分层的否则裸露的表面免受外部机械和/或化学影响。这种其它的金属层例如可以由如下合金之一制成：Ag、NiPd、NiAu、NiPdAu。可选地，这些合金可以含有其它合金添加剂。 
为了将功率半导体芯片2牢固地与陶瓷衬底4连接，设置有连接层16，该连接层16将下部芯片金属化部22与陶瓷衬底4的上部金属化部41相连接。连接层16可以被构造为扩散焊接层、被构造为粘合层或者被构造为含银的烧结层。 
在被构造为扩散焊接层的连接层16的情况下，下部芯片金属化部22和上部衬底金属化部41的彼此要连接的表面完全地或者至少主要由铜制成。为了制造扩散焊接连接，使用了基于锡的焊料。完成了的扩散焊接层以重量百分比为至少70由一种或多种金属间的铜-锡相制成，例如由Cu3Sn或者Cu3Sn5制成。 
在被构造为含银的烧结层的连接层16的情况下，功率半导体芯片2的下部金属化部22和陶瓷衬底4的上部金属化部41在烧结之前至少在其彼此要连接的表面的区域中配备有贵金属构成的涂层，该贵金属例如是银或者金或者是具有这些金属中的至少一种的合金。 
为了也在上侧电连接功率半导体芯片2，设置有基于铜的接合线72，该基于铜的接合线72被接合到上部芯片金属化部21上。上部芯片金属化部21可以利用接合线72被连接到功率半导体模块100的任意其它的电部件上。图1中所示的与上部衬底金属化部41的被构造为印制导线的区段的连接因而应被理解为仅仅是示例性的。 
功率半导体模块100的功率半导体芯片1、2例如可以是变频器电路的组成部分，该变频器电路整个或者部分地被实现成功率半导体模块100。变频器电路尤其是包含整流器电路和逆变器电路。功率半导体芯片2是逆变器电路的组成部分并且以快速时钟控制的方式在切换交替运行时被采用。功率半导体芯片2因此遭受高温和强的温度变化负载。功率半导体芯片1是整流器电路的组成部分。与功率半导体芯片2相比，功率半导体芯片1遭受较小的最高温度并且受到较低的温度变化负载。 
在根据图1的例子中，在陶瓷衬底3上布置有一个或多个传统的半导体芯片1，然而没有布置耐高温的功率半导体芯片2。由此，功率半导体模块的布置在陶瓷衬底3上的电路部分在比布置在陶瓷衬底4上的电路部分更低的温度的情况下运行，使得可以采用传统的连接技术，也就是采用由熔融焊料构成的连接层15或具有基于铝的接合线71的接合连接，以便将所述一个或多个半导体芯片1与陶瓷衬底3相连接和/或电接通所述一个或多个功率半导体芯片1。 
基本上，在陶瓷衬底3上也可以内装带有基于铜的芯片金属化部的现代的耐高温的功率半导体芯片，只要这些功率半导体芯片不是在如下的一个或多个连接层15中的温度不允许升高的温度范围中运行： 利用所述一个或多个连接层15将模块100的布置在陶瓷衬底3上的其它传统的功率半导体芯片1与陶瓷衬底3连接。 
在陶瓷衬底4上布置有一个或多个具有基于铜的芯片金属化部21、22的现代的耐高温的功率半导体芯片2，可是没有布置具有基于铝的芯片金属化部的传统的功率半导体芯片。安装在陶瓷衬底4上的现代的功率半导体芯片2中的每个都借助耐高温的连接工艺、即借助被构造为含银的烧结层或者被构造为扩散焊接层的耐高温的连接层16与上部金属化部41连接和/或借助基于铜的接合线72与功率半导体模块100的其它部件电接通。 
为了向外部接通功率半导体模块100，设置有金属的连接片51、52(例如被冲制的和弯曲的铜片)，这些金属的连接片51、52可以从壳体60突出并且其外端部与其它电部件旋紧在一起、压紧在一起、夹紧在一起或者焊接在一起。此外，软浇注材料65(例如硅凝胶)被填充到壳体60中，该软浇注材料65提高了功率半导体模块100的绝缘强度，并且该软浇注材料65至少覆盖功率半导体模块100的所有功率半导体芯片1、2的上侧。 
为了将连接片51、52导电地连接到集成在功率半导体模块100中的电路上，设置有基于铝的接合线或者基于铝的小带73，其将连接片51与陶瓷衬底3的上部衬底金属化部31连接，以及设置有基于铜的接合线或者基于铜的小带74，其将陶瓷衬底4的上部金属化部41与连接片52连接。 
代替借助接合线73或74将连接片51和/或52与相应的上部衬底金属化部31或41连接，也可以直接借助超声焊接将连接片51和/或52的下端部与相应的衬底金属化部31或41连接。 
基于铝的接合线或者小带73也可以被采用在该部位上，因为这些基于铝的接合线或者小带73与接合到现代的功率半导体芯片2上的接合线72相比受到显著更低的温度和温度变化负载。但是，基本上，接合线或者小带73也可以被构造为基于铜的接合线或者小带73。 
图1中所示的功率半导体模块100是所谓的“无底板的”功率半导体模块，因为该功率半导体模块不具有在其上共同地安装功率半导体模块100的陶瓷衬底3、4的底板。因而，所有被内装在功率半导体模块100中的装备有功率半导体芯片1或者2的陶瓷衬底3、4的下侧 3b、4b形成了功率半导体模块100的下侧100b的部分。 
与此相比，图2示出了功率半导体模块100，该功率半导体模块具有底板9，该底板9可以是例如基于铜的。该底板9具有上侧91以及下侧92。在底板9上布置有分别装备的陶瓷衬底3、4，所述陶瓷衬底3、4的下部金属化部32或42借助连接层95或96与底板9的上侧91连接。在被构建为焊接层的连接层95或96的情况下，设置有固定结构(Verankerungsstruktur)。这种固定结构例如可以被构造为金属格栅或者被构造为金属网，其为了焊接而被插入在陶瓷衬底3或4的下部金属化部32或42之间并且被焊接在一起。固定结构的另一例子是多个稍带长形的柱，这些柱在下部衬底金属化部32或42的下侧上基本上垂直于相关的陶瓷小板30或40走向并且是下部衬底金属化部32或42的组成部分。 
为了在功率半导体模块100运行时避免装配有至少一个陶瓷衬底3、4的底板9的由温度引起的过强的挠曲，该底板9可以在被装配有陶瓷衬底3、4之前预弯曲，使得底板9的下侧92尤其是在高的工作温度的情况下尽可能是平的，以便实现尽可能良好地将在功率半导体芯片1、2中出现的损耗热导出至安装在底板9的下侧92上的冷却体(未示出)。 
陶瓷衬底3、4及其装配有功率半导体芯片1、2、接合线71、72以及具有接合线73或74的布线可以以相同的方式、利用相同的材料和利用相同的连接技术来进行，如这在前面在根据图1的功率半导体模块100的情况下已被描述的那样。 
由于布置在陶瓷衬底3上的所有功率半导体芯片1在比较低的温度的情况下(即在小于例如125或者150℃的阻挡层温度的情况下)运行，所以传统的连接技术(即熔融焊接)可被用于将陶瓷衬底3与底板91连接。连接层95因此被构造为熔融焊接层。替换于此地，连接层95也可以被构造为扩散焊接层，被构造为粘合层或者被构造为含银的烧结层。 
布置在陶瓷衬底4上的功率半导体芯片2在比较高的温度的情况下(即在大于125、大于150℃或者大于175℃的阻挡层温度的情况下)运行，因此将陶瓷衬底4的下部金属化部与底板9相连接的连接层96必须是耐高温的并且是抗温度变化的，也就是连接层96被构造 为扩散焊接层、被构造为粘合层或者被构造为含银的烧结层。在功率半导体模块100中，底板9的下侧92至少形成功率半导体模块100的下侧100b的最大部分。 
在本发明的所有可能的扩展方案中，功率半导体模块100的所有装配有功率半导体芯片1、2的陶瓷衬底3、4借助以下连接技术中的同一连接技术与底板9的上侧91相连接：扩散焊接、银压力烧结或者粘合。 
图3中所示的功率半导体模块与根据图2的功率半导体模块的区别在于：图3中所示的功率半导体模块的底板9具有至少两个在热学上尽可能彼此解耦的段9a、9b。热解耦通过在段9a和9b之间的间隙93来实现。间隙93可以连贯地被构造，使得段9a和9b彼此相间隔。替换于此地，段9a和9b也可以通过接片彼此连接。 
图4A示出了传统的功率半导体芯片1的放大的图示，如其例如在根据图1至3的功率半导体模块中例如可以在整流器电路中被采用的那样。 
第一功率半导体芯片1的上部金属化部11具有多个金属的部分层11a、11b和11c，下部金属化部12具有多个金属的部分层12a、12b和12c。 
上部金属化部11的第一部分层11a和下部金属化部12的第一部分层12a分别是基于铝的并且以重量百分比大于99或者甚至以重量百分比大于99.9来由铝制成。其功能主要在于承载第一功率半导体芯片1的高电流。上部金属化部11的第一部分层11a和下部金属化部12的第一部分层12a因此与其它部分层11b和11c或12b和12c相比具有相对高的厚度，例如具有大于1μm或者大于2μm的厚度，例如具有约3μm的厚度。 
上部金属化部11的第二部分层11b和下部金属化部12的第二部分层12b承担了势垒层的功能，目的是显著地减小铝从上部金属化部11的第一部分层11a或从下部金属化部12的第一部分层12a到半导体本体10中的扩散。第二部分层11b和/或12b例如可以由如下材料中的一种或者多种制成或者具有如下材料中的至少一种：TiN、Ta、TaN、TiW、W、合金或者这些层的组合。第二部分层11b和/或12b的厚度例如可以分别为约500nm。 
上部金属化部11的第三部分层11c被布置在上部金属化部11的第一部分层11a的背离半导体本体10的那侧上。相对应地，下部金属化部12的第三部分层12c被布置在下部金属化部12的第一部分层12a的背离半导体本体10的那侧上。第三部分层11c和12c例如可以由如下材料中的一种或多种制成或者具有如下材料中的至少一种：Ag、NiPd、NiAu、NiPdAu。可选地，这些材料可以包含合金添加剂。 
此外，上部金属化部11还可以具有附加的、可选的部分层，所述附加的、可选的部分层被布置在上部金属化部11的第一部分层11a与上部金属化部11的第二部分层11b之间和/或被布置在上部金属化部11的第二部分层11b与半导体本体10之间。相对应地，下部金属化部12可选地还可以具有其它的部分层，这些其它的部分层被布置在下部金属化部12的第一部分层12a与下部金属化部12的第二部分层12b之间和/或被布置在下部金属化部12的第二部分层12b与半导体本体10之间。 
在此，在上部金属化部11的第三部分层11c被布置在接合线71和第一部分层11a之间期间，上部金属化部11的第三部分层11c根据图4B中所示的可替换的扩展方案在制造接合连接期间被接合线71局部损坏，使得接合线71直接接触上部金属化部11的第一部分层11a并且与其构造牢固的接合连接。 
图5示出了现代的功率半导体芯片2的放大的图示，如其例如在根据图1至3的功率半导体模块中例如可以在逆变器电路中被采用的那样。 
第二功率半导体芯片2的上部金属化部21具有多个金属的部分层21a、21b和21c，下部金属化部22具有多个金属的部分层22a和22b。 
上部金属化部21的第一部分层21a和下部金属化部22的第一部分层22a分别是基于铜的并且以重量百分比大于99或者甚至以重量百分比大于99.9来由铜制成。所述上部金属化部21的第一部分层21a和下部金属化部22的第一部分层22a的功能主要在于承载第二功率半导体芯片2的高电流。所述上部金属化部21的第一部分层21a和下部金属化部22的第一部分层22a因此与其它部分层21b和21c或22b相比具有相对高的厚度，具有例如大于1μm或者大于2μm的厚度，具有例如约3μm的厚度。 
上部金属化部21的第二部分层21b和下部金属化部22的第二部分层22b承担势垒层的功能，目的是显著地减小铜从上部金属化部21的第一部分层21a或从下部金属化部22的第一部分层22a到半导体本体20中的扩散。第二部分层21b和22b例如可以由如下材料中的一种或者多种制成或者具有如下材料中的至少一种：TiN、Ta、TaN、TiW、W、合金或者这些层的组合。第二部分层21b和/或22b的厚度例如可以分别为约500nm。 
上部金属化部21的第三部分层21c被布置在上部金属化部21的第一部分层21a的背离半导体本体20的那侧上。第三部分层21c例如可以由如下材料中的一种或多种制成或者具有如下材料中的至少一种：NiPd、NiAu、NiPdAu。可选地，这些材料可以包含合金添加剂。 
此外，上部金属化部21还可以具有附加的、可选的部分层，所述附加的、可选的部分层被布置在上部金属化部21的第一部分层21a与上部金属化部21的第二部分层21b之间和/或被布置在上部金属化部21的第二部分层21b与半导体本体20之间。相对应地，下部金属化部22可选地还可以具有其它的部分层，所述其它的部分层被布置在下部金属化部22的第二部分层22b与半导体本体20之间。 
可选地，下部金属化部22可以在制造第二功率半导体芯片2和陶瓷衬底4之间的焊接连接之前作为第三部分层具有含锡的焊接层，该含锡的焊接层在制造焊接连接之前形成功率半导体芯片2的下表面，并且该含锡的焊接层被直接地或者间接地涂敷到第一部分层22a的背离半导体本体20的那侧上。为了制造在第二功率半导体芯片2和陶瓷衬底4之间的焊接连接，含锡的焊接层被熔化并且被冷却来使得由该含锡的焊接层形成连接层16。在焊接过程期间，铜可以从陶瓷衬底4的上部金属化部41渗入到含锡的焊料中，并且只要含锡的焊料被直接涂敷到第二半导体芯片2的下部金属化部22的第一部分层22a上，铜就可以从下部金属化部22的第一部分层22a渗入到含锡的焊料中，并且与包含在其中的锡一起构造高熔点的金属间的铜-锡相(例如Cu3Sn或Cu3Sn5)。 
在此，在上部金属化部21的第三部分层21c被布置在接合线72和第一部分层21a之间期间，上部金属化部21的第三部分层21c根据图5B中所示的可替换的扩展方案在制造接合连接期间被接合线72局 部损坏，使得接合线72直接接触上部金属化部21的第一部分层21a并且与其构造牢固的接合连接。 
图6示出了具有两个彼此已热解耦的段9a和9b的底板9，这些段9a和9b借助接片94彼此连接。间隙93被构造为一体式的底板9中的稍带长形的槽。虚线示出了底板9的上侧91的其上安装有陶瓷衬底3或4的区段。 
根据图7中所示的可替换的底板9的例子，底板9的段9a、9b也可以彼此相间隔。 
图8示出了陶瓷衬底5的俯视图，在该陶瓷衬底5上布置具有基于铝的芯片金属化部11的传统的功率半导体芯片1以及具有基于铜的芯片金属化部21的现代的功率半导体芯片2。所有传统的功率半导体芯片1都与陶瓷衬底5的上部金属化部51借助以下连接层相连接：该连接层可以如在图1中所阐述的连接层15那样被构造和被制造。在此，不同的传统的功率半导体芯片1也可以利用不同的传统的连接技术与金属化部51相连接。同样，所有布置在陶瓷衬底5上的传统的功率半导体芯片1可以利用同样的传统连接技术与上部金属化部51相连接。 
相对应地，现代的、快速切换的并且在高温的情况下运行的功率半导体芯片2在所有情况下都利用耐高温的连接层(该连接层可以如在图1中所阐述的连接层16那样被构建)与上部金属化部51相连接。在这种情况下，不同的功率半导体芯片2也可以利用不同的耐高温的连接技术与金属化部51相连接。替换于此地，所有被布置在陶瓷衬底5上的功率半导体芯片2利用同样的耐高温的连接技术与金属化部51相连接。 
此外，传统的功率半导体芯片1在其基于铝的上部芯片金属化部11上借助基于铝的接合线71来接通。与此不同地，在高阻挡层温度的情况下运行的现代的功率半导体芯片2在其基于铜的上部芯片金属化部21上借助基于铜的接合线72来接通。 
此外，在逆变器电路W的功率半导体芯片2附近布置无源器件80，譬如布置温度传感器、NTC电阻(NTC＝负温度系数(negativetemperature coefficient))、分流电阻或者电容器。无源器件80同样具有如下金属化部：在所述金属化部上无源器件借助扩散焊接层、粘合层或者银烧结层与陶瓷衬底相连接。这样的无源器件80也可以在 根据图1至3的布局中利用同样的连接技术被布置在一个或多个同样的衬底4上，逆变器电路的功率半导体芯片2也位于所述一个或多个同样的衬底4上。 
为了在根据图8的布局中使传统的功率半导体芯片1、用来将传统的功率半导体芯片1与金属化部51相连接的传统的连接层以及接合线71与在现代的功率半导体芯片2运行时出现的高温解耦，传统的功率半导体芯片1和现代的功率半导体芯片2彼此相间隔地被布置在陶瓷衬底5上。在传统的功率半导体芯片1和现代的功率半导体芯片2之间的最小距离d例如可以被选择为大于5mm或者大于10mm。在此适宜的是，将传统的功率半导体芯片1和现代的功率半导体芯片2组合成分别在空间上分离的组。这些组接着同样彼此具有距离d。 
在根据图8的例子中，传统的功率半导体芯片1是整流器电路G的组成部分，该整流器电路G遭受比较小的温度变化负载。与此相对，现代的功率半导体芯片2是逆变器电路W的组成部分。现代的功率半导体芯片2比传统的功率半导体芯片1遭受显著更高的阻挡层温度和温度变化负载。 
如果陶瓷衬底被采用在无底板的功率半导体模块中，则陶瓷衬底5的背离上部金属化部51的可具有下部金属化部的下侧形成功率半导体模块的下侧的部分。替换于此地，根据参照图8所阐述的原理构建的和装备的陶瓷衬底5也可以被采用在具有底板的功率半导体模块中。对此，陶瓷衬底5利用其在图8中所遮盖的下部金属化部与虚线示出的底板9的上侧91相连。对此所采用的连接层的制造和结构对应于在图2和3中所阐述的连接层96的制造和结构。 
图9示出了具有功率半导体模块100的部分电路图的电路图，该功率半导体模块100包含用于整流器电路G的传统的功率半导体芯片1和用于逆变器电路W的现代的功率半导体芯片2。整个电路图尤其是示出了示例性的三相电网N，利用所述三相电网N，低频交流电流(例如具有25Hz、50Hz或者60Hz的三相电流)被提供并且借助整流器电路G为了提供中间电路电压U1(+)-U1(-)而被整流。整流器电路G针对电网N的每相都包含两个串联连接的整流器件1，所述整流器件1如所示的那样可被构造为二极管或者可替换地被构造为晶闸管。整流器电路G的整流器件1是具有基于铝的芯片金属化部的传统的缓慢切换的功率 半导体芯片。 
通常所需的用于平滑中间电路电压的中间电路电容器并未示出。这种中间电路电容器可以在需要时被布置在功率半导体模块100的壳体的外部或者内部。 
中间电路电压被处理(aufbereiten)用于提供高频时钟控制的、示例性地为三相的输出电压供给U1、U2、U3。高于电网N的频率的时钟频率例如可以为大于500Hz。该频率与逆变器电路的功率半导体芯片2的截止电压等级有关。例如，该频率在3.3kV的允许的截止电压的情况下为500Hz，或者在1.7kV的允许的截止电压的情况下为1kHz，或者在1.2kV的允许的截止电压的情况下为2kHz。输出电压供给用于驱动电负载，例如用于驱动电动机。 
为了处理中间电路电压，针对要提供的输出电压供给U1、U2、U3的每个相都设置有半桥支路，在该半桥支路上分别施加中间电路电压。半桥支路中的每个都包括两个可控的功率半导体开关，例如所示的IGBT或者也可以是MOSFET或者JFET，所述可控的功率半导体开关的负载段串联连接。快速切换的续流二极管与可控的功率半导体开关的负载段的每个都反并联地连接。可控的功率半导体开关和逆变器电路W的续流二极管是具有基于铜的芯片金属化部的现代的快速切换的功率半导体芯片。 
在根据图9中所示的部分电路图的功率半导体模块100中，功率半导体模块100的传统的功率半导体芯片1的所有功率半导体芯片都被布置在第一陶瓷衬底(参见例如图1、2和3中的陶瓷衬底3)上，而所有现代的功率半导体芯片2都被布置在第二陶瓷衬底(参见例如图1、2和3中的陶瓷衬底4)上。通常，功率半导体模块100的传统的功率半导体芯片1的任意子集都可以被布置在第一陶瓷衬底(参见例如图1、2和3中的陶瓷衬底3)上，而功率半导体模块100的现代的功率半导体芯片2的任意子集都可以被布置在第二陶瓷衬底(参见例如图1、2和3中的陶瓷衬底4)上。此外，不同的传统的功率半导体芯片1可以分布式地被布置在两个或者更多个陶瓷衬底上。相对应地同样适用于不同的现代的功率半导体芯片2，即不同的现代的功率半导体芯片2可以分布式地被布置在两个或者更多个陶瓷衬底上。 
电网N的相的数目基本上是任意的。同样适用于输出电压供给U1、 U2、U3的相的数目。整流器电路和逆变器电路G、W构成的单元的子单元也可以分布到分别带有自己的壳体的两个或者功率半导体模块上。这种功率半导体模块的结构可以根据如下原理来实现：该原理参照图1至8进行了阐述，这的前提条件是在相关的模块壳体之内设置有至少一个带有基于铝的芯片金属化部的传统的功率半导体芯片1和至少一个带有基于铜的芯片金属化部的现代的功率半导体芯片2。 
图10示出了功率半导体模块100的透视图。壳体和浇注材料被去除。在共同的底板9上布置多个陶瓷衬底3、4并且与其上侧91牢固地相连。陶瓷衬底3、4在其上侧上具有被结构化的金属化部31或41，以及在其下侧上具有金属化部(在图10中被遮挡)。此外，除了厚的负载电流连接片50、51、52之外还设置有连接片53，所述连接片53用于将控制信号输送给功率半导体模块100或者例如提供功率半导体模块100的状态信号或者任意其它信号。连接片50、51、52、53在任何情况下都用于在壳体之外电接触功率半导体模块100。 
连接片50、51、52、53中的至少单个可以具有弯折的脚部区域50b、51b(被遮挡)、52b(被遮挡)或53b，相关的连接片50、51、52、53利用这些脚部区域牢固地与陶瓷衬底的上部金属化部相连接。作为连接技术，对此合适的是例如熔融焊接、扩散焊接、导电粘合、具有银糊的低温压力烧结或者超声焊接。 
除了陶瓷衬底3和4(其与前面所描述的陶瓷衬底3或4一样被构建、被装配并且与底板9的上侧91相连接)之外还设置有其它的陶瓷衬底6，所述其它的陶瓷衬底6同样具有被结构化的上部金属化部61以及(被遮挡的)下部金属化部，其可以借助熔融焊接层、扩散焊接层、粘合层或者银烧结层与底板9的上侧91相连接。陶瓷衬底6被装备有无源器件80，在此例如被装备有NTC温度感测器。其具有用来将其导电地(例如通过熔融焊接、扩散焊接、导电粘合或者具有银糊的低温压力烧结)与金属化部61相连接的至少一个金属化部。 
利用本发明，可以实现在整流器电路的功率半导体芯片和逆变器电路的功率半导体芯片之间的热解耦，使得在功率半导体模块之内形成从逆变器电路的功率半导体芯片朝向整流器电路的温度梯度。由此，逆变器电路的功率半导体芯片在阻挡层温度(例如在175℃或者在200℃时)的情况下运行，该逆变器电路的功率半导体芯片的阻挡层温度 明显高于整流器电路的功率半导体芯片的阻挡层温度(例如125℃或者150℃)。 

Claims (27)

1.一种用于在变频器中采用的功率半导体模块，该变频器具有整流器电路(G)和逆变器电路(W)，该功率半导体模块包括：
-壳体(60)，
-第一功率半导体芯片(1)，所述第一功率半导体芯片(1)是整流器电路(G)的组成部分，并且所述第一功率半导体芯片(1)具有第一半导体本体(10)，所述第一半导体本体(10)具有上部芯片金属化部(11)和下部芯片金属化部(12)；
-第二功率半导体芯片(2)，所述第二功率半导体芯片(2)是逆变器电路(W)的组成部分，并且所述第二功率半导体芯片(2)具有第二半导体本体(20)，所述第二半导体本体(20)具有上部芯片金属化部(21)和下部芯片金属化部(22)；
-至少一个陶瓷衬底(3，4，5)；
其中，
-所述第一功率半导体芯片(1)和所述第二功率半导体芯片(2)被布置在所述壳体(60)中；
-与所述第一功率半导体芯片(1)的上部芯片金属化部(11)和/或下部芯片金属化部(12)分别紧邻有如下第一连接装置之一：熔融焊接层(15)、铝比例为铝的重量百分比为至少99的基于铝的接合线(71)；
-与所述第二功率半导体芯片(2)的上部芯片金属化部(21)和/或下部芯片金属化部(22)分别紧邻有如下第二连接装置之一：扩散焊接层(16)、含银的烧结层、粘合层、铜比例为铜的重量百分比为至少99的基于铜的接合线(72)。
2.根据权利要求1所述的功率半导体模块，其中，第一功率半导体芯片(1)的下部金属化部(12)具有厚度大于1μm或者大于2μm的至少一个第一部分层(12a)，所述至少一个第一部分层(12a)以重量百分比大于99来由铝制成。
3.根据权利要求1或2所述的功率半导体模块，其中，第一功率半导体芯片(1)的下部金属化部(12)借助熔融焊接层(15)与陶瓷衬底(3，5)的上部金属化部(31，51)相连。
4.根据上述权利要求之一所述的功率半导体模块，其中，第二功率半导体芯片(2)的下部金属化部(22)具有厚度大于1μm或者大于2μm的至少一个第一部分层(22a)，所述至少一个第一部分层(22a)以重量百分比大于99来由铜制成。
5.根据上述权利要求之一所述的功率半导体模块，其中，第二功率半导体芯片(2)的下部金属化部(22)借助扩散焊接层(16)、粘合层或者借助含银的烧结层与陶瓷衬底(4，5)的上部金属化部(41，51)相连。
6.根据上述权利要求之一所述的功率半导体模块，其中，第一功率半导体芯片(1)的上部金属化部(11)具有厚度大于1μm或者大于2μm的至少一个第一部分层(11a)，所述至少一个第一部分层(11a)以重量百分比大于99来由铝制成。
7.根据上述权利要求之一所述的功率半导体模块，其中，第一接合线(71)被接合到第一功率半导体芯片(1)的上部金属化部(11)上，所述第一接合线(71)以重量百分比大于99.9来由铝制成。
8.具有权利要求6和7的特征的功率半导体模块，其中，第一接合线(71)直接接触第一功率半导体芯片(1)的上部金属化部(11)的第一部分层(11a)。
9.根据上述权利要求之一所述的功率半导体模块，其中，第二功率半导体芯片(2)的上部金属化部(21)具有厚度大于1μm或者大于2μm的至少一个第一部分层(12a)，所述至少一个第一部分层(12a)以重量百分比大于99来由铜制成。
10.根据上述权利要求之一所述的功率半导体模块，其中，接合线(73)被接合到第二功率半导体芯片(1)的上部金属化部(21)上，所述接合线(73)以重量百分比大于99.9来由铜制成。
11.具有权利要求9和10的特征的功率半导体模块，其中，第二接合线(72)直接接触第二功率半导体芯片(2)的上部金属化部(21)的第一部分层(21a)。
12.根据上述权利要求之一所述的功率半导体模块，其中，至少一个陶瓷衬底(3，4，5)的布置有至少一个功率半导体芯片(1，2)的每个陶瓷衬底在背离上部金属化部(11，21)的一侧上具有下部金属化部(12，22)，所述下部金属化部(12，22)形成功率半导体模块(100)的下侧，其中在多个陶瓷衬底(3，4)的情况下，所述多个陶瓷衬底(3，4)的下部金属化部(12，22)彼此相间隔。
13.根据权利要求1至11之一所述的功率半导体模块，其具有金属的底板(9)，所述底板(9)具有上侧(91)和下侧(92)，其中底板(9)的下侧(92)形成功率半导体模块(100)的下侧(100b)的至少一部分，并且其中至少一个陶瓷衬底(3，4，5)的布置有至少一个功率半导体芯片(1，2)的每个陶瓷衬底的下部金属化部(12，22)牢固地与底板(9)的上侧(91)相连。
14.根据权利要求13所述的功率半导体模块，其中，第一功率半导体芯片(1)被布置在至少一个陶瓷衬底(3，4)的第一陶瓷衬底(3)上，并且其中，第一陶瓷衬底(3)在下部金属化部(32)上借助熔融焊接层牢固地与底板(9)的上侧(91)相连。
15.根据权利要求14所述的功率半导体模块，其中，第一功率半导体芯片(1)的下部金属化部(12)借助熔融焊接层牢固地与第一陶瓷衬底(3)的上部金属化部(31)相连。
16.根据权利要求13至15之一所述的功率半导体模块，其中，第二功率半导体芯片(2)被布置在至少一个陶瓷衬底(3，4)的第二陶瓷衬底(4)上，并且其中，第二陶瓷衬底(4)在下部金属化部(42)上借助扩散焊接层、粘合层或者借助含银的烧结层牢固地与底板(9)的上侧(91)相连。
17.根据权利要求16所述的功率半导体模块，其中，第二功率半导体芯片(2)的下部金属化部(22)借助扩散焊接层、粘合层或者借助含银的烧结层牢固地与第二陶瓷衬底(4)的上部金属化部(41)相连。
18.根据权利要求13至17之一所述的功率半导体模块，其中，底板(9)具有至少一个第一段(9a)和第二段(9b)，其中
-第一陶瓷衬底(3)被布置在第一段(9a)上，在所述第一陶瓷衬底(3)上布置第一功率半导体芯片(1)；
-第二陶瓷衬底(4)被布置在第二段(9b)上，在所述第二陶瓷衬底(4)上布置第二功率半导体芯片(2)。
19.根据权利要求18所述的功率半导体模块，其中，第一段(9a)和第二段(9b)一体式地被构造并且借助一个或者多个连接接片(94)彼此连接。
20.根据权利要求18所述的功率半导体模块，其中，第一段(9a)和第二段(9b)彼此相间隔。
21.根据权利要求1至20之一所述的功率半导体模块，其中，整流器电路(G)的所有功率半导体芯片(1)被布置在共同的第一陶瓷衬底(3)上并且利用下部芯片金属化部(12)分别借助熔融焊接层与共同的第一陶瓷衬底(3)的上部金属化部(31)相连接。
22.根据权利要求1至21之一所述的功率半导体模块，其中，逆变器电路(W)的所有功率半导体芯片(2)被布置在共同的第二陶瓷衬底(4)上并且利用下部芯片金属化部(22)分别借助扩散焊接层、粘合层或者借助含银的烧结层与共同的第二陶瓷衬底(4)的上部金属化部(41)相连接。
23.根据权利要求1至13之一所述的功率半导体模块，其包括带有上部金属化部(51)的共同的第三陶瓷衬底(5)，其中
-第一功率半导体芯片(1)的下部金属化部(12)借助熔融焊接层与共同的第三陶瓷衬底(5)的上部金属化部(51)相连；
-第二功率半导体芯片(2)的下部金属化部(22)借助含银的烧结层、粘合层或者借助扩散焊接层与共同的第三陶瓷衬底(5)的上部金属化部(51)相连接。
24.根据上述权利要求之一所述的功率半导体模块，其中，
-整流器电路(G)的所有布置在壳体(60)中的功率半导体芯片(1)具有铝比例为重量百分比分别大于50的上部芯片金属化部(11)和下部芯片金属化部(12)；
-逆变器电路(W)的所有布置在壳体(60)中的功率半导体芯片(2)具有铜比例为重量百分比分别大于50的上部芯片金属化部(21)和下部芯片金属化部(22)。
25.根据权利要求24所述的功率半导体模块，其中，
-整流器电路(G)的所有功率半导体芯片(1)在空间上以第一组而逆变器电路(W)的所有功率半导体芯片(2)在空间上以第二组被布置在共同的陶瓷衬底(5)上；
-在第一组的功率半导体芯片(1)和第二组的功率半导体芯片(2)之间的最小距离(d)大于5mm或者大于10mm。
26.一种用于驱动功率半导体模块的方法，其具有如下步骤：
-提供根据上述权利要求之一所述的功率半导体模块(100)；
-在阻挡层温度小于150℃或者小于125℃的情况下驱动第一功率半导体芯片(1)；
-在阻挡层温度大于150℃的情况下驱动第二功率半导体芯片(2)。
27.根据权利要求26所述的用于驱动功率半导体模块的方法，其中，
-整流器电路(G)的所有布置在壳体(60)中的功率半导体芯片(1)在阻挡层温度小于150℃或者小于125℃的情况下运行；
-逆变器电路(W)的所有布置在壳体(60)中的功率半导体芯片(2)在阻挡层温度大于150℃的情况下运行。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035601A (zh) * 2011-08-22 2013-04-10 英飞凌科技股份有限公司 在烧结银层上包括扩散焊接层的半导体器件
CN104254203A (zh) * 2013-06-25 2014-12-31 英飞凌科技股份有限公司 电路布置以及用于制造所述电路布置的方法
CN104851843A (zh) * 2014-02-17 2015-08-19 三菱电机株式会社 电力用半导体装置
CN107452637A (zh) * 2016-04-29 2017-12-08 丹佛斯硅动力有限责任公司 用于将功率半导体模块的第一部件粘结性地连接到功率半导体模块的第二部件的方法
CN107851634A (zh) * 2015-05-22 2018-03-27 Abb瑞士股份有限公司 功率半导体模块
CN108807301A (zh) * 2017-05-01 2018-11-13 恩智浦美国有限公司 使用烧结附着的封装微电子组件安装
CN109216313A (zh) * 2017-07-02 2019-01-15 英飞凌科技股份有限公司 具有包括钎焊的导电层的芯片载体的模制封装
CN111937127A (zh) * 2018-04-11 2020-11-13 Abb电网瑞士股份公司 功率半导体芯片上的材料减少的金属板

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010112983A1 (en) * 2009-03-31 2010-10-07 Stmicroelectronics (Grenoble 2) Sas Wire-bonded semiconductor package with a coated wire
DE102010002627B4 (de) * 2010-03-05 2023-10-05 Infineon Technologies Ag Niederinduktive Leistungshalbleiterbaugruppen
US8704269B2 (en) 2010-12-22 2014-04-22 Infineon Technologies Ag Die package
DE102011078811B3 (de) 2011-07-07 2012-05-24 Semikron Elektronik Gmbh & Co. Kg Leistungselektronisches System mit einer Kühleinrichtung
DE102011078806B4 (de) 2011-07-07 2014-10-30 Semikron Elektronik Gmbh & Co. Kg Herstellungsverfahren für ein leistungselektronisches System mit einer Kühleinrichtung
JP5633496B2 (ja) * 2011-09-29 2014-12-03 三菱電機株式会社 半導体装置及びその製造方法
US8563364B2 (en) * 2011-09-29 2013-10-22 Infineon Technologies Ag Method for producing a power semiconductor arrangement
DE102011115886B4 (de) * 2011-10-15 2020-06-18 Danfoss Silicon Power Gmbh Verfahren zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten
DE102011115887A1 (de) 2011-10-15 2013-04-18 Danfoss Silicon Power Gmbh Leistungshalbleiterchip mit oberseitigen Potentialflächen
JP5811803B2 (ja) * 2011-11-22 2015-11-11 住友電気工業株式会社 半導体装置及び半導体装置の製造方法
JP5588956B2 (ja) * 2011-11-30 2014-09-10 株式会社 日立パワーデバイス パワー半導体装置
JP5976678B2 (ja) * 2011-12-20 2016-08-24 株式会社東芝 セラミックス銅回路基板
US20130175704A1 (en) * 2012-01-05 2013-07-11 Ixys Corporation Discrete power transistor package having solderless dbc to leadframe attach
US8916968B2 (en) * 2012-03-27 2014-12-23 Infineon Technologies Ag Multichip power semiconductor device
US8716864B2 (en) * 2012-06-07 2014-05-06 Ixys Corporation Solderless die attach to a direct bonded aluminum substrate
JP5664625B2 (ja) * 2012-10-09 2015-02-04 三菱マテリアル株式会社 半導体装置、セラミックス回路基板及び半導体装置の製造方法
CN104919589B (zh) * 2012-10-15 2019-01-29 富士电机株式会社 半导体装置
US20140105767A1 (en) * 2012-10-16 2014-04-17 Denso Corporation Power supply module
KR101443972B1 (ko) * 2012-10-31 2014-09-23 삼성전기주식회사 일체형 전력 반도체 모듈
DE102012222791A1 (de) 2012-12-11 2014-06-12 Robert Bosch Gmbh Verfahren zur Kontaktierung eines Halbleiters und Halbleiterbauelement mit erhöhter Stabilität gegenüber thermomechanischen Einflüssen
US8987911B2 (en) 2012-12-31 2015-03-24 Ixys Corporation Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package
US8847328B1 (en) * 2013-03-08 2014-09-30 Ixys Corporation Module and assembly with dual DC-links for three-level NPC applications
US10308856B1 (en) 2013-03-15 2019-06-04 The Research Foundation For The State University Of New York Pastes for thermal, electrical and mechanical bonding
US9445532B2 (en) * 2013-05-09 2016-09-13 Ford Global Technologies, Llc Integrated electrical and thermal solution for inverter DC-link capacitor packaging
EP2825009B8 (en) * 2013-07-09 2016-11-23 ABB Schweiz AG Electric converter with compact module arrangement for subsea applications
JP6299120B2 (ja) * 2013-09-05 2018-03-28 富士電機株式会社 半導体モジュール
JP5854011B2 (ja) * 2013-09-06 2016-02-09 トヨタ自動車株式会社 半導体装置、及び半導体装置の製造方法
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
JP2015185570A (ja) * 2014-03-20 2015-10-22 三菱電機株式会社 電力用半導体装置
DE102014214766A1 (de) * 2014-07-28 2015-06-25 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Leistungsmoduls sowie Leistungsmodul
DE102014218426A1 (de) * 2014-09-15 2016-03-17 Siemens Aktiengesellschaft Baugruppe mit mindestens zwei Tragkörpern und einen Lotverbund
JP6357394B2 (ja) * 2014-09-30 2018-07-11 ルネサスエレクトロニクス株式会社 半導体装置
US10319674B2 (en) * 2014-10-29 2019-06-11 Infineon Technologies Americas Corp. Packaged assembly for high density power applications
CN204991692U (zh) * 2014-11-26 2016-01-20 意法半导体股份有限公司 具有引线键合和烧结区域的电子器件
DE102015113421B4 (de) 2015-08-14 2019-02-21 Danfoss Silicon Power Gmbh Verfahren zum Herstellen von Halbleiterchips
DE102015115271B4 (de) 2015-09-10 2021-07-15 Infineon Technologies Ag Elektronikbaugruppe mit entstörkondensatoren und verfahren zum betrieb der elektronikbaugruppe
US20170084521A1 (en) 2015-09-18 2017-03-23 Industrial Technology Research Institute Semiconductor package structure
DE102016117389B4 (de) * 2015-11-20 2020-05-28 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung
US10418347B2 (en) * 2016-03-03 2019-09-17 Mitsubishi Electric Corporation Power semiconductor device and power semiconductor core module
JP6750263B2 (ja) * 2016-03-18 2020-09-02 富士電機株式会社 電力用半導体モジュール
DE102016106284A1 (de) * 2016-04-06 2017-10-12 Epcos Ag Modul
US10410952B2 (en) 2016-12-15 2019-09-10 Infineon Technologies Ag Power semiconductor packages having a substrate with two or more metal layers and one or more polymer-based insulating layers for separating the metal layers
US10008411B2 (en) 2016-12-15 2018-06-26 Infineon Technologies Ag Parallel plate waveguide for power circuits
DE112018001769B4 (de) 2017-03-31 2022-05-05 Rohm Co., Ltd. Leistungsmodul und Herstellungsverfahren des Leistungsmoduls
US11043465B2 (en) * 2017-05-11 2021-06-22 Sumitomo Electric Industries, Ltd. Semiconductor device
CN110663110B (zh) * 2017-05-30 2023-04-18 三菱电机株式会社 半导体功率模块
KR102445515B1 (ko) * 2017-09-29 2022-09-21 현대자동차주식회사 차량용 전력모듈
DE102018110132B3 (de) * 2018-04-26 2018-11-29 Semikron Elektronik Gmbh & Co. Kg Drucksinterverfahren bei dem Leistungshalbleiterbauelemente mit einem Substrat über eine Sinterverbindung miteinander verbunden werden
US20220223546A1 (en) * 2019-06-19 2022-07-14 Mitsubishi Electric Corporation Semiconductor device and power converter
DE102019209829A1 (de) * 2019-07-04 2021-01-07 Audi Ag Vorrichtung umfassend einen Kühlkörper und Kraftfahrzeug
EP3770962A1 (en) * 2019-07-26 2021-01-27 Infineon Technologies AG Semiconductor module arrangement
EP4002454A1 (en) * 2020-11-23 2022-05-25 Hitachi Energy Switzerland AG Electrical contact arrangement, power semiconductor module, method for manufacturing an electrical contact arrangement and method for manufacturing a power semiconductor module
DE102020130991A1 (de) 2020-11-24 2022-05-25 Audi Aktiengesellschaft Halbbrückenmodul mit präziser Temperaturerfassung
JP7444084B2 (ja) * 2021-01-14 2024-03-06 三菱電機株式会社 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004266002A (ja) * 2003-02-28 2004-09-24 Mitsubishi Materials Corp 放熱体の製造方法及び放熱体並びにこの放熱体を用いたパワーモジュール用基板及びパワーモジュール
US20080093729A1 (en) * 2006-10-20 2008-04-24 Dirk Siepe Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate
CN101431069A (zh) * 2007-11-05 2009-05-13 英飞凌科技股份公司 具有温度传感器的功率半导体模块

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL281483A (zh) * 1961-10-31 1900-01-01
US3716759A (en) * 1970-10-12 1973-02-13 Gen Electric Electronic device with thermally conductive dielectric barrier
US5015803A (en) * 1989-05-31 1991-05-14 Olin Corporation Thermal performance package for integrated circuit chip
US5539254A (en) * 1994-03-09 1996-07-23 Delco Electronics Corp. Substrate subassembly for a transistor switch module
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US5530284A (en) * 1995-03-06 1996-06-25 Motorola, Inc. Semiconductor leadframe structure compatible with differing bond wire materials
US6143655A (en) * 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US7235810B1 (en) * 1998-12-03 2007-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6806808B1 (en) * 1999-02-26 2004-10-19 Sri International Wireless event-recording device with identification codes
US6617963B1 (en) * 1999-02-26 2003-09-09 Sri International Event-recording devices with identification codes
US6329714B1 (en) * 1999-11-01 2001-12-11 General Semiconductor, Inc. Hybrid S.C. devices and method of manufacture thereof
JPWO2003021664A1 (ja) * 2001-08-31 2005-07-07 株式会社日立製作所 半導体装置、構造体及び電子装置
US20040210289A1 (en) * 2002-03-04 2004-10-21 Xingwu Wang Novel nanomagnetic particles
US7832177B2 (en) * 2002-03-22 2010-11-16 Electronics Packaging Solutions, Inc. Insulated glazing units
US6962834B2 (en) * 2002-03-22 2005-11-08 Stark David H Wafer-level hermetic micro-device packages
US20060191215A1 (en) * 2002-03-22 2006-08-31 Stark David H Insulated glazing units and methods
WO2004068189A2 (en) * 2003-01-27 2004-08-12 David Stark Hermetic window assemblies and frames
US6906404B2 (en) * 2003-05-16 2005-06-14 Ballard Power Systems Corporation Power module with voltage overshoot limiting
US6987670B2 (en) * 2003-05-16 2006-01-17 Ballard Power Systems Corporation Dual power module power system architecture
US7505294B2 (en) * 2003-05-16 2009-03-17 Continental Automotive Systems Us, Inc. Tri-level inverter
JP4037815B2 (ja) * 2003-09-29 2008-01-23 オムロンレーザーフロント株式会社 レーザダイオードモジュール、レーザ装置、及びレーザ加工装置
US7586171B2 (en) * 2004-04-14 2009-09-08 Yong Cao Organic electronic device comprising conductive members and processes for forming and using the organic electronic device
DE102004059389B4 (de) 2004-12-09 2012-02-23 Infineon Technologies Ag Halbleiterbauelement mit Ausgleichsmetallisierung
DE102005024321B8 (de) * 2005-05-27 2012-10-04 Infineon Technologies Ag Absicherungsschaltung
DE102005024346B4 (de) * 2005-05-27 2012-04-26 Infineon Technologies Ag Sicherungselement mit Auslöseunterstützung
DE102005024347B8 (de) * 2005-05-27 2010-07-08 Infineon Technologies Ag Elektrisches Bauteil mit abgesichertem Stromzuführungsanschluss
DE112005003653B4 (de) * 2005-08-26 2013-05-16 Siemens Aktiengesellschaft Leistungshalbleitermodul mit auf Schaltungsträger aufgebrachten Lastanschlusselementen und Anschlussklemmelementen
US20070236849A1 (en) * 2006-04-06 2007-10-11 Littelfuse, Inc. Leadless integrated circuit protection device
US7804131B2 (en) * 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
DE102006036798B4 (de) * 2006-08-07 2013-08-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
DE102006044691B4 (de) * 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
US7825621B2 (en) * 2007-08-28 2010-11-02 Rockwell Automation Technologies, Inc. Junction temperature reduction for three phase inverters modules
DE102007046556A1 (de) 2007-09-28 2009-04-02 Infineon Technologies Austria Ag Halbleiterbauelement mit Kupfermetallisierungen

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004266002A (ja) * 2003-02-28 2004-09-24 Mitsubishi Materials Corp 放熱体の製造方法及び放熱体並びにこの放熱体を用いたパワーモジュール用基板及びパワーモジュール
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CN104851843A (zh) * 2014-02-17 2015-08-19 三菱电机株式会社 电力用半导体装置
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CN111937127A (zh) * 2018-04-11 2020-11-13 Abb电网瑞士股份公司 功率半导体芯片上的材料减少的金属板
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