CN110753996B - 功率电子设备模块 - Google Patents
功率电子设备模块 Download PDFInfo
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- CN110753996B CN110753996B CN201880038531.6A CN201880038531A CN110753996B CN 110753996 B CN110753996 B CN 110753996B CN 201880038531 A CN201880038531 A CN 201880038531A CN 110753996 B CN110753996 B CN 110753996B
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Abstract
一种功率电子设备模块(10),其包括:具有衬底金属化层(14)的衬底(12),该衬底金属化层被分成用于为功率电子设备模块(10)提供导电路径的导电区域(16,18);半导体开关芯片(26),其利用第一功率电极(28)结合至衬底金属化层(14)的第一导电区域(18);导体板(34,34’),其结合至半导体开关芯片(26)的与第一功率电极(28)相对的第二功率电极(30);以及栅极导体(40,40’),其结合至半导体开关芯片(26)的除第二功率电极(30)以外的栅电极(32);其中,导体板(34,34’)延伸到衬底金属化层(14)的第二导电区域(18),并且栅极导体(40,40’)延伸穿过布置在栅电极(32)上方的所述导体板(34,34’)中的开口(38)。
Description
技术领域
本发明涉及一种功率电子设备模块。
背景技术
包含固态开关器件如IGBT或功率MOSFET的功率电子设备模块被用于各种功率电子设备应用中,以对电流进行切换或整流。一种重要且快速增长的应用是用于电动或混合动力车辆的转换器系统。用于此类应用的典型六件套模块可具有高达1200V的额定电压和数百安的额定电流。由于电动车辆中的安装空间通常非常有限且受到几何形状的约束,所以电气传动系统的功率电子设备模块和转换器尽可能紧凑以允许灵活的安装是非常有利的。
一种增加功率电子设备模块的功率密度的方法是芯片堆叠,即,弃用半导体芯片的并排布置的传统二维电路布局而转向第三维的布置。例如,可以将半导体开关及其续流二极管一起堆叠到芯片叠层中。
尽管可以通过芯片堆叠来减小半导体芯片的占用空间,但是其它板载部件和电导体仍然布置在芯片叠层的旁边,并且可能导致进一步明显的占用空间和相应的杂散电感,这可能导致显著的电磁耦合。
此外,芯片堆叠可能导致涉及多个单独的粘结层界面和材料的复杂制造序列。
JP 2004 311 685A、US 2012 181 996A1和US 2013 113 114A1示出了具有堆叠的半导体芯片的电子设备模块。
发明内容
本发明的一个目的是提供一种具有增强的功率密度的功率电子设备模块,该功率电子设备模块具有通过该功率电子设备模块提供的半导体芯片的电气互连所产生的低杂散电感。本发明的另一目的是简化功率电子设备模块的制造。
这些目的通过独立权利要求的主题来实现。根据从属权利要求和以下描述,其它示例性实施例是显而易见的。
本发明涉及一种功率电子设备模块。功率电子设备模块可以是机械地和电气地支持一个或多个半导体芯片的任何组件。必须指出的是,术语“功率”可以与以下模块和/或半导体芯片有关,即,其适于处理100V以上的电压和/或10A以上。
根据本发明的一个实施例,该功率电子设备模块包括:具有衬底金属化层的衬底,该衬底金属化层被分成用于为功率电子设备模块提供导电路径的多个导电区域;至少一个半导体开关芯片,其利用第一功率电极结合至衬底金属化层的第一导电区域;导体板,该导体板结合至半导体开关芯片的与第一功率电极相对的第二功率电极;以及栅极导体,该栅极导体结合至半导体芯片的除第二功率电极以外的栅电极。
所述衬底可以是陶瓷衬底,其在至少一侧上设置有金属化层,该金属化层可以是铜层。半导体开关芯片可以包括晶体管或晶闸管。例如,半导体开关芯片可以是IGBT或MOSFET。半导体开关芯片可以基于宽带隙材料,例如SiC。
如将在下面更详细描述的,该功率电子设备模块还可以包括具有二极管的半导体芯片,该二极管可以与半导体开关芯片的开关反并联连接。同样,具有二极管的半导体芯片可以基于诸如SiC的宽带隙材料。宽带隙半导体芯片可以减少损耗和/或具有在较高接合温度(例如高于200℃)下工作的能力。
所述半导体开关芯片以及具有二极管的所述另一半导体芯片可以是具有两个平坦侧面的竖向器件,在所述两个平坦侧面上设置有两个功率电极。一个功率电极可以是相应芯片上的金属化层,其适于传导要通过芯片的半导体元件切换的电流。另一方面,栅电极的面积可以小于功率电极的面积。
第一功率电极可以是集电极,第二功率电极可以是发射极。在这种情况下,所述导体板可以是发射极导体的一部分。
所述半导体开关芯片可以结合至衬底金属化层的一个导电区域并结合至导体板。在本文中,“结合(bonding)”可以指与导电材料的钎焊、烧结、熔焊和/或胶合。
所述导体板可以是适于传导电流通过半导体开关芯片的任何基本上扁平的导电体。例如,导体板可以由金属板、金属片或印刷电路板的金属化层制成。印刷电路板可以包括塑料衬底,该塑料衬底在一面或两面上包括一个或多个金属化层。
所述栅极导体仅需要适于将控制信号传导至半导体开关芯片。例如,栅极导体可以包括一条或多条结合线和/或印刷电路板的金属化层。
根据本发明的一个实施例,导体板延伸到衬底金属化层的第二导电区域,并且栅极导体延伸穿过布置在栅电极上方的导体板中的开口。在此上下文中,术语“延伸”可以指导体板在半导体开关芯片的一侧上方突出和/或导体板朝向衬底上的第二导电区域延伸。
以这种方式,除了栅电极之外,导体板可以完全覆盖半导体开关。此外,对于定向导体板具有更大的灵活性。例如,结合至衬底金属化层的栅极导体的端部可以定位在与栅极导体的取向相同的方向上。
另外,栅极导体和导体板可以堆叠,这最大限度地减小了功率电子设备模块内部的电导体的占用空间。因此,作为另一个优点,可以提高功率电子设备模块的功率密度。
作为第三个益处,平行取向的栅极导体和导体板可以减少栅极回路——即,功率电子设备模块的电路的将栅极通常与半导体开关芯片的发射极互连的部分——的杂散电感。除了换流回路和栅极回路的低杂散电感以外,还减少了这些回路之间的耦合,这可以导致更快和更清晰的切换。
根据本发明的一个实施例,导体板中的所述开口是通孔。例如,开口可以相对于导体板居中,和/或可以相对于导体板的朝向结合至衬底金属化层的端部的取向位于导体板的中间。
然而,开口也可以位于导体板的边界处,和/或可以是导体板的边界中的凹部。
根据本发明的一个实施例,栅极导体在导体板上方延伸。栅极导体和导体板可以在相同的方向上定向。这可以导致基本同轴的栅极-发射极电路布置。栅极导体和导体板也可以至少部分地相对于彼此基本平行地延伸。
根据本发明的一个实施例,栅极导体包括结合线。结合线可以结合至栅电极,可以延伸穿过导体板中的开口,可以沿着导体板和/或在导体板上方延伸。结合线可以在其另一端处结合至另一导体,该另一导体例如可以由衬底和/或附接到导体板的顶部的印刷电路板提供。
必须指出的是,本文中使用的术语“顶部”和“底部”可以是指相对于功率电子设备模块的衬底的面的取向。顶面可以背离衬底,而底面可以面向衬底。例如,第一功率电极可以是底部电极,而第二电极和栅电极可以是顶部电极。
根据本发明的一个实施例,所述导体板是第一金属夹。导体板可以由金属片或金属板制成,并且可以弯折成使得它的可以结合至第二功率电极和衬底金属化层的端部处于要求的高度处。第一金属夹还可以弯折成使得可以具有开口的中间部分处于比第一金属夹的端部更高的高度处。一般而言,该第一金属夹可以是弯折的金属夹。
根据本发明的一个实施例,第一金属夹通过第一端结合至第二功率电极,并且第一金属夹通过第二端结合至衬底金属化层的第二导电区域。类似于衬底金属化层的第一导电区域,第二导电区域可以连接到功率电子设备模块的相应端子。
根据本发明的一个实施例,栅极导体衬底附接到第一金属夹的第二端上,该栅极导体衬底具有与结合线结合的栅极金属化层。栅极导体衬底可以是印刷电路板或直接结合的铜衬底。在导体板上方引导和/或堆叠栅极的电气路径可以附加地减小功率电子设备模块的电导体的占用空间。栅极导体衬底可以被实现为在功率电子设备模块的一个或多个半导体开关芯片的一个或多个导体板上方的带状线。
另外,在栅极导体之后的栅极路径也可以具有低电感。总之,当栅极导体被引导穿过导体板的开口并且结合至被实现为带状线的栅极导体衬底时,这可以提供极好的同轴布置,以使杂散电感和串扰最小化。
根据本发明的一个实施例,将结合预成型件结合至第一金属夹的第一端上,其中第二半导体芯片利用第一功率电极结合至结合预成型件上。第二半导体芯片可以是二极管和/或可以基于SiC衬底,即,第二半导体芯片可以是SiC二极管。二极管可以反并联连接至半导体开关芯片的开关。
这可以导致一种堆叠的半导体芯片布置,其减小了功率电子设备模块的半导体芯片的占用空间。而且,结合预成型件可以用作结合间隔件,即,可以具有第一半导体芯片和第二半导体芯片尽可能远地间隔开以满足电压清除和间隙的要求的高度。
此外,利用结合预成型件可以简化半导体芯片叠层的结合。双面的结合预成型件可以允许通过拾取和放置过程以自动化友好的方式制造叠层。在第一金属夹上预先施加的烧结膏可进一步改善可制造性。另外,结合层和附加间隔件不会由于热膨胀而不能配合。
根据本发明的一个实施例,结合预成型件是具有金属材料的芯部和烧结材料的两个外层的烧结预成型件,该两个外层适于将第一金属夹和第二半导体芯片烧结在结合预成型件上。烧结材料可以是由Ag制成的多孔材料,例如由纳米颗粒——即直径小于1000nm的颗粒——制成。芯部可以由Ag板或另一种金属材料的板制成。
在半导体开关芯片的顶面上进行烧结可以具有以下优点:避免在敏感边缘终端区域附近处于液相的任何导电结合材料,其可能例如由于在加工期间的飞溅和/或焊珠而导致产量损失。
根据本发明的一个实施例,结合预成型件可以是瞬态液相结合预成型件。这样的预成型件可以由两种不同金属材料的颗粒和/或元件制成,这两种不同金属材料适于形成熔点在这两种金属材料之间的合金。例如,这种预成型件可以由填充有Sn或Sn焊料的Cu网制成,其在加热时转变成金属间Cu/Sn相。
根据本发明的一个实施例,第二金属夹结合至第二半导体芯片的与第一功率电极相对的第二功率电极。第二金属夹可以结合至衬底金属化层的第一导电区域。这种夹也可以覆盖基本上所有的第二功率电极和/或第二半导体芯片。必须指出的是,第二金属夹可以在与结合在第一和第二半导体芯片之间的第一金属夹不同的方向上定向。换句话说,这些第一和第二金属夹的从半导体芯片的叠层突出的端部可以在不同取向的方向上突出,例如基本正交的方向。
根据本发明的一个实施例,电子部件附接到第二半导体芯片上方的第二金属夹上。第二半导体芯片上方的空间可用于定位功率电子设备模块的附加部件。该部件可以包括电子部件、无源元件和/或端子。当将功率电子设备模块的其它部件放置在第二半导体芯片的顶部上时,可以减小整个衬底的占用空间。
无源元件可以包括温度传感器、栅极电阻器、去耦电容器、其它传感器和/或滤波器。
这些部件可以例如通过温度传感器提供功率电子设备模块的在线诊断,该温度传感器可以热耦合到半导体芯片的叠层。此外,这些部件可以包括加速度计、振动传感器等。
第二半导体芯片上的端子可以被设计用于向功率电子设备模块的外部提供功率和/或辅助连接。这样的端子可以竖向布置并且可以从功率电子设备模块沿相同方向突出。这可以进一步最小化功率电子设备模块的导体的占用空间。
根据本发明的一个实施例,具有金属化层的顶部衬底在第二半导体芯片上方附接到第二金属夹上。例如,顶部衬底可以是电路板,诸如聚合物和/或陶瓷电路板,例如DBC(直接结合Cu)、DBA(直接结合Al)、AMB(活性金属钎焊)和LTCC(低温共烧制陶瓷)衬底。
根据本发明的一个实施例,一个部件附接到顶部衬底上。例如,顶部衬底可以是具有电子部件的电路板。如果分立部件要求电绝缘的附接,则电路板和分立部件的组合是有益的。
此外,可以将一条或多条结合线结合至顶部衬底。例如,顶部衬底可以用作两条结合线互连布置之间的中间导体。
根据本发明的一个实施例,功率电子设备模块包括:附接在半导体开关芯片上的印刷电路板,其中所述导体板是印刷电路板的外部金属化层。
结合至衬底金属化层的所述一个或多个半导体开关芯片可以与印刷电路板堆叠,在印刷电路板中嵌入一个或多个第二半导体芯片,其例如提供二极管。可以通过嵌入在印刷电路板中来预先封装第二半导体芯片,并且可以将印刷电路板结合至所述一个或多个半导体开关芯片的所述一个或多个第二功率电极。
根据本发明的一个实施例,一导电间隔件互连在衬底金属化层的第二导电区域与印刷电路板的外部金属化层所提供的导体板之间。该间隔件可以具有与半导体开关芯片相同的高度,以补偿印刷电路板的底面与功率电子设备模块的衬底之间的距离。
根据本发明的一个实施例,栅极导体包括印刷电路板的金属化层。在印刷电路板的内部和/或表面上可以存在多层导电层。例如,栅极导体可以是中间金属化层。以这种方式,栅极-发射极环路的一部分可以由以小的间距平行布置的导体提供。
栅电极可以结合至由印刷电路板提供的金属化层的一个区域。以此方式,可在一个步骤中制造半导体开关芯片的栅极连接件和发射极连接件。
根据本发明的一个实施例,印刷电路板包括在导体板中的所述开口上方的开口。栅极导体可以包括被引导穿过这两个开口的结合线,这两个开口即印刷电路板中的开口和结合至半导体芯片的第二功率电极的导体板中的开口。在这种情况下,结合线可以例如在印刷电路板的顶面上结合至印刷电路板的金属化层。
根据本发明的一个实施例,第二半导体芯片被嵌入印刷电路板中并与导体板电气互连。如已经提到的,印刷电路板可以包括一个或多个二极管芯片,其可以在印刷电路板内部连接到用作导体板的金属化层。
根据本发明的一个实施例,第二半导体芯片经由印刷电路板的一个或多个金属化层与衬底金属化层的第一导电区域互连。可以具有与半导体开关芯片相同的高度的导电间隔件可以互连在第一导电区域与印刷电路板之间。以这种方式,可在一个步骤中制造印刷电路板与具有半导体开关芯片的衬底之间的电气互连装置。
参考下文描述的实施例,本发明的这些和其它方面将变得明显并予以阐明。
附图说明
下面将参考附图中示出的示例性实施例更详细地说明本发明的主题。
图1示意性地示出了根据本发明的一个实施例的功率电子设备模块的截面图。
图2示意性地示出了根据本发明的又一实施例的功率电子设备模块的截面图。
图3示意性地示出了根据本发明的又一实施例的功率电子设备模块的截面图。
图4示意性地示出了根据本发明的又一实施例的功率电子设备模块的截面图。
图5示意性地示出了根据本发明的又一实施例的功率电子设备模块的截面图。
图6示意性地示出了根据本发明的又一实施例的功率电子设备模块的截面图。
图7示意性地示出了根据本发明的又一实施例的功率电子设备模块的顶视图。
附图中使用的附图标记以及它们的含义以概括形式在附图标记列表中列出。原则上,附图中对相同的部件提供相同的附图标记。
具体实施方式
图1示出了功率电子设备模块10,其包括衬底12,例如陶瓷衬底,在衬底的顶面上具有金属化层14。可以是铜层的金属化层14可以被分割成多个导电区域16、18。导电区域16可以与功率电子设备模块的DC-端子20或AC端子22连接(参见图7)。导电区域18可以与AC端子22或DC+端子24连接。
在导电区域16上,半导体开关芯片26与第一底部电极28结合。半导体开关芯片26可以基于SiC和/或可以提供IGBT或MOSFET。在另一上侧面上,半导体开关芯片28包括第二上部功率电极30,并且除了功率电极30之外还包括栅电极32。半导体开关芯片26可以具有基本平坦的主体和/或电极28、30、32可以是基本上平坦的金属层。
功率电极30与第一金属夹34的第一端结合,第一金属夹34可以看作是导体板34,其通过第二端结合至导电区域16。第一金属夹可以由铜板或铜片制成。第一金属夹34被弯折,使得其端部位于功率电极30和导电区域16的高度上,并使得中间部分36相对于功率电极30抬高。在中间部分36中,第一金属夹34包括位于栅电极30上方的开口38。如虚线所示,第一金属夹34的各部分在开口38的外部彼此互连。如图7所示,开口38可以是通孔,其可以在第一金属夹34中居中。
返回图1,形式为结合线40的栅极导体40被引导穿过开口38,并通过一端与栅电极32结合。结合线40通过另一端与栅极导体衬底42结合,栅极导体衬底42可以包括电绝缘中间层44和两个外部导电层46、48。利用层46可以将栅极导体衬底42结合至第一金属夹34的与导电区域16结合的端部的上侧面。结合线40结合至栅极导体层48。栅极导体衬底42可以是印刷电路板或直接结合的铜陶瓷衬底。
如图7所示,栅极导体衬底42可以设计成如同经由多个第一金属夹34被引导的带状线。
结合线40沿与第一金属夹34相同的方向延伸。由于第一金属夹34中的开口38,结合线40在第一金属夹34上方延伸,并与第一金属夹34上的栅极导体衬底42一起延伸,栅极-发射极环路的杂散电感得以减少。此外,功率电子设备模块10的组成部件的布置是紧凑的并且可以提高功率密度。
图2示出了第二半导体芯片50可以与半导体芯片18堆叠。半导体芯片50经由结合预成型件54与底部电极52一起结合至第一金属夹34的与半导体芯片18结合的端部的上侧面。
结合预成型件54可以由金属芯部56制成,两个烧结材料层58附接到该金属芯部56。例如,芯部56可以由Ag或Cu制成,和/或烧结层58可以由Ag颗粒诸如纳米Ag颗粒制成。可以调节结合预成型件54的芯部56,从而提供足够的间隙距离以使第二半导体芯片50的边缘终端绝缘。例如,该间隙距离可以是150μm以隔离额定1.2kV的芯片26、50。
第二半导体芯片50的上部电极60可以通过结合线61与第一导电区域18连接。第二半导体芯片50可以提供二极管,该二极管以这种方式与第一半导体芯片26的开关反并联连接。
图3示出:可替代地,第二半导体芯片50的上部电极60可以利用可由铜制成的另一第二金属夹62与第一导电区域18连接。类似于第一金属夹34,第二金属夹62可以被弯折,以补偿电极60与导电区域18之间的高度差。
如图7所示,第二金属夹62可以在与第一金属夹34不同的方向上定向。第二金属夹62的与金属化层14连接的端部可以从半导体芯片26、50的叠层沿与第一金属夹34不同的方向延伸。在图7中,第一和第二金属夹34、62相对于彼此正交地定向。
返回图3,在第二金属夹62的结合至半导体芯片50的上部电极60的端部的顶部上,可以附接功率电子设备模块10的部件64。这样的部件64可以是端子,其在半导体芯片26、50的叠层正上方从功率电子设备模块10突出。部件64也可以是温度传感器或其它传感器。
如图4所示,另一衬底66可以结合在第二金属夹62的与半导体芯片50的上部电极60结合的端部的顶部上,该另一衬底66可以承载这样的部件64。该另一衬底66可以包括电绝缘芯部68和两个外部导电层70。例如,该另一衬底可以是印刷电路板或直接结合的铜衬底。
功率电子设备模块10的制造可以通过以下方式进行:
在第一步骤中,可以将半导体开关芯片26结合至衬底12,并且可以将第一金属夹34结合至半导体开关芯片26和导电区域16。
在第二步骤中,可以将第二半导体芯片50结合至第二金属夹62。或者,可以在接下来的第三步骤中将结合线61结合。
在第三步骤中,将烧结预成型件54放置在半导体开关芯片26上,并且将半导体芯片50任选地与第二金属夹62一起通过烧结工艺结合至半导体开关芯片26。
功率电子设备模块的结合界面之间的所有结合过程都可以通过Ag烧结来实现。为了允许良好的可制造性,第一和第二金属夹34、62可以在结合界面处具有预先施加的烧结膏。
图5和6示出了替代实施例,其中第二半导体芯片50被嵌入印刷电路板72中,印刷电路板72被附接在第一半导体芯片26的顶部上。
印刷电路板72具有多个金属化层34’、74、76、78、80。设置在印刷电路板72的塑料主体的底面上的金属化层34’在一端处结合至半导体开关芯片26的上部功率电极30,并且可以被看作导电板34’。金属化层34’在另一端结合至导电间隔件82,该导电间隔件82可以由铜块制成和/或结合至导电区域16。
金属化层34’具有开口38,金属化层76布置在开口38中,该金属化层76也设置在印刷电路板72的底面上。金属化层76利用通路(via)与金属化层74互连,金属化层74与金属化层76一起形成栅极导体40’。金属化层76结合至半导体芯片26的栅电极。
金属化层80也设置在印刷电路板72的底面上,并结合至另一导电间隔件84,该另一导电间隔件84可以由铜块制成和/或结合至导电区域18。半导体开关芯片50经由金属化层78和多个通路与金属化层34’和金属化层80互连。
图6示出了印刷电路板72的塑料主体还可以具有布置在开口38上方的开口86。可以引导结合至栅电极32的结合线88穿过两个开口38、86,结合线88的另一端可以结合至印刷电路板的顶面。在这里,结合线88可以例如利用通路与金属化层76互连。在这种情况下,栅极导体40’也可包括结合线88。
图7示出了具有两对由两个半导体芯片26、50组成的叠层的功率电子设备模块10,其可以如图3和4所示地设计。每对叠层并联连接并且形成半桥的一个臂。DC-端子20、AC端子22和DC+端子24提供与该半桥的互连。此外,功率电子设备模块10提供栅极端子90和辅助发射极端子92,它们对于每对并联的叠层均并排布置。
栅极端子90经由结合线与栅极导体衬底42连接,并且栅极信号经由导电区域16上方的栅极导体衬底42所提供的带状线以及第一金属夹34的端部被传导,此后栅极信号由在第一金属夹34上方延伸并进入开口38的结合线40传导。这导致低电感、低耦合和低占用空间。
虽然已在附图和前面的说明书中示出和详细描述了本发明,但这种图示和描述应该被认为是说明性的或示例性的而非限制性的;本发明并不限于所公开的实施例。通过研究附图、公开内容和所附权利要求,本领域中实施要求保护的发明的技术人员可以理解和实现所公开实施例的其它变型。在权利要求书中,用词“包括”不排除其它要素或步骤,并且不定冠词“一”或“一个”不排除多个。单个处理器或控制器或其它单元可实现在权利要求书中记载的多个项目的功能。在彼此不同的从属权利要求中记载特定措施的单纯事实并不表示这些措施的组合不能有利地使用。权利要求中的任何附图标记均不应被解释为限制保护范围。
附图标记列表
10 功率电子设备模块
12 衬底
14 金属化层
16 导电区域
18导电区域
20DC-端子
22AC端子
24DC+端子
26 半导体开关芯片
28 功率电极
30 功率电极
32 栅电极
34 第一金属夹
36 中间部分
38 开口
40栅极导体,结合线
42 栅极导体衬底
44 隔离中间层
46 导电层
48 栅极导体层
50 半导体芯片
52 功率电极
54 结合预成型件
56 金属芯部
58 结合层
60 功率电极
61 结合线
62 第二金属夹
64电气/电子部件
66 另一衬底
68 电隔离芯部
70 导电层
72印刷电路板
34’导体板,金属化层
40’栅极导体
74 金属化层
76 金属化层
78 金属化层
80 金属化层
82 导电间隔件
84 导电间隔件
86 开口
88 结合线
90 栅极端子
92 辅助发射极端子
Claims (7)
1.一种功率电子设备模块(10),包括:
具有衬底金属化层(14)的衬底(12),所述衬底金属化层被分成用于为所述功率电子设备模块(10)提供导电路径的多个导电区域(16,18);
半导体开关芯片(26),所述半导体开关芯片利用第一功率电极(28)结合至所述衬底金属化层(14)的第一导电区域(18);
导体板(34,34’),所述导体板结合至所述半导体开关芯片(26)的与所述第一功率电极(28)相对的第二功率电极(30);
栅极导体(40,40’),所述栅极导体结合至所述半导体开关芯片(26)的除所述第二功率电极(30)之外的栅电极(32);
其中,所述导体板(34,34’)延伸到所述衬底金属化层(14)的第二导电区域(16),并且所述栅极导体(40,40’)延伸穿过所述导体板(34,34’)中的布置在所述栅电极(32)上方的开口(38);
其中,所述栅极导体包括结合线(40);
其中,所述导体板是第一金属夹(34);
其中,结合预成型件(54)结合到所述第一金属夹(34)上;
其中,第二半导体芯片(50)利用第一功率电极(52)结合至所述结合预成型件(54)。
2.根据权利要求1所述的功率电子设备模块(10),
其中,所述导体板中的开口(38)是通孔。
3.根据权利要求1或2所述的功率电子设备模块(10),
其中,所述栅极导体(40,40’)在所述导体板(34,34’)上方延伸。
4.根据权利要求1或2所述的功率电子设备模块(10),
其中,所述第一金属夹(34)通过第一端结合至所述第二功率电极(30),并且所述第一金属夹(34)通过第二端结合至所述衬底金属化层(14)的第二导电区域(16);
其中,栅极导体衬底(42)附接到所述第一金属夹(34)的第二端,该栅极导体衬底(42)具有与所述结合线(40)结合的栅极金属化层(48)。
5.根据权利要求1或2所述的功率电子设备模块(10),
其中,所述结合预成型件(54)是具有金属材料芯部(56)和两个烧结材料外层(58)的烧结预成型件,所述两个烧结材料外层适于将所述第一金属夹(34)和所述第二半导体芯片(50)烧结至所述结合预成型件(54)。
6.根据权利要求1或2所述的功率电子设备模块(10),
其中,第二金属夹(62)结合至所述第二半导体芯片(50)的与所述第一功率电极(52)相对的第二功率电极(60);
其中,所述第二金属夹(62)结合至所述衬底金属化层(14)的所述第一导电区域(18)。
7.根据权利要求6所述的功率电子设备模块(10),
其中,具有金属化层(70)的顶部衬底(66)在所述第二半导体芯片(50)上方附接到所述第二金属夹(62)上;
其中,电气部件和电子部件(64)中的至少一者附接到所述第二金属夹(62)和所述顶部衬底(66)中的至少一者上。
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EP17166088.9A EP3389090A1 (en) | 2017-04-11 | 2017-04-11 | Power electronics module |
EP17166088.9 | 2017-04-11 | ||
PCT/EP2018/059347 WO2018189276A1 (en) | 2017-04-11 | 2018-04-11 | Power electronics module |
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CN110753996B true CN110753996B (zh) | 2023-06-02 |
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US (1) | US11183489B2 (zh) |
EP (2) | EP3389090A1 (zh) |
CN (1) | CN110753996B (zh) |
WO (1) | WO2018189276A1 (zh) |
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US11316438B2 (en) * | 2019-01-07 | 2022-04-26 | Delta Eletronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
DE102019126265B4 (de) * | 2019-09-30 | 2023-12-14 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Vorrichtung umfassend ein erstes Trägersubstrat und ein zweites Trägersubstrat, Kraftfahrzeug und Verfahren zur Herstellung einer Vorrichtung |
DE102021103050A1 (de) | 2021-02-10 | 2022-08-11 | Infineon Technologies Ag | Package mit einem Clip mit einem Durchgangsloch zur Aufnahme einer bauteilbezogenen Struktur |
US11842953B2 (en) | 2021-04-28 | 2023-12-12 | Infineon Technologies Ag | Semiconductor package with wire bond joints and related methods of manufacturing |
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JP2000164800A (ja) | 1998-11-30 | 2000-06-16 | Mitsubishi Electric Corp | 半導体モジュール |
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DE102005039478B4 (de) | 2005-08-18 | 2007-05-24 | Infineon Technologies Ag | Leistungshalbleiterbauteil mit Halbleiterchipstapel und Verfahren zur Herstellung desselben |
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2017
- 2017-04-11 EP EP17166088.9A patent/EP3389090A1/en not_active Withdrawn
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- 2018-04-11 US US16/603,667 patent/US11183489B2/en active Active
- 2018-04-11 EP EP18716294.6A patent/EP3610504A1/en active Pending
- 2018-04-11 CN CN201880038531.6A patent/CN110753996B/zh active Active
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EP0513410A1 (de) * | 1991-05-15 | 1992-11-19 | IXYS Semiconductor GmbH | Leistungshalbleitermodul und Verfahren zur Herstellung eines solchen Moduls |
DE102012204159A1 (de) * | 2012-03-16 | 2013-03-14 | Continental Automotive Gmbh | Leistungshalbleitermodul und Verfahren zur Herstellung desselben |
CN205984938U (zh) * | 2015-07-24 | 2017-02-22 | 半导体元件工业有限责任公司 | 半导体组件 |
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WO2018189276A1 (en) | 2018-10-18 |
EP3610504A1 (en) | 2020-02-19 |
EP3389090A1 (en) | 2018-10-17 |
US20210091054A1 (en) | 2021-03-25 |
US11183489B2 (en) | 2021-11-23 |
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