CN113711351A - 具有激光焊接的引线框的功率半导体模块 - Google Patents

具有激光焊接的引线框的功率半导体模块 Download PDF

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CN113711351A
CN113711351A CN202080029019.2A CN202080029019A CN113711351A CN 113711351 A CN113711351 A CN 113711351A CN 202080029019 A CN202080029019 A CN 202080029019A CN 113711351 A CN113711351 A CN 113711351A
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control
lead frame
semiconductor module
power semiconductor
power
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CN113711351B (zh
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N·帕利克
F.莫恩
M·图特
S·柯尼格
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Hitachi Energy Co ltd
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Hitachi Energy Switzerland AG
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Abstract

一种功率半导体模块(10)包括具有结构化金属化层(22)的衬底(12)；利用第一功率电极(38)结合到金属化层(22)的半导体芯片(14)；引线框(16，18)，该引线框被激光焊接到所述半导体芯片(14)的组(36a，36b)的第二电极(40)，用于电互连半导体芯片(14)；控制导体(52)，该控制导体(52)附接到与半导体芯片(14)相对的引线框(16，18)并且与引线框(16，18)电隔离。控制导体(52)电连接到组(36a，36b)中的半导体芯片(14)的控制电极(58)。

Description

具有激光焊接的引线框的功率半导体模块
技术领域
本发明涉及一种功率半导体模块。
背景技术
功率半导体模块中通常使用的半导体芯片(诸如IGBT、MOSFET、二极管等)是垂直器件。电流从顶侧源极/发射极触点垂直流向底侧漏极/集电极触点。芯片的底侧的整个区域被结合(例如焊接或烧结)到金属层(例如陶瓷衬底的顶部金属化层)。顶侧连接通常通过大量粗引线结合来实现。
最近的发展集中于用由SiC或GaN制成的宽带隙器件代替Si器件，因为在最小化开关损耗和/或增加开关频率方面有有益的性质。此外，电流密度增加，并且较少的芯片面积可用于容纳给定电流所需数量的引线结合。
引线结合技术在电流能力方面可能达到其极限。这已经引发了从Al引线转变到Cu引线以确保可靠结合。尽管如此，新型功率半导体开关的不断增加的电流密度可能需要优越的顶侧连接。
另外，大量的粗结合线可能限制每台引线结合机装备的制造产量，并可能导致引线结合工具的显著磨损。此外，具有大量引线结合的功率半导体模块的可靠性可能被限制，因为引线结合故障(诸如剥离、跟部断裂等)属于主要故障机制。
US 2018 090 338A1描述了一种具有焊接到结合到芯片的应力缓冲层的引线框的功率半导体模块。
US 2014/217 600A1涉及半导体模块的制造，该半导体模块具有结合到加热体的几个半导体芯片。
DE 10 2012 222 791A1示出了一种具有接触元件的半导体模块，该接触元件通过烧结层激光焊接到功率半导体芯片。
JP 2013 105 789A示出了具有电接触元件的半导体模块，该电接触元件结合到两个半导体芯片，并且柔性电路板附接到该电接触元件。
发明内容
本发明的目的是提供一种可靠且容易且快速地制造具有高电流密度的功率半导体模块。
这个目的通过独立权利要求的主题来实现。从从属权利要求和以下描述中，另外的示例性实施例是显而易见的。
本发明涉及一种功率半导体模块。功率半导体模块可以是包括功率半导体芯片、它们的电互连件、端子和支撑所有这些部件的机械结构的组件。功率半导体模块可以包括外壳和从外壳突出的端子。例如，以上提及的零件可以装入由聚合物材料制成的外壳中。
在此和下文中的术语“功率”可以涉及模块、芯片和/或器件，其适于处理大于100V(例如大于100V)、和/或大于1A(例如大于10A)的电压。
功率半导体芯片可以是和/或可以提供一个或多个半导体器件，诸如晶体管、晶闸管和/或二极管，特别是IGBT、IGCT和/或MOSFET。一些或所有功率半导体芯片可以是功率半导体开关。功率半导体芯片可以由Si和/或由宽带隙材料制成，诸如SiC、GaN等。
根据本发明的实施例，功率半导体模块包括具有结构化金属化层的衬底和利用第一功率电极结合到金属化层的多个半导体芯片。衬底可以包括例如由陶瓷制成的隔离层和可以由诸如Cu的金属制成的金属化层。金属化层可以被结构化，即被分成在隔离层上电断开(但是可以通过另外的导体电连接)的区域。
半导体芯片可以被烧结和/或钎焊到金属化层。第一功率电极(诸如漏极、源极、集电极或发射极)可以覆盖半导体芯片的面向金属化层的整个侧面。
根据本发明的实施例，功率半导体模块包括引线框，该引线框被激光焊接到半导体芯片组的第二电极，用于电互连半导体芯片。引线框可以是金属板，例如由Al、Cu等和/或由片状金属制成。第二功率电极(诸如漏极、源极、集电极或发射极)以及控制电极(诸如栅极)可以覆盖半导体芯片的与金属化层相反的整个侧面。引线框可以仅覆盖第二功率电极。可以利用激光束将其激光焊接到第二功率电极上，该激光束指向引线框的背离功率半导体芯片的侧面。激光焊缝可以是圆形、线形和/或点形和/或它们的组合。
该半导体芯片的组可以经由衬底的金属化层和引线框与它们的功率电极平行。
必须注意，功率半导体模块可以包括一个以上的激光焊接引线框。一个或多个引线框可以用作顶侧源极和/或发射极连接。单个引线框可以连接所有平行的半导体芯片。
根据本发明的实施例，功率半导体模块包括控制导体，该控制导体附接到与半导体芯片相对的引线框并与引线框电隔离，其中控制导体电连接到该半导体芯片的组中的控制电极，并且控制导体被激光焊接到控制电极中的至少一个。控制导体可以将诸如栅极信号的控制信号引导到功率半导体芯片。控制导体可以包括与引线框电绝缘的一个或多个金属化层和/或一条或多条引线。例如，在控制导体和引线框之间提供电绝缘材料。
当例如以柔性电路板的金属层或衬底的形式的控制导体在控制电极上方被引导时，它可以被激光焊接到控制电极。
必须注意的是，控制导体也可以用于路由其他辅助信号(诸如辅助源极连接)和/或来自传感器的信号。呈一个或多个控制导体的形式的信号连接可以在引线框的顶部上在附加层中被引导。
一个或多个引线框可以实现高可靠性和低成本的功率模块。一个或多个引线框可以精确地放置在功率模块衬底上的半导体芯片上，并通过聚焦激光束进行焊接。基于引线框的顶侧连接可以代替大量的粗引线结合。这种引线框也可以直接充当功率端子。
另外，由于衬底面积可以被减小，完全组装的功率半导体模块(包括模塑封装或外壳)的占地面积在其大小方面又可以减小大约一半。附加地，这可以模塑料或外壳的成本节省。
可以减少制造步骤的数量，因为例如可以省略顶部衬底与主衬底的结合、后续的清洁步骤以及至少一些端子结合。功率半导体模块的可靠性可以增加，因为引线结合的主要故障源可以减轻。最后，可以存在通过多层共面电流布线(例如通过堆叠引线框)实现的附加设计自由度和/或改善的电气特性。
根据本发明的实施例，功率半导体模块还包括附接到引线框的柔性电路板，其中控制导体至少部分地由柔性电路板的金属层提供。柔性电路板可以包括柔性隔离层和金属层。柔性电路和/或预制电路可以结合(诸如层压、胶合、焊接等)到引线框上。它可以是完全结合的，或者在引线框的离散点上结合。该至少一个金属层可以提供导电轨迹，其可以用作一个或多个控制导体。
根据本发明的实施例，功率半导体模块还包括附接到引线框的电绝缘引线，其中控制导体至少部分地由电绝缘引线的金属芯提供。除了柔性电路板或作为柔性电路板的替代，一个或多个绝缘引线可以附接(诸如胶合)到引线框。一个或多个绝缘引线可以具有同轴设计，也就是说，可以在隔离件内具有导电软管用于屏蔽用于路由控制信号的中心引线。
根据本发明的实施例，功率半导体模块还包括具有附接到引线框的电绝缘层的控制衬底，其中控制导体至少部分地由控制衬底的金属化层提供。除了柔性电路板和/或一个或多个绝缘引线之外或作为其替代，控制衬底可以被结合(诸如胶合、钎焊等)到引线框。控制衬底可以是陶瓷衬底(诸如直接覆铜DBC和/或活性金属支撑AMB)和/或绝缘金属衬底IMS。
根据本发明的实施例，控制导体经由引线结合与控制电极中的至少一个连接。可以使用一个或多个引线结合。引线结合可以补偿栅极电极的顶侧和引线框上方的控制导体的不同水平。
根据本发明的实施例，控制导体是控制衬底或柔性电路板的一部分，其在至少一个控制电极处突出于引线框。可能的是控制导体可以在控制电极上方被引导，使得它可以直接连接到控制电极。
根据本发明的实施例，控制导体可以利用通孔与控制电极中的至少一个电连接。控制导体可以结合(诸如钎焊或烧结)到控制电极。
根据本发明的实施例，栅极导体和辅助导体与半导体芯片相对地附接到引线框，并且与引线框电隔离。可以在引线框上提供呈栅极导体和辅助导体的形式的两个控制导体。辅助导体可以是辅助源极连接。
根据本发明的实施例，在栅极导体的两侧上提供辅助导体的两个条带。以这种方式，可以实现栅极导体和辅助导体的同轴布置，以最小化栅极环路电感。
根据本发明的实施例，引线框激光被焊接到的半导体芯片的第二功率电极包括结合到半导体芯片的金属缓冲板。缓冲板可以由Cu或其他可焊接的金属制成。缓冲板可以被结合(诸如钎焊或烧结)到半导体芯片的有源区。引线框可以激光焊接到缓冲板上。
缓冲板可以促进激光焊接而不损坏半导体芯片的有源区，因为半导体芯片的有源区金属化可能太薄而不能适应稳定的激光焊接。一般而言，一个或多个导电缓冲板可以结合到芯片顶面上，以便能够在源极焊盘或发射极焊盘上进行激光焊接。
控制电极也可以包括这种金属缓冲板。引线结合可以附接到缓冲板。控制导体可以激光焊接到缓冲板。
根据本发明的实施例，金属缓冲板包括两层不同的金属材料，诸如Mo和Cu。可以使用不同材料的多个缓冲板的堆叠(诸如半导体芯片上的Mo板和Mo板的顶部上的Cu板)以提供可焊接的表面。
根据本发明的实施例，引线框提供功率半导体模块的功率端子，其从功率半导体模块的外壳突出。可能的是引线框的部分可能被用作外部端子。外壳可以是模塑封装，并且引线框的一部分可以从模塑封装突出。
根据本发明的实施例，控制端子在与引线框相同的水平处从外壳突出。控制端子由与引线框相同的材料并且以与引线框相同的厚度制成。控制端子可以由与互连半导体芯片的引线框相同的引线框预制件制成。控制端子和引线框可以在制造期间在外壳的外部互连，其中在提供外壳之后移除互连。
根据本发明的实施例，控制端子与外壳内部的控制导体电互连。这可以通过引线结合和/或经由将控制导体激光焊接到控制端子来完成。
一般而言，一个或多个附加端子可以链接到引线框，其中在随后的生产步骤中移除(诸如切割和/或修整)链接。
根据本发明的实施例，半导体芯片被布置在至少一个行中，其中引线框包括沿着该行行进的中心部分和在该行的半导体芯片上从中心部分突出的分支部分。可以形成功率半导体模块的单个开关的并联连接的半导体芯片可以布置在一个或多个行中。引线框可以包括纵向中心部分，其可以在要连接的半导体芯片的行之间行进。每个分支部分可以从中心部分行进到相应半导体芯片上的位置。一般而言，引线框可以是树状的。
控制导体可以设置在中心部分和分支部分上，和/或也可以是树形的。
根据本发明的实施例，分支部分朝向半导体芯片弯曲。引线框的中心部分可以在比分支部分的端部在更高的水平上。中心部分可以比分支部分的端部距衬底更远。
根据本发明的实施例，引线框包括外围部分，该外围部分附接到分支部分的端部并且平行于中心部分行进。这种引线框可以互连半导体芯片行，这些半导体芯片行相比于在树形引线框的情况距离彼此更远。可以看到这种引线框具有网格形形式。外围部分可以将与中心部分同轴的电流引导朝向端子。在这种情况下，控制导体可以设置在外围部分上。中心部分可以比外围部分距衬底更远。
根据本发明的实施例，功率半导体模块形成半桥，并且第一组半导体芯片利用其功率电极并联电连接以形成低侧开关，并且第二组半导体开关利用其功率电极并联电连接以形成高侧开关。第一组和第二组中的每一组可以设置在两行半导体芯片中，这两行半导体芯片可以利用树形引线框和/或网格形引线框互连。
第一引线框可以激光焊接到第一组半导体芯片的第二电极，并且第二引线框可以激光焊接到第二组半导体芯片的第二电极。
根据本发明的实施例，第一组的半导体芯片沿着功率半导体模块的中心线以行的形式布置，并且第二组的半导体芯片在第一组的两侧处在第一组的外侧以两行的形式布置。可以是树形的第一引线框可以布置在功率半导体模块的衬底和可以是网格形的第二引线框之间。
参考下文描述的实施例，本发明的这些和其他方面将变得显而易见并得以阐明。
附图说明
本发明的主题将在下文中参考附图中示出的示例性实施例更详细地进行解释。
图1示出了功率半导体模块的透视图。
图2示出了图1的功率半导体模块的侧视图。
图3示出了图1的功率半导体模块的截面图。
图4示出了图1的功率半导体模块的树形引线框。
图5示出了图1的功率半导体模块的网格形引线框。
图6示出了根据本发明的实施例的功率半导体模块的部分横截面。
图7示出了功率半导体模块的局部俯视图。
附图中使用的附图标记及其含义在附图标记列表中以概述形式列出。原则上，在附图中相同的部分提供有相同的附图标记。
具体实施方式
图1示出了功率半导体模块10的透视图，其包括衬底12、结合到衬底12的半导体芯片14和两个引线框16、18，这两个引线框在半导体芯片14顶侧上将半导体芯片14电互连。
半导体模块也在图2和图3中以侧视图和截面图示出。可以看到的是，衬底12包括绝缘层20和在绝缘层20两侧上的两个金属化层22、24。绝缘层20可以由陶瓷制成。金属化层22、24可以由Cu制成。
如图1所示，顶侧(即面向半导体芯片14的侧面)上的金属化层22被结构化，即被分成几个断开的区域26、28、30。区域26是DC+区域，并且区域28是AC区域。区域30a、30b、30c、30d可以用作辅助源极、低侧栅极、高侧辅助源极和高侧栅极。区域26的部分32可以用作高侧辅助漏极。区域30e可以用作用于温度传感器的端子。
半导体芯片14结合到金属化层22的相应区域26、28，并通过引线框16、18连接以形成半桥。半导体芯片14被布置在四个平行的行34a、34b、34c、34d中。行34a、34b形成并联连接的半导体芯片14的第一组36a，其提供半桥的低侧开关。行34c、34d形成并联连接的半导体芯片14的第一组36a，其提供半桥的高侧开关。
半导体芯片14在其底侧上提供第一功率电极38，并且在其顶侧上提供第二功率电极40。
行34c、34d的芯片14的底侧功率电极38连接到DC+区域26，在模块10的操作期间该区域处于DC+电位。行34c、34d的芯片14的顶侧功率电极40连接到引线框18，该引线框也连接到AC区域28。在模块10的操作期间，引线框18和AC区域28处于AC电位。行34a、34b的芯片14的底侧功率电极38连接到AC区域28。行34a、34a的芯片14的顶侧功率电极40连接到引线框16，该引线框在模块10的操作期间处于DC-电位。
可以由片状金属和/或Cu制成的引线框16、18被激光焊接到顶侧电极40。如图3所示，顶侧电极40可以包括缓冲板42，该缓冲板结合到半导体芯片14的有源区。引线框16、18然后可以焊接到缓冲板42，该缓冲板可以由金属(诸如CU和/或Mo)制成。
如图1所示，柔性电路板44、46附接到引线框16、18中的每一个的顶侧。柔性电路板44、46中的每一个包括附接到相应引线框16、18的绝缘基层48和在基层48的顶部上的导电层50(参见图3)。基层48可以由柔性塑料材料和/或箔制成。可以由Cu制成的导电层50被分成断开的区域，这些区域中的每一个为模块10提供控制导体52、54。
同样如图4和图5所示，层50的内部区域52提供了栅极导体52。内部区域/栅极导体52用于栅极信号分配。围绕内部区域52的外部区域54提供用于辅助源极电位的导体54。为了最小化栅极环路电感，内部区域52被引导在外部区域52的两条迹线和/或条带之间。也可能的是，诸如区域52或区域54的仅一个区域用于传导控制信号。
回到图1，栅极导体52可以经由引线结合56与相应功率半导体芯片14的相应控制电极58连接。另外的引线结合60可以用于将栅极导体52分别连接到端子区域30c、30b。
辅助导体54可以经由引线结合62与相应功率半导体芯片14的功率电极40连接。另外的引线结合64可以用于将辅助导体54分别连接到端子区域30d、30a。
栅极导体52和/或辅助导体54的尺寸可以根据需求(例如是否需要每芯片的栅极电阻器)进行调整。引线框16、18的将被激光焊接到功率半导体芯片14的区域可以没有柔性电路板44、46。
图4更详细地示出了树形引线框16。引线框16具有纵向中心部分66，其在半导体芯片14的两个内部行34a、34b之间沿着模块10的中心行进。在一个端部处，功率端子68连接到中心部分66，该功率端子也由引线框16的材料制成。在另一端部处，中心部分66被扭结，使得在其顶部的柔性电路板44被引导朝向端子区域30b(参见图1)。半导体模块10可以具有模制的封装，并且只有端子68的一部分可以从封装突出。
引线框16还包括分支部分70，该分支部分从中心部分66基本正交地分支。分支部分70的端部在内部行34的功率半导体芯片14上方对齐。另外，分支部分70朝向半导体芯片14弯曲，使得中心部分66处于比分支部分70的端部更高的水平处。
引线框16上的柔性电路板44沿着中心部分和分支部分70行进，并且也是树形的。
图5更详细地示出了网格形引线框18。如引线框16，引线框18具有中心部分66、功率端子68’和分支部分70。当引线框18在模块10中时，功率端子68’相对于引线框16的功率端子68布置在模块10的相对侧上。
引线框18还提供AC区域连接72，该AC区域连接72被连接到分支部分70并且朝向AC区域28向下弯曲。引线框18可以经由AC区域连接72激光焊接到AC区域28。
引线框18附加地具有两个纵向外围部分74，它们平行于中心部分66行进并连接到分支部分70。外围部分74处于比中心部分66更低的水平处。外围部分74被定位在半导体芯片14的外部行34c、34d的顶部上。引线框18经由外围部分74与功率半导体芯片14焊接在一起。
引线框16上的柔性电路板46还沿着除了功率端子68’之外的外围部分74和分支部分70行进。柔性电路板46是U形的。
功率半导体模块10可以如下制造。
在第一步骤中，半导体芯片14可以结合到衬底12。在这个步骤中，缓冲板42也可以结合到半导体芯片14。
在第二步骤中，第一引线框16可以被激光焊接到行34a、34b中半导体芯片的第一组36a。此后，栅极导体52可以引线结合到相应的栅极电极/控制电极58。而且，辅助源极导体54可以引线结合到相应的第二电极40。
在第三步骤中，第二引线框16可以被激光焊接到行34c、34d中半导体芯片的第二组36b。然后，第一引线框16被夹在衬底12和第二引线框18之间。第二引线框18的栅极导体52可以引线结合到相应的栅极电极/控制电极58。而且，第二引线框18的辅助源极导体54可以引线结合到相应的第二电极40。
根据引线框16、18的具体布局，替代性的制造顺序是可能的。例如，可能的是当第二引线框18被设计成使得半导体芯片14的第一组36a的顶侧保持可接近时，可以分别合并两个激光焊接步骤和两个引线结合步骤。
图6示出了功率半导体模块10的部分横截面，其中缓冲板42具有多于一个层76、78。层76、78可以是不同材料(诸如Mo和Cu)的金属层。
功率半导体芯片14可以包括半导体衬底上的有源电极区域80，诸如Mo层的第一层76结合(例如钎焊或烧结)到该有源电极区域80。诸如Cu层的第二层78被结合到第一层76和/或引线框16、18被激光焊接到第二层78。图6示出了行进穿过引线框16、18和第二层78的激光焊接82。可能的是，激光焊接82在第一层76之前停止。
图6示出了另外的实施例，柔性电路板44、46可以如何电连接到半导体芯片14。柔性电路板44、46从引线框16、16的边缘突出和/或延伸。柔性电路板44、46可以位于栅极电极/控制电极58上，并且栅极/控制导体52可以直接结合到栅极/控制电极58，例如通过焊接、激光焊接、钎焊等。可能的是柔性电路板44、46在栅极/控制导体52和栅极/控制电极58之间具有通孔。
必须注意，辅助导体54到电极40的电连接也可以以这种方式进行。
可能的是，将另外的缓冲板42’结合到栅极/控制电极58的有源区域80’，该缓冲板42’也可以具有两个层76’、78’，这两层可以被制成缓冲板42的层。
图7示出了功率半导体模块10的局部俯视图，其中几个端子68’、30’由相同的引线框预成型件84制成。引线框18可以经由桥86与端子30’连接，该端子30’可以是栅极端子。在附接到模块10之后，可以通过移除桥86来断开引线框18和端子30’。特别地，模块10可以包括由虚线指示的模制外壳88。引线框18和端子30’可以部分地模制到外壳88中，该外壳可以是模塑封装。
相同的构思可以应用于其他类型的端子、应用于与其他类型的端子结合的引线框16和/或应用于两个引线框16、18，也就是说，引线框16、18可以结合在一个预制件84中、可以一起附接到模块10、并且可以通过在模制外壳之后移除桥86而断开。
图7还示出了控制导体52可以由具有附接到引线框18的电绝缘层92的控制衬底90提供。控制导体52可以由控制衬底90上的金属化层50提供，该控制衬底可以是DBC、AMD或IMS衬底。
控制导体52也可以由隔离的线缆或引线94提供，该线缆或引线94可以附接在引线框18上方和/或可以在其上方行进。这个线缆或引线94可以是同轴线缆。
必须注意的是，控制导体54也可以被提供为这样的隔离线缆或引线94，和/或控制导体54可以被提供为控制衬底90上的金属化层50。
虽然本发明已经在附图和前面的描述中详细示出和描述，但是这种示出和描述被认为是说明性的或示例性的，而不是限制性的；本发明不限于公开的实施例。根据对附图、公开内容和所附权利要求的研究，本领域中的和实践所要求保护的发明的技术人员人可以理解和实现所公开的实施例的其他变化。在权利要求中，词语“包含”不排除其它元件或步骤，并且不定冠词“一”或“一个”不排除多个。单个处理器或控制器或其他单元可以实现权利要求中列举的几个项的功能。在相互不同的从属权利要求中引用某些措施的事实并不指示这些措施的组合不能被有利地使用。权利要求中的任何附图标记不应被解释为限制范围。
附图标记列表
10功率半导体模块
12衬底
14半导体芯片
16第一引线框
18第二引线框
20绝缘层
22金属化层
24金属化层
26DC+区域
28AC区域
30，30’端子区域
30a低侧辅助源极区域
30b低侧栅极区域
30c高侧辅助源极区域
30d高侧栅极区域
30e温度传感器区域
32高侧辅助漏极部分
34a第一行
34b第二行
34c第三行
34d第四行
36a第一组
36b第二组
38第一功率电极
40第二功率电极
42，42’缓冲板
44第一柔性电路板
46第二柔性电路板
48绝缘基层
50导电层
52栅极/控制导体
54辅助/源极/控制导体
56引线结合
58控制电极
60引线结合
62引线结合
64引线结合
66中心部分
68，68’功率端子
70中心部分
72 AC区域连接
74外围部分
76，76’第一层
78，78’第二层
80有源电极区域
82激光焊接
84引线框预制件
86桥
88外壳
90控制衬底
92电绝缘层
94被隔离的线缆或引线

Claims (15)

1.一种功率半导体模块(10)，包括：
具有结构化金属化层(22)的衬底(12)；
利用第一功率电极(38)结合到所述金属化层(22)的半导体芯片(14)；
引线框(16，18)，所述引线框(16，18)被激光焊接到所述半导体芯片(14)的组(36a，36b)的第二电极(40)，用于电互连所述半导体芯片(14)；
控制导体(52)，所述控制导体(52)与所述半导体芯片(14)相对地附接到所述引线框(16，18)并且与所述引线框(16，18)电隔离；
其中，所述控制导体(52)电连接到所述组(36a，36b)中的所述半导体芯片(14)的控制电极(58)，并且所述控制导体(52)被激光焊接到所述控制电极(58)中的至少一个。
2.根据权利要求1所述的功率半导体模块(10)，还包括：
柔性电路板(44，46)，所述柔性电路板(44，46)附接到所述引线框(16，18)；
其中所述控制导体(52)至少部分地由所述柔性电路板(44，46)的金属层(50)提供。
3.根据权利要求1或2所述的功率半导体模块(10)，还包括：
电绝缘引线(94)，所述电绝缘引线(94)附接到所述引线框(16，18)；
其中，所述控制导体(52)至少部分地由所述电绝缘引线(94)的金属芯提供。
4.根据前述权利要求中任一项所述的功率半导体模块(10)，还包括：
控制衬底(90)，所述控制衬底(90)具有附接到所述引线框(16，18)的电绝缘层(50)；
其中，所述控制导体(52)至少部分地由所述控制衬底(90)的金属化层(50)提供。
5.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，所述控制导体(52)经由引线结合(56)与所述控制电极(58)中的至少一个连接。
6.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，所述控制导体(52)是控制衬底(90)或柔性电路板(44，46)的一部分，所述控制导体(52)在所述控制电极(58)处突出于所述引线框(16，18)。
7.根据权利要求6所述的功率半导体模块(10)，其中所述控制导体(52)通过通孔与所述控制电极(58)中的至少一个电连接。
8.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，栅极导体(52)和辅助导体(54)与所述半导体芯片(14)的组相对地附接到所述引线框(16，18)并且与所述引线框(16，18)电隔离；
其中在栅极导体(52)的两侧上提供所述辅助导体(54)的两个条带。
9.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，所述引线框(16，18)被激光焊接到的所述半导体芯片(10)的第二功率电极(40)包括结合到所述半导体芯片(14)的金属缓冲板(42)；
其中，所述引线框(16，18)被激光焊接到所述缓冲板(42)。
10.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中所述引线框(16，18)提供所述功率半导体模块(10)的功率端子(68，68’)，所述功率端子(68，68’)从所述功率半导体模块(10)的外壳(88)突出。
11.根据权利要求10所述的功率半导体模块(10)，
其中，控制端子(30’)在与所述引线框(16，18)相同的水平处从所述外壳(88)突出，所述控制端子(30’)由与所述引线框(16，18)相同的材料并且以与所述引线框(16，18)相同的厚度制成；
其中，所述控制端子(30’)在所述外壳(88)内部与所述控制导体(52)电互连。
12.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，所述半导体芯片(14)布置在至少一行(34a-34d)中；
其中，所述引线框(16，18)包括沿着所述行行进的中心部分(66)和分支部分(70)，所述分支部分(70)在所述半导体芯片(14)的行(34a-34d)的上方从所述中心部分(66)突出。
13.根据权利要求12所述的功率半导体模块(10)，
其中，所述分支部分(70)朝向半导体芯片(14)弯曲。
14.根据前述权利要求中任一项所述的功率半导体模块(10)，
其中，所述功率半导体模块(10)形成半桥，并且第一组(36a)半导体芯片(14)利用其功率电极(38，40)并联电连接以形成低侧开关，并且第二组(36b)半导体开关(14)利用其功率电极(38，40)并联电连接以形成高侧开关；
其中，第一引线框(16)被激光焊接到所述第一组(36a)半导体芯片(14)的第二电极(40)；
其中，第二引线框(18)被激光焊接到所述第二组(36b)半导体芯片(14)的第二电极(40)。
15.根据权利要求14所述的功率半导体模块(10)，
其中，所述第一组(36a)半导体芯片(14)沿着所述功率半导体模块(10)的中心线以行(34a，34b)的形式布置；
其中，所述第二组(36b)半导体芯片(14)在所述第一组(36a)的两侧处以在所述第一组(36a)的外侧两行(34c，34d)的形式布置；
其中，所述第一引线框(16)布置在所述功率半导体模块(10)的衬底(12)和所述第二引线框(18)之间。
CN202080029019.2A 2019-04-18 2020-03-12 具有激光焊接的引线框的功率半导体模块 Active CN113711351B (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115910985A (zh) * 2022-11-10 2023-04-04 北京智慧能源研究院 一种功率半导体模块
CN117525010A (zh) * 2024-01-05 2024-02-06 苏州博创集成电路设计有限公司 一种集成封装的低侧开关芯片及低侧开关装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4068915A1 (en) * 2021-03-30 2022-10-05 Hitachi Energy Switzerland AG Power module and method for manufacturing a power module
DE102021110607A1 (de) * 2021-04-26 2022-10-27 Semikron Elektronik Gmbh & Co. Kg Gerät mit Funktionskomponente und Kunststoffgehäuseelement und Verfahren zur Überprüfung der Echtheit eines solches Geräts
FR3140224A1 (fr) * 2022-09-28 2024-03-29 Valeo Equipements Electriques Moteur Module de puissance

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009235A (zh) * 2006-01-24 2007-08-01 恩益禧电子股份有限公司 半导体装置制造方法
JP2013105789A (ja) * 2011-11-10 2013-05-30 Sumitomo Electric Ind Ltd 配線シート付き配線体、半導体装置、およびその半導体装置の製造方法
EP2743973A2 (de) * 2012-12-11 2014-06-18 Robert Bosch Gmbh Verfahren zur Kontaktierung eines Halbleiterelements mittels Schweißens eines Kontaktelements an eine Sinterschicht auf dem Halbleiterelement und Halbleiterbauelement mit erhöhter Stabilität gegenüber thermomechanischen Einflüssen
CN103972277A (zh) * 2013-02-06 2014-08-06 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4294405B2 (ja) * 2003-07-31 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US7960817B2 (en) 2007-09-05 2011-06-14 Delphi Technologies, Inc. Semiconductor power module with flexible circuit leadframe
US7759778B2 (en) 2008-09-15 2010-07-20 Delphi Technologies, Inc. Leaded semiconductor power module with direct bonding and double sided cooling
US11469205B2 (en) * 2013-03-09 2022-10-11 Adventive International Ltd. Universal surface-mount semiconductor package
JP2015023211A (ja) 2013-07-22 2015-02-02 ローム株式会社 パワーモジュールおよびその製造方法
JP6475918B2 (ja) 2014-02-05 2019-02-27 ローム株式会社 パワーモジュール
JP6338937B2 (ja) 2014-06-13 2018-06-06 ローム株式会社 パワーモジュールおよびその製造方法
US9240370B1 (en) 2014-12-15 2016-01-19 Industrial Technology Research Institute Power module
EP3104507A1 (en) 2015-06-12 2016-12-14 ABB Technology AG Terminal arrangement for a power semiconductor module
US9620440B1 (en) 2016-02-25 2017-04-11 Texas Instruments Incorporated Power module packaging with dual side cooling
EP3545550B1 (en) 2016-11-23 2021-02-17 ABB Schweiz AG Manufacturing of a power semiconductor module
JP6747304B2 (ja) * 2017-01-16 2020-08-26 三菱電機株式会社 電力用半導体装置
US11127603B2 (en) * 2017-09-04 2021-09-21 Mitsubishi Electric Corporation Semiconductor module and power conversion device
JP6998826B2 (ja) * 2018-04-27 2022-01-18 ルネサスエレクトロニクス株式会社 電子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009235A (zh) * 2006-01-24 2007-08-01 恩益禧电子股份有限公司 半导体装置制造方法
JP2013105789A (ja) * 2011-11-10 2013-05-30 Sumitomo Electric Ind Ltd 配線シート付き配線体、半導体装置、およびその半導体装置の製造方法
EP2743973A2 (de) * 2012-12-11 2014-06-18 Robert Bosch Gmbh Verfahren zur Kontaktierung eines Halbleiterelements mittels Schweißens eines Kontaktelements an eine Sinterschicht auf dem Halbleiterelement und Halbleiterbauelement mit erhöhter Stabilität gegenüber thermomechanischen Einflüssen
CN103972277A (zh) * 2013-02-06 2014-08-06 三菱电机株式会社 半导体装置及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115910985A (zh) * 2022-11-10 2023-04-04 北京智慧能源研究院 一种功率半导体模块
CN115910985B (zh) * 2022-11-10 2023-10-27 北京智慧能源研究院 一种功率半导体模块
CN117525010A (zh) * 2024-01-05 2024-02-06 苏州博创集成电路设计有限公司 一种集成封装的低侧开关芯片及低侧开关装置
CN117525010B (zh) * 2024-01-05 2024-03-19 苏州博创集成电路设计有限公司 一种集成封装的低侧开关芯片及低侧开关装置

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