JP2022529965A - レーザ溶接のリードフレームを備えた電力半導体モジュール - Google Patents
レーザ溶接のリードフレームを備えた電力半導体モジュール Download PDFInfo
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- JP2022529965A JP2022529965A JP2021561814A JP2021561814A JP2022529965A JP 2022529965 A JP2022529965 A JP 2022529965A JP 2021561814 A JP2021561814 A JP 2021561814A JP 2021561814 A JP2021561814 A JP 2021561814A JP 2022529965 A JP2022529965 A JP 2022529965A
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- lead frame
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- semiconductor module
- power
- power semiconductor
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Abstract
Description
本発明は、電力半導体モジュールに関する。
一般的に、電力半導体モジュールに使用されている半導体チップ(例えば、IGBT、MOSFETおよびダイオード)は、縦型デバイスである。電流は、上下方向に沿って、上面のソース/エミッタコンタクトから底面のドレイン/コレクタコンタクトに流れる。チップ底面の全体は、金属層(例えば、セラミック基板の上面の金属被覆層)に接合(例えば、はんだ付けまたは焼結)される。この上面接続は、通常、多くの厚いワイヤボンドによって実現される。
本発明の目的は、高電流密度の電力半導体モジュールを確実且つ容易且つ迅速に製造することを提供することにある。
図面に使用された参照記号およびその意味は、参照記号のリストに概略に記載されている。原則的には、図面において、同じ部品は、同じ参照記号で示される。
第1のステップにおいて、半導体チップ14を基板12に接合してもよい。このステップにおいて、バッファプレート42を半導体チップ14に接合してもよい。
10 電力半導体モジュール、12 基板、14 半導体チップ、16 第1のリードフレーム、18 第2のリードフレーム、20 絶縁層、22 金属被覆層、24 金属被覆層、26 DC+領域、28 AC領域、30,30′ 端子領域、30a ローサイド補助ソース領域、30b ローサイドゲート領域、30c ハイサイド補助ソース領域、30d ハイサイドゲート領域、30e 温度センサ領域、32 ハイサイド補助ドレイン部、34a 第1列、34b 第2列、34c 第3列、34d 第4列、36a 第1組、36b 第2組、38 第1の電力電極、40 第2の電力電極、42,42′ バッファプレート、44 第1の可撓性回路基板、46 第2の可撓性回路基板、48 ベース絶縁層、50 導電層、52 ゲート/制御導体、54 補助/ソース/制御導体、56 ワイヤボンド、58 制御電極、60 ワイヤボンド、62 ワイヤボンド、64 ワイヤボンド、66 中央部、68,68′ 電力端子、70 分岐部、72 AC領域接続、74 周辺部、76,76′ 第1の層、78,78′ 第2の層、80 活性電極領域、82 レーザ溶接、84 リードフレームプリフォーム、86 ブリッジ、88 ハウジング、90 制御基板、92 電気絶縁層、94 電気絶縁ケーブルまたはワイヤ。
Claims (15)
- 電力半導体モジュール(10)であって、
構造化された金属被覆層(22)を含む基板(12)と、
第1の電力電極(38)を介して前記金属被覆層(22)に接合された半導体チップ(14)と、
一組(36a,36b)の前記半導体チップ(14)の第2の電極(40)にレーザ溶接され、前記半導体チップ(14)を電気的に相互接続するためのリードフレーム(16,18)と、
前記半導体チップ(14)の反対側の前記リードフレーム(16,18)に取り付けられ且つ前記リードフレーム(16,18)から電気的に絶縁された制御導体(52)とを備え、
前記制御導体(52)は、前記一組(36a,36b)の前記半導体チップ(14)の制御電極(58)に電気的に接続され、
前記制御導体(52)は、少なくとも1つの前記制御電極(58)にレーザ溶接される、電力半導体モジュール(10)。 - 前記リードフレーム(16,18)に取り付けられた可撓性回路基板(44,46)をさらに備え、
前記制御導体(52)は、前記可撓性回路基板(44,46)の金属層(50)によって少なくとも部分的に形成される、請求項1に記載の電力半導体モジュール(10)。 - 前記リードフレーム(16,18)に取り付けられた電気絶縁ワイヤ(94)をさらに備え、
前記制御導体(52)は、前記電気絶縁ワイヤ(94)の金属コアによって少なくとも部分的に形成される、請求項1または2に記載の電力半導体モジュール(10)。 - 前記リードフレーム(16,18)に取り付けられた電気絶縁層(50)を含む制御基板(90)をさらに備え、
前記制御導体(52)は、前記制御基板(90)の金属被覆層(50)によって少なくとも部分的に形成される、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記制御導体(52)は、ワイヤボンド(56)を介して、少なくとも1つの前記制御電極(58)に接続される、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。
- 前記制御導体(52)は、制御基板(90)または可撓性回路基板(44,46)の一部であり、
前記可撓性回路基板(44,46)は、前記制御電極(58)で前記リードフレーム(16,18)の上方に突出する、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記制御導体(52)は、貫通ビアを介して、少なくとも1つの前記制御電極(58)に電気的に接続される、請求項6に記載の電力半導体モジュール(10)。
- ゲート導体(52)および補助導体(54)は、前記一組の半導体チップ(14)の反対側の前記リードフレーム(16,18)に取り付けられ且つ前記リードフレーム(16,18)から電気的に絶縁され、
前記補助導体(54)の2つのストリップは、前記ゲート導体(52)の両側に設けられる、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記半導体チップ(10)の前記第2の電力電極(40)には、前記リードフレーム(16,18)がレーザ溶接されており、
前記第2の電力電極(40)は、前記半導体チップ(14)に接合された金属バッファプレート(42)を含み、
前記リードフレーム(16,18)は、前記バッファプレート(42)にレーザ溶接される、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記リードフレーム(16,18)は、前記電力半導体モジュール(10)の電力端子(68,68′)を形成し、
前記電力端子(68,68′)は、前記電力半導体モジュール(10)のハウジング(88)から突出する、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 制御端子(30′)は、前記リードフレーム(16,18)と同じ高さで前記ハウジング(88)から突出し、
前記制御端子(30′)は、前記リードフレーム(16,18)と同じ材料で同じ厚さに作製され、
前記制御端子(30′)は、前記ハウジング(88)内の前記制御導体(52)に電気的に接続される、請求項10に記載の電力半導体モジュール(10)。 - 前記半導体チップ(14)は、少なくとも1つの列(34a~34d)に配置され、
前記リードフレーム(16,18)は、前記列に沿って延在する中央部(66)と、前記中央部(66)から前記列(34a~34d)の前記半導体チップ(14)の上方に突出する分岐部(70)とを含む、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記分岐部(70)は、前記半導体チップ(14)に向かって湾曲している、請求項12に記載の電力半導体モジュール(10)。
- 前記電力半導体モジュール(10)は、ハーフブリッジを形成し、
第1組(36a)の半導体チップ(14)は、ローサイドスイッチを形成ように、対応する電力電極(38,40)と並列に接続され、
第2組(36b)の半導体スイッチ(14)は、ハイサイドスイッチを形成するように、対応する電力電極(38,40)と並列に接続され、
第1のリードフレーム(16)は、前記第1組(36a)の半導体チップ(14)の第2の電極(40)にレーザ溶接され、
第2のリードフレーム(18)は、前記第2組(36b)の半導体チップ(14)の第2の電極(40)にレーザ溶接される、先行する請求項のいずれか1項に記載の電力半導体モジュール(10)。 - 前記第1組(36a)の前記半導体チップ(14)は、前記電力半導体モジュール(10)の中心線に沿って列(34a,34b)に配置され、
前記第2組(36b)の前記半導体チップ(14)は、前記第1組(36a)の両側且つ前記第1組(36a)の外側で2列(34c,34d)に配置され、
前記第1のリードフレーム(16)は、前記電力半導体モジュール(10)の前記基板(12)と前記第2のリードフレーム(18)との間に配置される、請求項14に記載の電力半導体モジュール(10)。
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