JP2010538483A - 基板プレート、殊にdcbセラミック基板プレートを用いる電子的な構成素子の製造方法および接触接続方法 - Google Patents
基板プレート、殊にdcbセラミック基板プレートを用いる電子的な構成素子の製造方法および接触接続方法 Download PDFInfo
- Publication number
- JP2010538483A JP2010538483A JP2010523459A JP2010523459A JP2010538483A JP 2010538483 A JP2010538483 A JP 2010538483A JP 2010523459 A JP2010523459 A JP 2010523459A JP 2010523459 A JP2010523459 A JP 2010523459A JP 2010538483 A JP2010538483 A JP 2010538483A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- support film
- fixed
- component
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (18)
- 上面(3)および/または下面(5)にそれぞれ配置されている、固定および/または電気的な接触接続のための少なくとも1つの接触面(7)を備えている、ケーシングされていない少なくとも1つの電子的な構成素子(1)、殊に電力用構成素子または電力用半導体構成素子を接触接続させる方法において、
前記構成素子(1)を該構成素子(1)の下面(5)を用いて、該下面(5)の表面を超えて延在している絶縁性の支持体フィルム(13)に固定し、
前記上面(3)の表面を超えて延在し、成形された3次元構造体を形成しているそれぞれ1つの導電性の導体部(15)に、前記上面(3)における前記接触面(7)を固定および/または電気的に接触接続させ、
前記支持体フィルム(13)と前記導体部(15)の前記3次元構造体との間に絶縁性質量体(17)を形成し、
前記接触面(7)の領域において前記下面(5)から前記支持体フィルム(13)を除去し、
基板(11)、殊に導体により事前に構造化されたDCBセラミック基板において前記接触面(7)と対向しているそれぞれ1つの接触面(9)に前記下面(5)における前記接触面(7)を固定および/または電気的に接触接続させることを特徴とする、方法。 - 前記導体部(15)から、殊に前記支持体フィルムの平面にまで延在する、少なくとも1つの接触フレーム(16)を形成する、請求項1記載の方法。
- 導体部(15)が前記支持体フィルムの平面にまで延在する場合、前記接触フレーム(16)の領域における前記支持体フィルム(13)を除去し、前記接触フレーム(16)を前記基板(11)における対向する接触面(9)に固定および/または電気的に接触接続させる、請求項2記載の方法。
- 高導電性の材料、殊に銅を有する前記導体路(15)および/または前記構成素子(1)の接触面(7)をはんだ付けないしはんだ(19)により前記基板(11)に固定および/または電気的に接触接続させる、請求項1から3までのいずれか1項または複数項記載の方法。
- 前記絶縁性質量体(17)を射出成形により形成する、および/または、前記絶縁性質量体(17)を成形する従来の射出成形ツールを使用する、請求項1から4までのいずれか1項または複数項記載の方法。
- 前記支持体フィルム(13)は感光性であり、露光および/またはアブレーション、例えばレーザアブレーションにより前記支持体フィルム(13)を除去するか、前記支持体フィルム(13)内に開口部(21)を形成する、請求項1から5までのいずれか1項または複数項記載の方法。
- 前記下面(5)における接触面(7)および/または前記接触フレーム(16)をはんだ付けおよび/または接着により、前記基板(11)のそれぞれの前記接触面(9)に固定および/または電気的に接触接続させる、請求項1ないし3から6までのいずれか1項または複数項記載の方法。
- 前記構成素子(1)を前記支持体フィルム(13)上の所定の位置において、所定の機能構造に応じて固定する、請求項1から7までのいずれか1項または複数項記載の方法。
- 前記導体部(15)上、および/または、前記絶縁性質量体(17)内、および/または、前記基板(11)上に冷却用装置、殊に冷却チャネル、ヒートシンク(23)および/またはヒートパイプを配置する、請求項1から8までのいずれか1項または複数項記載の方法。
- 請求項1から9までのいずれか1項または複数項記載の方法により製造されるデバイスにおいて、
上面(3)および/または下面(5)にそれぞれ配置されている、固定および/または電気的な接触接続のための少なくとも1つの接触面(7)を備えている、ケーシングされていない少なくとも1つの電子的な構成素子(1)、殊に電力用半導体素子を有し、
前記構成素子(1)は該構成素子(1)の下面(5)を用いて、前記接触面(7)の領域において、基板(11)、殊にDCBセラミック基板における対向するそれぞれ1つの接触面(9)に固定および/または電気的に接触されており、
絶縁性の支持体フィルム(13)が前記接触面(7)の領域外で前記下面(5)を超えて、前記構成素子(1)に対向する側における前記基板(11)の上に形成されており、
前記上面(3)における前記接触面(7)には、成形された3次元構造体を形成するそれぞれ1つの導体部(15)が固定および/または電気的に接触接続されており、前記導体部(15)は前記上面(3)の表面を超えて延在しており、
前記支持体フィルム(13)と前記導体部(15)の前記3次元構造体との間に絶縁性質量体(17)が形成されていることを特徴とする、デバイス。 - 前記導体部(15)から、殊に前記支持体フィルムの平面にまで延在する、少なくとも1つの接触フレーム(16)が形成される、請求項10記載のデバイス。
- 導体部(15)が前記支持体フィルムの平面にまで延在する場合、前記接触フレーム(16)の領域においては前記支持体フィルム(13)が除去されており、ないし開口部(21)が形成されており、前記接触フレーム(16)は前記基板(11)における対向する接触面(9)に固定および/または電気的に接触接続されている、請求項11記載のデバイス。
- 前記導体部(15)は高導電性の材料、殊に銅を有する、請求項10から12までのいずれか1項または複数項記載のデバイス。
- 2つより多くの構成素子(1)では、該構成素子(1)は前記支持体フィルム(13)上の所定の位置において、所定の機能構造に応じて固定されている、請求項10から13までのいずれか1項または複数項記載のデバイス。
- 前記導体部(15)上、および/または、前記絶縁性質量体(17)内、および/または、前記基板(11)上に冷却用装置、殊に冷却チャネル、ヒートシンク(23)および/またはヒートパイプが配置されている、請求項10から14までのいずれか1項または複数項記載のデバイス。
- 前記導体部(15)の膨張係数および前記絶縁性質量体(17)は高い熱サイクル耐性および電気サイクル耐性を生じさせるために相互に適合されている、請求項10から15までのいずれか1項または複数項記載のデバイス。
- 上面(3)および/または下面(5)にそれぞれ配置されている、固定および/または電気的な接触接続のための少なくとも1つの接触面(7)を備えている、ケーシングされていない少なくとも1つの電子的な構成素子(1)、殊に電力用半導体素子を有し、
前記構成素子(1)は該構成素子(1)の下面(5)を用いて、該下面(5)の表面を超えて延在している絶縁性の支持体フィルム(13)に固定されており、
前記上面(3)における前記接触面(7)には、成形された3次元構造体を形成するそれぞれ1つの導体部(15)が固定および/または電気的に接触接続されており、前記導体部(15)は前記上面(3)の表面を超えて延在しており、
前記支持体フィルム(13)と前記導体部(15)の前記3次元構造体との間には絶縁性質量体(17)が形成されていることを特徴とする、装置。 - 前記導体部(15)から、殊に前記支持体フィルムの平面にまで延在する、少なくとも1つの接触フレーム(16)が形成されている、請求項17記載の装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102007041921A DE102007041921A1 (de) | 2007-09-04 | 2007-09-04 | Verfahren zur Herstellung und Kontaktierung von elektronischen Bauelementen mittels einer Substratplatte, insbesondere DCB-Keramik-Substratplatte |
PCT/EP2008/060196 WO2009030562A1 (de) | 2007-09-04 | 2008-08-04 | Verfahren zur herstellung und kontaktierung von elektronischen bauelementen mittels einer substratplatte, insbesondere dcb-keramik-substratplatte |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2010538483A true JP2010538483A (ja) | 2010-12-09 |
Family
ID=40030334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010523459A Ceased JP2010538483A (ja) | 2007-09-04 | 2008-08-04 | 基板プレート、殊にdcbセラミック基板プレートを用いる電子的な構成素子の製造方法および接触接続方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8261439B2 (ja) |
EP (1) | EP2195832A1 (ja) |
JP (1) | JP2010538483A (ja) |
KR (1) | KR20100067097A (ja) |
CN (1) | CN101842887B (ja) |
DE (1) | DE102007041921A1 (ja) |
WO (1) | WO2009030562A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2594867T3 (es) | 2007-03-09 | 2016-12-23 | Alexza Pharmaceuticals, Inc. | Unidad de calentamiento para usar en un dispositivo de administración de fármaco |
US20100065052A1 (en) * | 2008-09-16 | 2010-03-18 | Alexza Pharmaceuticals, Inc. | Heating Units |
US20120048963A1 (en) | 2010-08-26 | 2012-03-01 | Alexza Pharmaceuticals, Inc. | Heat Units Using a Solid Fuel Capable of Undergoing an Exothermic Metal Oxidation-Reduction Reaction Propagated without an Igniter |
US8941208B2 (en) * | 2012-07-30 | 2015-01-27 | General Electric Company | Reliable surface mount integrated power module |
DE102014203306A1 (de) * | 2014-02-25 | 2015-08-27 | Siemens Aktiengesellschaft | Herstellen eines Elektronikmoduls |
EP4272744A3 (en) | 2015-03-11 | 2024-01-24 | Alexza Pharmaceuticals, Inc. | Use of antistatic materials in the airway for thermal aerosol condensation process |
DE102016220553A1 (de) | 2016-10-20 | 2018-04-26 | Robert Bosch Gmbh | Leistungsmodul |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09116045A (ja) * | 1995-10-13 | 1997-05-02 | Dainippon Printing Co Ltd | リードフレームを用いたbgaタイプの樹脂封止型半導体装置およびその製造方法 |
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
EP1641035A1 (en) * | 2004-09-27 | 2006-03-29 | STMicroelectronics S.r.l. | Mounting method of electronic power components on printed circuit boards |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2751450B2 (ja) * | 1989-08-28 | 1998-05-18 | セイコーエプソン株式会社 | テープキャリアの実装構造及びその実装方法 |
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
WO2001024260A1 (en) * | 1999-09-24 | 2001-04-05 | Virginia Tech Intellectual Properties, Inc. | Low cost 3d flip-chip packaging technology for integrated power electronics modules |
AU2002340750A1 (en) | 2001-09-28 | 2003-04-14 | Siemens Aktiengesellschaft | Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces |
JP2003204027A (ja) * | 2002-01-09 | 2003-07-18 | Matsushita Electric Ind Co Ltd | リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法 |
JP2003341782A (ja) * | 2002-05-27 | 2003-12-03 | Oki Electric Ind Co Ltd | 電子デバイス収容体、電子デバイスの搬送方法、電子デバイスの実装方法、電子デバイスの収容方法 |
JP3809168B2 (ja) * | 2004-02-03 | 2006-08-16 | 株式会社東芝 | 半導体モジュール |
DE102004030042B4 (de) * | 2004-06-22 | 2009-04-02 | Infineon Technologies Ag | Halbleiterbauelement mit einem auf einem Träger montierten Halbleiterchip, bei dem die vom Halbleiterchip auf den Träger übertragene Wärme begrenzt ist, sowie Verfahren zur Herstellung eines Halbleiterbauelementes |
-
2007
- 2007-09-04 DE DE102007041921A patent/DE102007041921A1/de not_active Withdrawn
-
2008
- 2008-08-04 EP EP08802958A patent/EP2195832A1/de not_active Withdrawn
- 2008-08-04 WO PCT/EP2008/060196 patent/WO2009030562A1/de active Application Filing
- 2008-08-04 US US12/733,507 patent/US8261439B2/en not_active Expired - Fee Related
- 2008-08-04 KR KR1020107007086A patent/KR20100067097A/ko not_active Application Discontinuation
- 2008-08-04 JP JP2010523459A patent/JP2010538483A/ja not_active Ceased
- 2008-08-04 CN CN2008801137606A patent/CN101842887B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09116045A (ja) * | 1995-10-13 | 1997-05-02 | Dainippon Printing Co Ltd | リードフレームを用いたbgaタイプの樹脂封止型半導体装置およびその製造方法 |
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
EP1641035A1 (en) * | 2004-09-27 | 2006-03-29 | STMicroelectronics S.r.l. | Mounting method of electronic power components on printed circuit boards |
Also Published As
Publication number | Publication date |
---|---|
EP2195832A1 (de) | 2010-06-16 |
US20100208438A1 (en) | 2010-08-19 |
DE102007041921A1 (de) | 2009-03-05 |
US8261439B2 (en) | 2012-09-11 |
CN101842887A (zh) | 2010-09-22 |
CN101842887B (zh) | 2012-10-10 |
WO2009030562A1 (de) | 2009-03-12 |
KR20100067097A (ko) | 2010-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9147637B2 (en) | Module including a discrete device mounted on a DCB substrate | |
JP7145075B2 (ja) | 多層回路基板に基づくパワーモジュール | |
US8324726B2 (en) | Semiconductor device, electrode member and electrode member fabrication method | |
EP3198640B1 (en) | Method of forming a semiconductor package | |
US20220375833A1 (en) | Substrate structures and methods of manufacture | |
US20050280998A1 (en) | Half-bridge power module with insert molded heatsinks | |
US9159715B2 (en) | Miniaturized semiconductor device | |
US9891247B2 (en) | U-shaped vertical shunt resistor for Power Semiconductor module | |
JP2010538483A (ja) | 基板プレート、殊にdcbセラミック基板プレートを用いる電子的な構成素子の製造方法および接触接続方法 | |
JP2014199829A (ja) | 半導体モジュール及びそれを搭載したインバータ | |
JP2006253516A (ja) | パワー半導体装置 | |
US9385107B2 (en) | Multichip device including a substrate | |
US20160056088A1 (en) | Cold Plate, Device Comprising a Cold Plate and Method for Fabricating a Cold Plate | |
TW201801273A (zh) | 具有單列直插引線模塊的半導體功率器件及其製備方法 | |
CN104851843A (zh) | 电力用半导体装置 | |
US20180040562A1 (en) | Elektronisches modul und verfahren zu seiner herstellung | |
CN106252332B (zh) | 热敏电阻搭载装置及热敏电阻部件 | |
JP2017511976A (ja) | スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ | |
Meisser et al. | Low-inductive compact SiC power modules for high-frequency operation | |
EP2178117A1 (en) | Power semiconductor module with double side cooling | |
CN109844939A (zh) | 功率模块 | |
JP2013041939A (ja) | 半導体モジュール及びそれを搭載したインバータ | |
CN111584422B (zh) | 半导体装置及其制造方法 | |
CN104867903B (zh) | 电子模块 | |
JP7392308B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101228 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110913 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110916 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111214 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111221 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120214 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120718 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121116 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121126 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130201 |
|
A045 | Written measure of dismissal of application [lapsed due to lack of payment] |
Free format text: JAPANESE INTERMEDIATE CODE: A045 Effective date: 20130624 |