CN103247545A - 半导体装置及其方法 - Google Patents

半导体装置及其方法 Download PDF

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Publication number
CN103247545A
CN103247545A CN2013100491812A CN201310049181A CN103247545A CN 103247545 A CN103247545 A CN 103247545A CN 2013100491812 A CN2013100491812 A CN 2013100491812A CN 201310049181 A CN201310049181 A CN 201310049181A CN 103247545 A CN103247545 A CN 103247545A
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China
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semiconductor chip
bearing part
solder
layer
solder material
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CN2013100491812A
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Inventor
拉尔夫·奥特伦巴
林峰
阿卜杜尔·拉赫曼·穆罕默德
张翠薇
艾达·菲舍巴赫
克萨韦尔·施勒格尔
于尔根·施雷德尔
约瑟夫·赫格劳尔
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN103247545A publication Critical patent/CN103247545A/zh
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Abstract

本发明涉及半导体装置及其方法。该方法包括提供具有第一主表面和第二主表面的半导体芯片。以半导体芯片的第一主表面面向承载件的形式，将半导体芯片放置在承载件上。在第一主表面和承载件之间设置焊料材料的第一层。以第一接触区域面向半导体芯片的第二主表面的方式，将包括第一接触区域的接触夹放置在半导体芯片上。在第一接触区域和第二主表面之间设置焊料材料的第二层。其后，将热量施加于焊料材料的第一层和第二层，从而在承载件、半导体芯片和接触片之间形成扩散焊料结合。

Description

半导体装置及其方法
技术领域
本发明涉及将半导体芯片安装在承载件（carrier）上的技术，并且在具体实施方式中，涉及扩散焊接的技术。
背景技术
半导体装置制造商经常努力增加他们的产品的性能，而减少他们的制造成本。半导体装置的制造中的成本密集的区域是封装半导体芯片。如本领域技术人员知道的，在晶片上制作集成电路，然后，将其切割（singulated），以便生产半导体芯片。随后，可将半导体芯片安装在电子传导的承载件上，如引线框架（leadframes）。以低的费用提供高产量的封装方法是期望的。
关于这些和其他原因，对本发明存在需要。
附图说明
包含附图，以提供对实施方式的进一步理解，并且将附图包括在本说明书中且构成本说明书的一部分。附图说明了实施方式，并且与描述一起用来解释实施方式的原理。如通过参考以下详细描述将，它们变得更好地被理解一样，将容易地理解其他实施方式和实施方式的许多预期的优势。附图的要素相对于彼此不一定是按比例的。同样的参考数字指示相应的类似部分。
图1A-1D示意性地示出了将半导体芯片安装到承载件上的方法的一个实施方式的横截面图；
图2A-2C示意性地示出了将半导体芯片安装到承载件上和将接触芯片安装到半导体芯片上的方法的一个实施方式的横截面图；
图3A-3C示意性地示出了将半导体芯片安装到承载件上和将接触芯片安装到半导体芯片和引线上的方法的一个实施方式的横截面图；
图4示意性地示出了安装到承载件上的半导体芯片和连接到半导体芯片上的接触芯片的一个实施方式的横截面图，其中接触芯片是倾斜的；
图5A-5C示意性地示出了将半导体芯片安装到承载件上的方法的一个实施方式的横截面图；
图6A示意性地示出了根据制造半导体装置的方法的一个实施方式的引线框架的顶视图；
图6B示意性地示出了沿着图6A的线A-A’的横截面图；
图6C示意性地示出了沿着图6A的线B-B’的横截面图；
图7A示意性地示出了根据制造半导体装置的方法的一个实施方式的在将半导体芯片放置在引线框架上之后，与图6B对应的横截面图；
图7B示意性地示出了如图7A所示的配置（布置）的顶视图；
图8A示意性地示出了在将焊料材料沉积在半导体芯片上之后，与图7A对应的横截面图；
图8B示意性地示出了如图8A中所示的配置（布置）的顶视图；
图9A示意性地示出了在将接触芯片放置在半导体芯片上之后，与图8A对应的横截面图；
图9B示意性地示出了如图9A中所示的配置的顶视图；
图9C示意性地示出了在被引入到炉子中和形成扩散焊接接缝（焊接接点）之后，图9A的配置的横截面图；
图10示出了利用隧道式炉（隧道炉）来制造半导体装置的方法的实施方式的示意图；和
图11示出了在炉子中利用批处理来制造半导体装置的方法的实施方式的示意图。
具体实施方式
在以下详细描述中，参考附图，所述附图形成其一部分，并且其中，通过可在其中实施本发明的示例性具体实施方式来示出。在这点上，参照待被描述的图的方向使用方向术语，如“顶部”、“底部”、“前面”、“后面”、“前沿”、“尾部”等。因为可以以许多不同取向来设置实施方式的部件，因此方向术语被用于说明的目的，并且决不是限制性的。应该理解，可以利用其他实施方式，并且在不脱离本发明的范围的情况下，可进行结构改变或逻辑改变。因此，以下详细描述不应该认为是限制意义上的，并且本发明的范围由所附的权利要求限定。
应该理解，除非另另外具体指出，否则此处描述的各种示例性实施方式的特征可以彼此结合。
如在本说明书中应用的，术语“耦接的”和/或“电耦接的”不倾向于意味着，要素（元件）必需直接地耦接在一起；可以在“耦接的”或“电耦接的”要素（元件）之间设置中间要素（中间元件）。
下面描述包括半导体芯片的设备。特别地，可以涉及具有垂直结构（纵向结构，竖直结构）的半导体芯片，即，可以以电流可在垂直于半导体芯片的主表面的方向中流动的方式来制造半导体芯片。具有垂直结构的半导体芯片在它的两个主表面上具有电极，即在它的顶面和底面。
特别地，可以涉及功率半导体芯片。功率半导体芯片可具有垂直结构（纵向结构，竖直结构）。例如，垂直功率半导体芯片可以被构造成功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结型栅极场效应晶体管）、功率双极晶体管或功率二极管。例如，功率MOSFET的源电极和栅电极可以位于一个主表面上，而将功率MOSFET的漏电极布置在其他主表面上。不需要由特定半导体材料来制造半导体芯片，例如，Si、SiC、SiGe、GaAs，并且此外，半导体芯片可以包含不是半导体的无机材料和/或有机材料。半导体芯片可能是不同类型的并且可以通过不同的技术来制造。
半导体芯片可以具有接触焊盘（或电极或接触元件），其允许与半导体芯片中包括的集成电路进行电接触。接触焊盘可以包括一个或更多个金属层，其施加于半导体芯片的半导体材料。可以利用任何期望的几何形状和任何期望的材料组成来制造金属层。例如，金属层可以为遮盖区域的层的形式。可以将能够形成扩散焊料结合的任何期望的金属，例如，Cu、Ni、NiSn、Au、Ag、Pt、Pd，和这些金属中的一种或多种的合金用作材料。金属层不需要是同质的或仅由一种材料制造，即，金属层中可能含有不同组成（成分）和浓度的材料。
可以使用焊料材料以电和机械地将半导体芯片连接至承载件和/或将接触芯片连接至半导体芯片和/或将接触芯片连接至承载件的引线。可以使用能够形成扩散焊料结合（solder bonds）的任何焊料材料，例如，包括Sn、SnAg、SnAu、In、InAg、和InAu中的一种或多种的焊料材料。此外，焊料材料可以不含Pb。
特别地，如果焊料材料包括Sn，则焊料材料可以包括大于80％、90％或甚至95％含量的Sn。焊料材料也可以包括100％含量的Sn。
焊料材料可以包括直径在1到30μm之间，更具体地在5到10μm之间的金属颗粒。
图1A-1D示意性地示出了根据一个实施方式的用于将半导体芯片安装在承载件上的方法。图1A示意性地示出了承载件15。例如，承载件15可以是引线框架的芯片焊盘（die pad）、PCB（印刷电路板）、DCB（直接铜结合（Direct Copper Bond）），其是在它的顶面和底面上具有铜层的陶瓷衬底，等等。承载件15由任何能够形成扩散焊料结合的期望的金属来制造或者承载件15具有由任何能够形成扩散焊料结合的期望的金属制造的上表面14，例如，Cu、Ni、NiSn、Au、Ag、Pt、Pd、或者这些金属中的一种或多种的合金。
在图1B中，将焊料材料13的第一层沉积在承载件15的上表面14上。焊料材料13的第一层可以由上述提及的任何焊料材料制成。
在一个实施方式中，通过利用溅射工艺来沉积焊料材料的第一层13。在这种情况中，将沉积速度设置为这样的值，使得获得所需量或沉积的焊料材料的层厚度。
在一个实施方式中，可通过电气化学沉积工艺来沉积焊料材料的第一层13。对于该目的，将含有焊料颗粒的溶液施加于承载件15，并且在承载件15和参考电极之间施加适当的电压，使得焊料颗粒沉积在承载件15的上表面14上。
在一个实施方式中，可以通过将焊料材料糊印刷或分配在承载件15的上表面14上来沉积焊料材料的第一层13。焊料材料糊可以包含如上提及的金属颗粒。此外，其可以包含焊剂材料。它可以不含有本领域已知的用于分离金属颗粒的任何有机溶剂。
图1C示意性地示出了放置在承载件15上的半导体芯片10，其中半导体芯片10的第一主表面11面向承载件15并且第二主表面12远离面向承载件15。在半导体芯片10的第一主表面11和承载件15的上表面14之间布置焊料材料的第一层13。可在与焊料材料的第一层13相对的和邻近的半导体芯片10的第一主表面11上安装第一芯片电极（未示出）。
图1D示意性地示出了为了将半导体芯片10牢固地连接至承载件15，将焊料材料加热到温度T。在炉子50中完成加热。
在一个实施方式中，例如，通过炉子50施加给焊料材料的最大温度可以在250℃到350℃之间，更具体地，例如，在270℃到320℃之间。
在一个实施方式中，在焊料材料位于炉子期间的停留时间在30秒到300秒之间，更具体地在60s到120s之间。
在一个实施方式中，在它停留在炉子50中期间，没有将外部压力施加于图1D所示的配置（布置，arrangement）。即，当在炉子50中暴露于高温时，仅重力控制施加于焊料材料的第一层13的力或压力。
在停留在炉子50中期间，将焊料材料的第一层13转变成第一扩散焊料结合层13a。更具体地，焊料材料开始在熔化温度下熔融。例如，Sn具有232℃的熔化温度。将焊料材料暴露于比焊料材料的熔化温度高的温度T。通过扩散，在焊料材料的第一层13中形成金属间相。在炉子50中的停留时间的末端，完全地转变第一层13的所有焊料材料，例如，已经完全地将其变成金属间相。用这种金属间相制造用那样的方式生产的第一扩散焊料结合层13a。它能够经受高温，它是高度机械稳定的并且表现出高的电和热传导性。
应该注意，可以基于要生产的第一扩散焊料结合层13a的厚度（例如，沉积在承载件15上的焊料材料的量）并且基于用于形成金属间相的金属材料的种类（例如，在承载件15的上表面14上的金属材料和半导体芯片10的电极的金属材料），来选择温度T和炉子停留时间。在一个实施方式中，第一扩散焊料结合层13a的厚度等于或小于，例如10μm，更具体地5μm。此外，在一个实施方式中，在焊料材料的第一层13的两侧使用的用于形成金属间相的材料是相同的材料。在这种情况下，在转变成第一扩散焊料结合层13a期间，在焊料材料的第一层13的两侧上发生的扩散过程具有相同的扩散速度。
图2A-2C举例说明了将半导体芯片10安装到承载件15上并且将接触芯片15安装到半导体芯片10上的工序。可以将结合图2A-2C描述的工艺的方面与在前述实施方式中描述的工艺结合，并且反之亦然。
首先，可完成涉及结合图1A-1C的工序。然后，以图1C中所示的配置开始，如图2A中所示，可将焊料材料的第二层16沉积在半导体芯片10的第二主表面12上。第二芯片电极（未示出）可在半导体芯片10的第二主表面12上延伸，并且可将焊料材料的第二层16设置在该第二芯片电极上。
焊料材料的第二层16的焊料材料可与焊料材料的第一层13的焊料材料相同。此外，与针对施加焊料材料的第一层13描述相同的工艺可以用于将焊料材料的第二层16沉积在半导体芯片10的第二主表面12上。应该注意，当沉积焊料材料的第二层16时，不能将焊料材料的第一层13转变成扩散焊料结合层13a。
在图2B中，将接触夹（接触钳，contact clip）25放置在半导体芯片10上。接触夹25可具有第一接触区域26。这样放置接触夹25，即，将第一接触区域26放置在焊料材料的第二层16上。接触夹25或，至少，接触夹25的第一接触区域26可以由任何期望的能够形成扩散焊料结合的金属，例如，Cu、Ni、NiSn、Au、Ag、Pt、Pd、或这些金属中的一种或多种的任何合金来制造。
接触夹25可以是连接至半导体装置的外部终端或形成半导体装置的外部终端的引线。例如，接触夹25可以是引线框架的引线并且承载件15可以是引线框架的芯片焊盘。如将在下面更详细地描述的，在其他实施方式中，接触夹可以是在第二芯片电极和半导体设备的外部终端（如，例如，引线框架的引线）之间桥接的传导元件。
在图2C中，将图2B中所示的配置引入到炉子50中。在炉子50中，将焊料材料的第一层13的焊料材料和焊料材料的第二层16的焊料材料加热到温度T。图2C中使用的熔炉工艺可以与参照图1D描述的相同，并且为了避免重复，将参考相应的描述。特别地，在它停留在炉子50中期间，没有将外部压力施加于图2C中所示的配置，即，当在炉子50中暴露于高温时，仅仅通过重力来控制施加于焊料材料的第一层13和施加于焊料材料的第二层16的力或压力。
在停留在炉子50期间，同时分别将焊料材料的第一层13和焊料材料的第二层16转变成第一扩散焊料结合层13a和第二扩散焊料结合层16a。与第一扩散结合层13a有关的所有的公开可同样地适用于第二扩散结合层16a，并且为了简洁，参考相应的公开。特别地，相同的焊料材料可用于焊料材料的第一层13和第二层16，并且第二扩散焊料结合层16a可具有与第一扩散焊料结合层13a的厚度相同的范围或相同的厚度。
图3A-3C举例说明了将半导体芯片10安装到承载件15上和将接触夹25安装到半导体芯片10上的工序。可将此处描述的其他实施方式的方面与结合图3A-3C描述的工艺结合，并且反之亦然。
在图3A中，提供引线20。引线20可以是引线框架的引线，其中，在这种情况下，承载件15可以是引线框架的芯片焊盘。已经将焊料材料的第三层21沉积在引线20的上表面上。涉及焊料材料的第一和第二层13、16的所有公开内容同样地应用于焊料材料的第三层21。特别地，可通过与上述描述相同的技术，将焊料材料的第三层21的焊料材料沉积在引线20上，并且焊料材料可以与在焊料材料的第一和第二层13、16中使用的材料相同。此外，焊料材料的第三层21的厚度可分别与焊料材料的第一或第二层13、16的厚度的范围相同或与第一或第二层的厚度相同。
在图3B中，将接触夹25放置在半导体芯片10和引线20上。接触夹25具有与焊料材料的第三层21相对的和与其邻近的第二接触区域27。第二接触区域27可由与上面提及的涉及第一接触区域26相同的材料组成。
在图3C中，将图3B中所示的配置引入到炉子50中。以相同的方式加热焊料材料的第一、第二和第三层13、16和21，并且如上面参照图1D和2C描述的，在炉子50中处理。特别地，再次，在停留在炉子50中期间，可不将外部压力施加于图3C所示的配置，并且可使用如上提及的熔炉停留时间。结果，产生第一、第二和第三扩散焊料结合层13a、16a和21a。分别通过第二和第三扩散焊料结合层16a和21a将接触夹25牢固地固定到半导体芯片10和引线20上。涉及第一和第二扩散焊料结合层13a和16a的所有公开内容（例如，材料，厚度等）等同地应用于第三焊料结合层21a，并且为了简洁，避免重复。
如图4中描述的，可通过相对于平面的具体的倾斜距离TD，使接触夹25倾斜，其中由半导体芯片10的第二主表面12定义平面。当在邻近接触夹25的外端的侧面上测量时（即，图4的左侧）并且当在相反面上测量时（即，图4的右侧），通过第二扩散焊料结合层16a的厚度的差异来限定倾斜距离TD。在一个实施方式中，例如，倾斜距离TD等于或小于10μm，更具体地5μm。换句话说，第二扩散焊接结合层16a的小厚度保证了接触夹25的最大倾斜也限于小值。应该注意，图4中示出的倾斜距离同样地适用于图2A-2C中所示的实施方式和图3A-3C中所示的实施方式。
图5A-5C示意性地示出和举例说明了用于将半导体芯片10安装到承载件15上的方法。在将半导体芯片10放置在承载件上但是沉积在半导体芯片10的第一主表面11上之前（图5A），在将半导体芯片10与焊料材料的第一层13一起放置在承载件15上之前，除了没有将焊料材料的第一层13沉积在承载件15上之外，图5A-5C中公开的方法与结合图1A-1D描述的方法对应。除了这种差异之外，图5B中所示的配置与图1C中所示的配置对应。在炉子50中执行焊料材料的第一层13到第一扩散焊料结合层13a的转变，并且与结合图1D中描述的相同的方式完成所述转变。为了简洁，参考相应的公开内容，以便避免重复。
类似于图5A-5C中所示的方法，如上面结合图2A-4描述的，当将接触夹25放置在半导体芯片10和（可选地）引线20上并且焊接到其上时，在将接触夹25放置在半导体10和（可选地）引线20上之前，可首先将焊料材料的第二层16和/或焊料材料的第三层21沉积在接触夹25上。再次，除了这种变化之外，可以如上面描述的相同的方式完成将半导体芯片10安装到承载件15上和将接触夹25安装到半导体芯片10和（可选地）引线20上的这样的方法。为了简洁，省略了重复。
图6A-9C举例说明了根据一个实施方式的制造半导体装置的阶段。在某些方面中，下列公开内容比前述实施方式的公开内容更加详细。应该注意，可将结合图6A-9C描述的细节与在前述实施方式中描述的概念和方面结合。反过来，可将关于前述实施方式公开的概念和方面与参照图6A-9C解释的实施方式的公开内容结合。
图6A示意性地示出了引线框架100。在平面图（图6A）中、沿着线A-A’的横截面图（图6B）和沿着线B-B’的横截面图（图6C）中示出了引线框架100。引线框架100可以包括芯片焊盘101、第一引线102、第二引线103和第三引线104。引线102-104基本上以平行的方式从芯片焊盘101的一侧突出。第二引线103可与芯片焊盘101的一侧相连。可通过橡皮障（dam）（转向拉杆）来连接芯片焊盘101和引线102-104，为了简洁，在图中没有阐明所述橡皮障。如图6B和6C中所示，可选地，可将引线102-104布置在不同于芯片焊盘101的平面中，但是可替换地，可将其布置在相同的平面中。
在一个实施方式中，引线框架100可以是承载件15和引线20的具体实现方式。更具体地，芯片焊盘101可与承载件15对应并且第一引线102可与引线20对应，并且反之亦然。可由上面提及的材料来制造引线框架100。引线框架100的厚度可以在100μm至1mm的范围内或者甚至可以更厚。可以通过打孔、轧制或冲压金属板来制造引线框架100。
图7B示意性地示出了作为功率半导体芯片且放置在芯片焊盘101上的半导体芯片10。在一个实施方式中，可将另外的功率半导体芯片放置在相同的芯片焊盘101上或放置在引线框架100的另外的芯片焊盘上，其没有在图7B中示出。
如图7A中所示，将半导体芯片10放置在芯片焊盘101上，其中它的第一主表面11面向芯片焊盘101。半导体芯片10可以具有在第一主表面上的第一电极17和在第二主表面12上的第二电极22。第一和第二电极17、22是负载电极。此外，如图7B中所示，半导体芯片10在它的第二主表面12上可具有第三电极18。第三电极18可以是控制电极。芯片焊盘101的顶面可以比半导体10的第一主表面11大。
半导体芯片10被构造成功率晶体管，例如，功率MOSFET、IGBT、JFET或功率双极晶体管，或功率二极管。在功率MOSFET或JFET的情形中，第一电极17是漏电极，第二电极22是源电极，并且第三电极18是栅电极。在IGBT的情形中，第一电极17是集电极，第二电极22是发射电极，和第三电极18是栅电极。在功率双极晶体管的情形中，第一电极17是集电极，第二电极22是发射电极，和第三电极18是基极电极。在功率二极管的情形中，第一和第二电极17、22是阳极和阴极，并且不存在第三电极。在操作期间，可在第一和第二电极17、22之间施加高于5、50、100、500或1000V的电压。
如图7中所示，在加热工艺之前，在第一电极17和芯片焊盘101之间布置焊料材料的第一层13。参考前述实施方式，以便避免重复。
图8A-8B示意性地示出了焊料材料的第二和第三层16、21，分别地将它们沉积在半导体芯片10的第二电极22的至少一部分上和第一引线102的上表面上。在已经在芯片焊盘101和半导体芯片10之间形成焊接接缝之前，沉积焊接材料的第二和第三层16、21。通过利用印刷、分配或如以前提及的任何其他适当的技术来沉积焊料材料的第二和第三层16、21。例如，焊料材料的第二和第三层16、21可具有等于或小于10μm，更具体地5μm的厚度。在一个实施方式中，可利用镍或铜或任何其他金属或如上述提及的金属合金的层来涂覆半导体芯片10的第二电极22和/或第一引线102的上表面，其允许在扩散焊接工艺中生产焊接接缝。另外，可将银或金层沉积在该层上，银或金层具有的厚度在10至200nm的范围内。银或金层阻止镍或铜层（或上面提及的任何其他金属层）的氧化。
图9A-9B示意性地示出了放置在第一引线102和半导体芯片10上的接触夹25。接触夹25具有面向半导体芯片10的第二电极22的第一接触区域26和面向第一引线102的第二接触区域27。
可由如上面提及的金属或金属合金来制造接触夹25。接触夹25的形状不限于任何大小或几何形状。接触夹25可具有如图9B中示例性示出的形状，但是也可能是任何其他形状。在一个实施方式中，接触夹25具有范围从100至200μm的厚度。可通过冲压、打孔、挤压、切割、锯切、轧制或任何其他适当的技术来制作接触夹25。可通过冲压、打孔、蚀刻术或任何其他适当的技术来制造第一和第二接触区域26、27。可利用如上述提及的镍或铜或任何其他金属或金属合金的层来涂覆它们，其允许在扩散焊接工艺中生产焊接接缝。另外，可将银或金的层沉积在该层上，银或金层的厚度的范围是从10至200nm。银或金层阻止镍或铜层（或上述提及的任何其他金属层）的氧化。
图9C示意性地示出了为了将焊料材料的层13、16和21转变成各自的扩散焊料结合层13a、16a和21a，同时将引入到炉子50中的图9A-9B所示的配置和焊料材料的层13、16和21加热到温度T。特别是考虑到（没有）外部压力施加、熔炉停留时间、温度、焊料材料、焊料材料沉积的方法、和扩散焊料结合厚度，可如上所述来完成熔炉工艺。
图10示出了根据一个实施方式的熔炉工艺。将承载件15和半导体芯片10，和可选地，接触夹25，例如，如在图1C、2B、3B、5B和9A-9B中所示的，称为配置X。将配置X放置在运输机31上。例如，可通过步进电动机来驱动运输机31，并且在图10中，在通过箭头P指示的方向中移动配置X。在配置X放置在运输机31上之后，配置X经过隧道式熔炉501。在隧道式熔炉501中，焊料材料的层13、16、21暴露于加热，以便获得最大的温度T。如果使用连续工艺（即，利用恒定速度来驱动运输机31），则可通过运输机31的速度来控制配置X在隧道式熔炉50_1中的停留时间，或如果使用半连续工艺，则通过运输机在间歇的操作中停止期间的时间间隔来控制。停留时间应该足够大，以便允许焊料材料到金属间相的完全转变，并且例如，可在30s到300s之间，或更具体地，在60s到120s之间。
图11示出了用于焊接配置X的另外的熔炉工艺的示意图。这里，将配置X放置在一个或更多个料斗（magazines）36中。随后，可将料斗36和可能地另外的料斗36放置在或引入炉子50_2中。在炉子50_2中，类似于隧道式熔炉50_1，将焊料材料的层13、16、21暴露于加热，以便获得最大温度T。在如上提及的停留时间消逝之后，从炉子50_2除去一个或更多料斗36。
尽管此处已经说明和描述了具体实施方式，但是本领域技术人员应该理解，在不脱离本发明的范围的情况下，多种替换和/或等价的实施方式可代替示出和描述的具体实施方式。本申请旨在涵盖此处讨论的具体实施方式的任何改变或变化。因此，仅仅用于通过权利要求及其等价物来限制本发明。

Claims (25)

1.一种方法，包括：
提供具有第一主表面和第二主表面的半导体芯片；
将所述半导体芯片放置在承载件上，其中所述半导体芯片的所述第一主表面面向所述承载件，其中在所述第一主表面与所述承载件之间设置焊料材料的第一层；
将包括第一接触区域的接触夹设置在所述半导体芯片上，其中所述第一接触区域面向所述半导体芯片的所述第二主表面，其中在所述第一接触区域与所述第二主表面之间设置焊料材料的第二层；并且之后
将热施加于焊料材料的所述第一层和所述第二层，从而由焊料材料的所述第一层形成第一扩散焊料结合层并且由焊料材料的所述第二层形成第二扩散焊料结合层。
2.根据权利要求1所述的方法，其中，所述承载件包括引线框架。
3.根据权利要求1所述的方法，其中，所述半导体芯片包括功率半导体芯片。
4.根据权利要求1所述的方法，其中，所述第二扩散焊料结合层具有等于或小于10μm的厚度。
5.根据权利要求1所述的方法，其中，施加热包括将所述承载件、所述半导体芯片和所述接触夹放置在炉子中。
6.根据权利要求5所述的方法，其中，当在所述炉子中时，不将外部压力施加于所述承载件、所述半导体芯片和所述接触夹。
7.根据权利要求5所述的方法，其中，通过所述炉子施加于焊料材料的所述第一层和所述第二层的最大温度在250℃到350℃之间。
8.根据权利要求5所述的方法，其中，焊料材料的所述第一层和所述第二层位于所述炉子中的停留时间在30秒到300秒之间。
9.根据权利要求1所述的方法，其中，所述接触夹的所述第一接触区域和所述半导体芯片的所述第二主表面由相同的金属材料构成。
10.根据权利要求9所述的方法，其中，所述金属材料是Cu、Ni、NiSn、Au、Ag、Pt、Pd、或这些金属中的一种或多种的合金中的一种。
11.根据权利要求1所述的方法，其中，所述接触夹包括第二接触区域并且所述承载件包括引线，所述方法进一步包括：
当将所述接触夹放置在所述半导体芯片上时，将所述第二接触区域放置在所述引线上，其中在所述第二接触区域和所述引线之间设置焊料材料的第三层。
12.根据权利要求11所述的方法，进一步包括：
在将热施加于焊料材料的所述第一层和所述第二层的同时，将热施加于焊料材料的所述第三层，从而形成第三扩散焊料结合层。
13.根据权利要求1所述的方法，其中，焊料材料的所述第一层和所述第二层各自包括直径在1到30μm之间的金属颗粒。
14.根据权利要求1所述的方法，其中，焊料材料的所述第一层和所述第二层中的至少一个包括大于80％含量的Sn。
15.根据权利要求1所述的方法，其中，焊料材料的所述第一层和所述第二层中的至少一个包括Sn、SnAg、SnAu、In、InAg、和InAu中的一种。
16.一种方法，包括：
提供承载件；
将第一焊料沉积物施加于所述承载件；
将半导体芯片放置在所述第一焊料沉积物上；
将第二焊料沉积物施加于所述半导体芯片；
将接触夹放置在所述第二焊料沉积物上；并且之后
将热施加于所述第一焊料沉积物和所述第二焊料沉积物，从而在所述承载件、所述半导体芯片和所述接触夹之间形成扩散焊料结合。
17.根据权利要求16所述的方法，其中，施加热包括将所述承载件、所述半导体芯片和所述接触夹放置在炉子中。
18.一种方法，包括：
提供具有第一主表面和第二主表面的半导体芯片；
将所述半导体芯片放置在承载件上，其中所述半导体芯片的第一主表面面向所述承载件，其中在所述第一主表面和所述承载件之间设置焊料材料的第一层；以及
将所述承载件和所述半导体芯片放置到炉子中，从而将热施加于焊料材料的所述第一层，从而在所述承载件与所述半导体芯片之间形成扩散焊料结合。
19.根据权利要求18所述的方法，其中，通过所述炉子施加于焊料材料的所述第一层的最大温度在250℃到350℃之间。
20.根据权利要求18所述的方法，其中，焊料材料的所述第一层位于所述炉子中的停留时间在30秒到300秒之间。
21.根据权利要求18所述的方法，其中，当在所述炉子中时，不将外部压力施加于所述承载件和所述半导体芯片。
22.一种半导体装置，包括：
承载件；
安装在所述承载件上的半导体芯片；
在所述承载件和半导体芯片之间的第一焊料结合层；
安装在所述半导体芯片上的接触夹；以及
在所述半导体芯片和所述接触夹之间延伸的第二焊料结合层，其中所述第一焊料结合层和所述第二焊料结合层是扩散焊料结合并且所述第一焊料结合层和第二焊料结合层各自具有等于或小于10μm的厚度。
23.根据权利要求22所述的半导体装置，其中，所述第一焊料结合层和所述第二焊料结合层的厚度等于或小于5μm。
24.根据权利要求22所述的半导体装置，其中，所述第一焊料结合层和所述第二焊料结合层中的至少一个包括大于80％含量的Sn。
25.一种半导体装置，包括：
承载件；
安装在所述承载件上的半导体芯片；和
在所述承载件和半导体芯片之间延伸的第一焊料结合层，其中所述第一焊料结合层是扩散焊料结合并且具有等于或小于10μm的厚度。
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Application publication date: 20130814