CN106098646B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106098646B
CN106098646B CN201610268559.1A CN201610268559A CN106098646B CN 106098646 B CN106098646 B CN 106098646B CN 201610268559 A CN201610268559 A CN 201610268559A CN 106098646 B CN106098646 B CN 106098646B
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conductor layer
semiconductor device
volume
equal
insulation board
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CN106098646A (zh
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吉田博
大坪义贵
石桥秀俊
中原贤太
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明提供一种具有高散热性且能够对以热应力为起因的翘曲进行抑制的半导体装置。第1导体层(4)设置在绝缘板(12)的第1面(S1)之上，具有第1体积。第2导体层(2)设置在绝缘板(12)的第2面(S2)之上，具有第2体积。第3导体层(3)设置在绝缘板(12)的第2面(S2)之上，具有第3体积。第3导体层具有比第2导体层厚的安装区域(3M)。第2体积及第3体积之和大于或等于第1体积的70％且小于或等于130％。半导体芯片(1)设置在安装区域(3M)之上。封装部(10)由绝缘体制成，在壳体(9)内将半导体芯片(1)封装。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，特别涉及具有在电路基板之上设置的半导体芯片的半导体装置。
背景技术
为了实现低碳社会，在半导体装置的领域，对能够有助于能量效率的提高的功率设备的期待提高。功率设备领域所使用的半导体芯片不断地高集成化，另外，变得以更高速进行动作。因此，半导体芯片的功率密度变高，另外，其发热量也变大。与之相对应地，对半导体装置要求高的散热性能。散热性能大幅依赖于安装半导体芯片的电路基板。
根据日本特开2007-134563号公报(专利文献1)，公开了一种电路基板，其具有陶瓷基板和利用蚀刻形成的金属电路图案。在陶瓷基板的背面接合金属层。该金属层用于在该金属层之上接合散热板。另外，在该公报中，鉴于在功率模块的功率部和控制部流过元件的电流量不同这一点，指出了需要在1个基板之上形成金属电路厚的部分和薄的部分。
根据日本特开2007-201346号公报(专利文献2)，指出了金属化层(金属层)与散热器(散热板)经由焊料接合的情况下的问题。具体地说，指出了由于焊料层的存在而不能充分地发挥散热器的散热性。因此，在该公报记载的技术中，在陶瓷基板的表面形成由金属颗粒成分的烧结体构成的厚膜的散热性导体电路。
专利文献1：日本特开2007-134563号公报
专利文献2：日本特开2007-201346号公报
关于电路基板，电路图案与支撑该电路图案的绝缘板由不同的材料制成。因此，如果半导体装置的温度变化，则以不同材料间的热膨胀系数的差异为起因，电路基板发生翘曲。在上述各公报记载的技术中，未考虑抑制电路基板的翘曲。
发明内容
本发明就是为了解决如上述的课题而提出的，其目的在于提供一种具有高散热性且能够对以热应力为起因的翘曲进行抑制的半导体装置。
本发明的半导体装置具有：壳体、外部端子、绝缘板、第1导体层、第2导体层、第3导体层、半导体芯片、封装部、以及配线部。外部端子安装于壳体。绝缘板具有第1面和与第1面相反的被壳体包围的第2面。第1导体层设置在绝缘板的第1面之上，由一种导体材料制成，具有第1体积。第2导体层设置在绝缘板的第2面之上，由一种导体材料制成，具有第2体积。第3导体层与第2导体层分离地设置在绝缘板的第2面之上，由一种导体材料制成，具有第3体积。第3导体层具有比第2导体层厚的安装区域。第2体积及第3体积之和大于或等于第1体积的70%且小于或等于130%。半导体芯片设置在第3导体层之上。封装部由绝缘体制成，在壳体内将半导体芯片封装。配线部穿过封装部内，将外部端子及第2导体层中的至少某个与半导体芯片短接。
发明的效果
根据本发明，半导体芯片配置在比第2导体层厚的安装区域之上，从而相比于安装区域具有与第2导体层的厚度相同的厚度的情况，能够提高散热性，特别是能够抑制瞬态热阻。另外，在绝缘板的第2面之上设置的第2及第3导体层的体积之和大于或等于在绝缘板的第1面之上设置的第1导体层的体积的70%且小于或等于130%，从而绝缘板的第1面侧的热应力与第2面侧的热应力之间的差异变小。由此，能够抑制绝缘板的翘曲。综上所述，得到具有高散热性且能够对以热应力为起因的翘曲进行抑制的半导体装置。
附图说明
图1是示意性地表示本发明的实施方式1中的半导体装置的结构的剖视图。
图2表示图1的半导体装置所具有的电路基板的结构，是沿图3的线II—II的示意剖视图。
图3是示意性地表示图1的半导体装置所具有的电路基板的结构的俯视图。
图4是表示对比例的半导体装置的结构的剖视图。
图5是表示图4的半导体装置的瞬态热阻的例子的曲线图。
图6是表示图1的半导体装置的瞬态热阻的例子的曲线图。
图7是表示体积V2及V3之和相对于体积V1的比率、与绝缘板的翘曲量之间的关系的例子的曲线图。
图8是示意性地表示本发明的实施方式2中的半导体装置所具有的电路基板的结构的剖视图。
图9是示意性地表示本发明的实施方式3中的半导体装置所具有的电路基板的结构的俯视图。
图10是图9的虚线部X的放大图。
图11是沿图10的线XI—XI的示意局部剖视图。
图12是示意性地表示本发明的实施方式4中的半导体装置所具有的电路基板的结构的俯视图。
图13是示意性地表示本发明的实施方式5中的半导体装置所具有的电路基板的结构的俯视图。
图14是图13的虚线部XIV的放大图。
图15是沿图14的线XV—XV的示意局部剖视图。
图16是沿图14的线XVI—XVI的示意局部剖视图。
标号的说明
S1下表面（第1面），S2上表面（第2面），V1～V3第1～第3体积，1半导体芯片，2电路图案（第2导体层），3电路图案（第3导体层），4电路图案（第1导体层），3M安装区域，3S台阶，5a、5b凹坑部，6导线，7信号端子（外部端子），8主端子（外部端子），9壳体，10封装部，11焊料部，12绝缘板，13a、13b狭缝部，101～105电路基板，501半导体装置。
具体实施方式
下面，基于附图对本发明的实施方式进行说明。
<实施方式1>
（结构）
参照图1，本实施方式的半导体装置501具有：壳体9、信号端子7（外部端子）、主端子8（外部端子）、半导体芯片1、焊料部11、封装部10、导线6（配线部）、以及电路基板101。进一步参照图2及图3，电路基板101具有：绝缘板12、电路图案4（第1导体层）、电路图案2（第2导体层）、以及电路图案3（第3导体层）。此外，在图3中，除了电路基板101的形状，还以虚线示出了电路图案3的安装区域3M，另外，以双点划线示出了半导体芯片1。
绝缘板12由例如氧化铝、氮化硅或者氮化铝陶瓷制成。绝缘板12具有下表面S1（第1面）和与下表面S1相反的被壳体9包围的上表面S2（第2面）。
电路图案4设置在绝缘板12的下表面S1之上。也可以在电路图案4之上安装冷却鳍片等冷却器（未图示）。冷却器例如可以通过导热脂进行安装。电路图案2设置在绝缘板12的上表面S2之上。电路图案2成为半导体装置501的电路的一部分。电路图案3与电路图案2分离地设置在绝缘板12的上表面S2之上。电路图案3具有比电路图案2厚的安装区域3M。优选安装区域3M具有大于或等于0.6mm的厚度。电路图案2～4由一种导体材料制成，例如利用铜或者铝制成。此外，在本实施方式中，如图2所示，电路图案3具有平坦的表面，因此不存在沿表示安装区域3M的虚线（图3）的特殊形状。
电路图案4具有体积V1（第1体积），电路图案2具有体积V2（第2体积），电路图案3具有体积V3（第3体积）。体积V2及体积V3之和大于或等于体积V1的70％且小于或等于130％。
半导体芯片1设置在电路图案3的安装区域3M之上。具体地说，半导体芯片1通过焊料部11接合在安装区域3M之上。关于半导体芯片1，典型的是如图3所示，具有拥有4个角的四边形状。
壳体9由绝缘体制成，优选由树脂制成，例如由PPS(Poly Phenylene Sulfide：聚苯硫醚)或者PBT(Polybutylene Terephthalate：聚对苯二甲酸丁二酯)制成。
信号端子7及主端子8安装于壳体9。信号端子7及主端子8用于半导体装置501的与外部的电连接。具体地说，信号端子7用于半导体芯片1的控制信号的输入，主端子8用于半导体芯片1的主电压或主电流的输入输出。
封装部10在壳体9内将半导体芯片1、电路图案2及3封装。封装部10由具有比绝缘板12的线膨胀系数大的线膨胀系数的绝缘体制成，例如由硅凝胶(线膨胀系数200～350ppm/K左右)或者环氧树脂制成。优选封装部10由具有大于或等于9ppm/K且小于或等于12ppm/K的线膨胀系数的热硬化性环氧树脂制成。
导线6穿过封装部10内。导线6将信号端子7、主端子8以及电路图案2中的至少某个与半导体芯片1短接。
(对比例)
参照图4，在对比例的半导体装置500的电路基板100，代替上述电路图案3而设置有电路图案3Z。电路图案3Z及2是通过对利用钎焊剂粘合于绝缘板12的均匀厚度的金属板进行蚀刻而形成的。因此，电路图案3Z具有与电路图案2的厚度相同的厚度。另外，为了使该蚀刻变得容易，该厚度设为小于或等于0.5mm。
图5表示从在电路图案3Z(电路基板100的上表面)之上安装有半导体芯片1的部位向在电路图案4(电路基板100的下表面)之上安装有冷却鳍片(未图示)的部位的散热路径的瞬态热阻、与半导体芯片1的散热时间之间的关系的实验结果。例如0.1秒的瞬态热阻为3.5K/W。作为降低该值的方法，通常将具有作为散热器的功能的其他部件经由焊料搭载至电路图案3之上，或者，在电路图案4之上经由焊料而设置铜基座板。
另外，电路基板通常具有下述结构，即，利用铜(线膨胀系数18ppm/K左右)等的电路图案夹着氮化铝(线膨胀系数4.5ppm/K左右)或氮化硅(线膨胀系数：2.5ppm/K左右)等的绝缘板。即，绝缘板与电路图案之间存在线膨胀系数的失配。因此，可能发生以温度变化为起因的应力即热应力。如果在电路基板100的上表面与下表面之间发生热应力的失衡，则电路基板100发生翘曲。关于包含电路图案2及3Z在内的图案，由于是与半导体装置500所要求的电路相对应地进行图案化，因此并不是存在于绝缘板12的上表面的大部分。另一方面，电路图案4具有单纯地将绝缘板12的背面的大致整体覆盖那样的图案(满铺图案)。如此，由于绝缘板12的下表面之上的电路图案4的面积与绝缘板12的上表面之上的电路图案2及3Z的面积之间的差异大，因此容易在电路基板100发生以热应力为起因的翘曲。
(实施例)
图6表示针对半导体装置501(图1)的、从在电路图案3(电路基板101的上表面)之上安装有半导体芯片1的部位向在电路图案4(电路基板101的下表面)之上安装有冷却鳍片(未图示)的部位的散热路径的瞬态热阻、与半导体芯片1的散热时间之间的关系的实验结果。半导体装置501与半导体装置500相比具有较低的瞬态热阻。例如在0.1秒处，半导体装置500具有瞬态热阻3.5K/W(图5)，而半导体装置501具有瞬态热阻3.0K/W(图6)。
图7表示电路图案2的体积V2及电路图案3的体积V3之和相对于电路图案4的体积V1的比率、与发生由半导体芯片1引起的升温时的绝缘板12的翘曲量之间的关系的实验结果。在这里，正的翘曲表示向绝缘板12的下表面侧(电路图案4侧)的翘曲，负的翘曲表示向绝缘板12的上表面侧(电路图案2及3侧)的翘曲。可知通过将比率设为大于或等于70％能够显著地抑制正的翘曲。另外，可知通过将比率设为小于或等于130％能够显著地抑制负的翘曲。
(效果的总结)
根据本实施方式，半导体芯片1配置在比电路图案2厚的安装区域3M之上，从而相比于安装区域3M具有与电路图案2的厚度相同的厚度的情况，能够提高散热性，特别是能够抑制瞬态热阻。另外，在绝缘板12的上表面S2之上设置的电路图案2及电路图案3的体积之和V2+V3大于或等于在绝缘板12的下表面S1之上设置的电路图案4的体积V1的70％且小于或等于130％，从而绝缘板12的下表面S1侧的热应力与上表面S2侧的热应力之间的差异变小。由此，能够抑制绝缘板12的翘曲。综上所述，得到具有高散热性且能够对以热应力为起因的翘曲进行抑制的半导体装置501。
特别地，在电路图案4之上安装有冷却鳍片的情况下，如果由于电路基板101的翘曲而在电路图案4与冷却鳍片之间产生间隙，则由冷却鳍片实现的冷却效果降低。因此，通过如上所述地抑制翘曲，能够抑制冷却鳍片的冷却效果的降低。
电路图案2比安装区域3M薄。由此，相比于电路图案2也具有与安装区域3M的厚度相同的厚度的情况，能够抑制制造成本。
在电路图案3的安装区域3M具有大于或等于0.6mm的厚度的情况下，电路基板101的散热性更充分地得到提高。
在封装部10由具有大于或等于9ppm/K且小于或等于12ppm/K的线膨胀系数的热硬化性环氧树脂制成的情况下，能够使封装部10的线膨胀系数更接近于具有电路图案4、电路图案2、电路图案3以及绝缘板12的电路基板101的线膨胀系数。由此，能够抑制以温度变化为起因的半导体装置501的翘曲。
关于导线6，由于其整体被约束在封装部10中，因此在热膨胀收缩时与封装部10一起进行伸缩。另一方面，导线6具有与电路基板101接合的端部。因此，在发生以半导体芯片1的发热或者半导体装置501的保存温度的变动为起因的热膨胀收缩时，以电路基板101及封装部10之间的线膨胀系数的差异为起因，有可能对导线6的端部施加大的应力。如上所述，在封装部10由具有大于或等于9ppm/K且小于或等于12ppm/K的线膨胀系数的热硬化性环氧树脂制成的情况下，由于上述的线膨胀系数的差异受到抑制，因此能够对施加于导线6的端部的应力的大小进行抑制。从而，导线6的接合部的寿命提高。
<实施方式2>
参照图8，关于本实施方式的半导体装置的电路基板102，电路图案3在安装区域3M的外侧具有台阶3S。优选如图所示，通过台阶3S，使电路图案3的表面高度从安装区域3M的外侧朝向安装区域3M变高。换言之，关于电路图案3，优选与位于安装区域3M的外侧的外周部相比，安装区域3M更厚。此外，由于上述以外的结构与上述的实施方式1的结构大致相同，因此对相同或相应的要素标注相同的标号，省略重复的说明。
根据本实施方式，在利用焊料部11(图1)进行接合的半导体芯片1的焊接时，能够在台阶3S的部位阻止焊料的流动。由此，在安装区域3M的周围防止焊料不必要地扩展。由此，能够对由焊料部11和封装部10形成的密接性低的界面的面积进行抑制。从而，抑制封装部10从电路图案3的剥离。
<实施方式3>
参照图9～图11，关于本实施方式的半导体装置的电路基板103，电路图案3在安装区域3M的外侧具有凹部。具体地说，电路图案3在安装区域3M的外侧具有凹坑部5a。优选凹坑部5a在深度方向具有倒锥形状(参照图11中的凹坑部5a的下部)。封装部10(图1)进入至凹坑部5a内。此外，由于上述以外的结构与上述的实施方式1的结构大致相同，因此对相同或相应的要素标注相同的标号，省略重复的说明。
根据本实施方式，在形成封装部10时，具体地说，在为了形成封装部10而使树脂流入至电路基板103之上时，封装部10进入至凹坑部5a内。由此，抑制封装部10从电路图案3的剥离。在凹坑部5a具有倒锥形状的情况下，利用其锚固效果，更可靠地抑制剥离。
另外，以半导体芯片1的发热或者半导体装置的保存温度的变动为起因的、电路图案3的边缘附近处的热应力，因为在安装区域3M周围设置的凹坑部5a而得到缓和。由此，缓和对电路图案3的边缘施加的应力。因此，能够抑制以反复施加这样的应力为起因的电路图案3的剥离的发生。
关于导线6(图1)，由于其整体被约束在封装部10(图1)中，因此在热膨胀收缩时与封装部10一起进行伸缩。另一方面，导线6具有与电路基板103(图9)接合的端部。因此，在发生以半导体芯片1的发热或者半导体装置的保存温度的变动为起因的热膨胀收缩时，以电路基板103及封装部10之间的线膨胀系数的差异为起因，有可能对导线6的端部施加大的应力。如上所述，利用凹坑部5a，封装部10与电路基板103相互得到约束，从而在由于半导体装置的温度变化而引起的热膨胀收缩时，抑制封装部10的伸缩与电路基板103的伸缩之间的差异。由此，能够对施加于导线6的端部的应力的大小进行抑制。从而，导线6的接合部的寿命提高。
<实施方式4>
参照图12，关于本实施方式的半导体装置的电路基板104，电路图案3的凹部除了包含所述的凹坑部5a，还包含分别沿半导体芯片1的4个角延伸的4个狭缝部13a。此外，也可以在俯视观察时(图12)，在半导体芯片1与狭缝部13a之间设置有间隔。
此外，由于上述以外的结构与所述的实施方式3的结构大致相同，因此对相同或相应的要素标注相同的标号，省略重复的说明。
根据本实施方式，在利用焊料部11(图1)进行接合的半导体芯片1的焊接时，能够在半导体芯片1的4个角的附近处利用狭缝部13a(图12)阻止焊料的流动。由此，抑制电路图案3之上的半导体芯片1的安装位置的偏离。另外，利用狭缝部13a缓和安装区域3M周围的应力。由此，能够缓和对电路图案3的图案的边缘施加的应力。
此外，这些效果即使没有凹坑部5a也能够得到。
<实施方式5>
参照图13～图16，关于本实施方式的半导体装置的电路基板105，电路图案3的凹部具有狭缝部13b和多个凹坑部5b。多个凹坑部5b是与电路图案3的缘部分离而设置的。狭缝部13b将多个凹坑部5b相互连接，且延伸至电路图案3的缘部。此外，由于上述以外的结构与上述的实施方式1的结构大致相同，因此对相同或相应的要素标注相同的标号，省略重复的说明。
根据本实施方式，在形成封装部10(图1)时，具体地说，在为了形成封装部10而使树脂流入至电路基板105之上时，凹坑部5b内的空气容易穿过狭缝部13b排出。由此，封装部10更充分地进入至凹坑部5b内。从而，更充分地抑制封装部10从电路图案3的剥离。在封装部10由环氧树脂制成的情况下，此效果特别大。
此外，本发明可以在其发明的范围内，将各实施方式自由地进行组合，或对各实施方式进行适当变形、省略。

Claims (7)

1.一种半导体装置，其具有：
壳体；
外部端子，其安装于所述壳体；
绝缘板，其具有第1面和与所述第1面相反的被所述壳体包围的第2面；
第1导体层，其设置在所述绝缘板的所述第1面之上，由一种导体材料制成，具有第1体积；
第2导体层，其设置在所述绝缘板的所述第2面之上，由所述一种导体材料制成，具有第2体积；以及
第3导体层，其与所述第2导体层分离地设置在所述绝缘板的所述第2面之上，由所述一种导体材料制成，具有第3体积，所述第3导体层具有比所述第2导体层厚的安装区域，所述第2体积及所述第3体积之和大于或等于所述第1体积的70％且小于或等于130％，
所述半导体装置还具有：
半导体芯片，其设置在所述第3导体层的所述安装区域之上；
封装部，其由绝缘体制成，在所述壳体内将所述半导体芯片封装；以及
配线部，其穿过所述封装部内，将所述外部端子及所述第2导体层中的至少某个与所述半导体芯片短接，
所述第3导体层在所述安装区域的外侧具有凹部，
所述第3导体层的所述凹部包含狭缝部和多个凹坑部，该多个凹坑部是与所述第3导体层的缘部分离而设置的，该狭缝部将所述多个凹坑部相互连接且延伸至所述第3导体层的缘部。
2.根据权利要求1所述的半导体装置，其中，
所述第3导体层的所述安装区域具有大于或等于0.6mm的厚度。
3.根据权利要求1所述的半导体装置，其中，
所述第3导体层在所述安装区域的外侧具有台阶。
4.根据权利要求2所述的半导体装置，其中，
所述第3导体层在所述安装区域的外侧具有台阶。
5.根据权利要求1至4中任一项所述的半导体装置，其中，
所述凹部包含在深度方向具有倒锥形状的部分。
6.根据权利要求1至4中任一项所述的半导体装置，其中，
所述封装部由具有大于或等于9ppm/K且小于或等于12ppm/K的线膨胀系数的热硬化性环氧树脂制成。
7.根据权利要求5所述的半导体装置，其中，
所述封装部由具有大于或等于9ppm/K且小于或等于12ppm/K的线膨胀系数的热硬化性环氧树脂制成。
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